SN54LVTH240_16 [TI]
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN54LVTH240_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 驱动 输出元件 |
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SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
SN54LVTH240 . . . J PACKAGE
SN74LVTH240A . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
2OE
1Y1
2A4
1Y2
2A3
1Y3
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
13 2A2
12 1Y4
I
and Power-Up 3-State Support Hot
off
Insertion
11
2A1
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
SN54LVTH240 . . . FK PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
3
2
1 20 19
18
4
5
6
7
8
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
17
16
15
14
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
9 10 11 12 13
description
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) V operation, but with the
CC
capability to provide a TTL interface to a 5-V system environment.
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH240A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
†
logic symbol
1
19
1OE
EN
2OE
EN
11
13
15
17
9
7
5
3
2
18
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
1A1
4
1Y1
1Y2
1Y3
1Y4
16
14
12
1A2
6
1A3
8
1A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
19
11
1OE
2OE
2A1
2
18
16
14
12
9
7
5
3
1A1
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
4
13
15
17
1A2
2A2
2A3
2A4
6
1A3
8
1A4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH240A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH240 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH240A . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH240 SN74LVTH240A
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH240
SN74LVTH240A
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
V
CC
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
2.4
2
2.4
2
V
V
OH
V
= 3 V
CC
CC
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
10
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
10
±1
1
CC
Control inputs
Data inputs
V = V
or GND
±1
CC
I
CC
CC
I
I
µA
V = V
I
1
V
CC
V
CC
V
CC
= 3.6 V
V = 0
I
–5
–5
I
I
= 0, V or V = 0 to 4.5 V
±100
µA
µA
off
I
O
V = 0.8 V
I
75
75
= 3 V
Data inputs
V = 2 V
I
–75
–75
I(hold)
‡
V
V
V
V
= 3.6 V ,
= 3.6 V,
= 3.6 V,
V = 0 to 3.6 V
±500
5
CC
CC
CC
CC
I
I
I
V
= 3 V
5
µA
µA
OZH
O
O
V
= 0.5 V
–5
–5
OZL
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE = don’t care
O
±100
±100
±100
±100
µA
µA
I
OZPU
OZPD
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
CC
= 3 V to 3.6 V,
§
One input at V
– 0.6 V,
or GND
0.2
0.2
∆I
CC
CC
Other inputs at V
CC
C
C
V = 3 V or 0
3
7
3
7
pF
pF
i
I
V
O
= 3 V or 0
o
On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
A
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54LVTH240
SN74LVTH240A
FROM
(INPUT)
TO
(OUTPUT)
V
= 3.3 V
V
= 3.3 V
V
CC
± 0.3 V
CC
V
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
CC
MIN
± 0.3 V
†
MIN
0.9
1.2
1
MAX
4.3
4.7
5.7
5.5
5.1
5.4
MIN
MAX
5.1
4.9
6.7
6.2
5.2
5.4
MIN TYP
MAX
3.8
4
MAX
4.6
4.2
5.6
5
t
t
t
t
t
t
1.1
1.3
1.1
1.4
2
2.2
2.6
2.6
2.7
2.9
3
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
4.6
4.4
4.4
4.3
OE
OE
1.2
1
4.6
4.3
1.1
1.8
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH240, SN74LVTH240A
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679F – DECEMBER 1996 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
PHL
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
Output
1.5 V
1.5 V
1.5 V
t
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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