SN54LVTH373 [TI]
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS; 3.3 -V ABT八路透明D类锁存器具有三态输出
| 型号： | SN54LVTH373 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
SN54LVTH373 . . . J OR W PACKAGE
SN74LVTH373 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
OE
1Q
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
I
and Power-Up 3-State Support Hot
off
8Q
8D
7D
Insertion
1D
2D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
2Q
3Q
16 7Q
15 6Q
14
13
12
11
3D
4D
4Q
GND
6D
5D
5Q
LE
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
SN54LVTH373 . . . FK PACKAGE
(TOP VIEW)
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
Latch-Up Performance Exceeds 500 mA Per
JESD 17
3
2
1 20 19
18
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
4
5
6
7
8
17
16
15
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Ceramic (J)
DIPs
14 6D
9 10 11 12 13
description
These octal latches are designed specifically for low-voltage (3.3-V) V
provide a TTL interface to a 5-V system environment.
operation, but with the capability to
CC
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
1
EN
C1
OE
LE
11
3
2
5
1D
2D
3D
4D
5D
6D
1D
1Q
2Q
3Q
4Q
5Q
6Q
4
7
6
8
9
13
14
12
15
17
18
16
19
7D
8D
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
LE
C1
1D
2
1Q
3
1D
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH373 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH373 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH373 SN74LVTH373
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH373
SN74LVTH373
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
10
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
10
±1
1
CC
Control inputs
V = V
or GND
±1
CC
I
CC
CC
I
I
I
µA
µA
µA
I
V = V
I
1
Data inputs
V
CC
V
CC
V
CC
= 3.6 V
= 0,
V = 0
I
–5
–5
V or V = 0 to 4.5 V
±100
off
I
O
V = 0.8 V
I
75
75
= 3 V
V = 2 V
I
–75
–75
Data inputs
I(hold)
500
–750
‡
V
CC
= 3.6 V ,
V = 0 to 3.6 V
I
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
–5
–5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
±100
±100
±100
±100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
7
3
7
pF
pF
i
I
V
O
= 3 V or 0
o
On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH373
= 3.3 V
SN74LVTH373
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
3
MAX
MIN
3
MAX
MIN
3
MAX
MIN
3
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
1.1
1.7
0.4
2
1.1
1.4
0.4
1.4
switching characteristics over recommended free-air temperature, C = 50 pF (unless otherwise
L
noted) (see Figure 1)
SN54LVTH373
= 3.3 V
SN74LVTH373
FROM
(INPUT)
TO
(OUTPUT)
V
CC
V
CC
= 3.3 V
V
V
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
CC
± 0.3 V
± 0.3 V
†
MIN
1.4
1.4
1.6
1.6
1.2
1.2
1.8
1.8
MAX
4.1
4.1
4.4
4.4
5
MIN
MAX
4.7
4.7
5.1
5.1
6.1
5.7
5.1
4.9
MIN TYP
MAX
3.9
3.9
4.2
4.2
4.8
4.8
4.6
4.5
MIN
MAX
4.5
4.5
4.9
4.9
5.9
5.5
4.9
4.6
t
t
t
t
t
t
t
t
1.5
1.5
1.7
1.7
1.3
1.3
1.9
1.9
2.6
2.6
2.7
2.7
3
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
LE
OE
OE
5
3
4.8
4.8
3
3
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH373, SN74LVTH373
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS689E – MAY 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
S1
S1
500 Ω
From Output
Under Test
t
/t
Open
6 V
PLH PHL
/t
t
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
t
GND
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1999, Texas Instruments Incorporated
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