SN55HVD75DRBREP [TI]
具有 IEC ESD 保护功能的 3.3V 电源 RS-485 | DRB | 8 | -55 to 125;
| 型号： | SN55HVD75DRBREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 IEC ESD 保护功能的 3.3V 电源 RS-485 | DRB | 8 | -55 to 125 |
| 文件： | 总33页 (文件大小：1245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN55HVD75-EP
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
SN55HVD75-EP 具有 IEC ESD 保护功能的 3.3V 电源供电的 RS-485
1 特性
2 应用范围
1
•
总线 I/O 保护
•
•
•
工厂自动化
电信基础设施
运动控制
–
–
–
>±15kV 人体模型 (HBM) 保护
>±12kV IEC 61000-4-2 接触放电
>±4kV IEC61000-4-4 快速瞬态突发
3 说明
•
扩展的工业温度范围
这些器件具有稳健耐用的 3.3V 驱动器和接收器，并且
采用小型封装，可满足工业应用 的严苛要求。。总线
引脚可耐受 ESD 事件，具有针对人体模型和 IEC 接触
放电规范的高级保护。
-55°C 至 125°C
•
•
•
用于噪声抑制的较大接收器滞后 (80mV)
低单元负载可实现超过 200 个节点的连接
低功耗
–
–
低待机电源电流：< 2µA
其中每一款器件都配有一个差分驱动器和一个差分接收
器。这两个器件由 3.3V 单电源供电。驱动器差分输出
和接收器差分输入在内部连接，构成一个适用于半双工
（两线制总线）通信的总线端口。这些器件具备宽共模
电压范围，因此适用于长线缆上的 多点 应用。这些器
件的额定运行温度范围为 -55°C 至 125°C。
运行过程中的 ICC < 1mA 静态电流
•
•
与 3.3V 或 5V 控制器兼容的 5V 耐压逻辑输入
针对以下信号传输速率进行了优化：
250kbps，20Mbps，50Mbps
•
•
采用小型超薄小外形尺寸无引线 (VSON) 封装
支持国防、航天和医疗 应用：
器件信息(1)
–
–
–
–
–
–
–
受控基线
器件型号
封装
VSON (8)
封装尺寸（标称值）
一个组装/测试场所
一个制造场所
SN55HVD75-EP
3.00mm x 3.00mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
在扩展温度范围（-55°C 至 125°C）内可用
延长的产品生命周期
延长产品的变更通知周期
产品可追溯性
典型应用图
R
R
R
R
A
A
B
RE
RE
R
T
R
T
B
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS913
SN55HVD75-EP
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 15
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1 器件支持................................................................ 24
12.2 接收文档更新通知 ................................................. 24
12.3 社区资源................................................................ 24
12.4 商标....................................................................... 24
12.5 静电放电警告......................................................... 24
12.6 Glossary................................................................ 24
13 机械、封装和可订购信息....................................... 24
6.6 Switching Characteristics: 20 Mbps Device, Bit Time
≥50 ns ........................................................................ 6
6.7 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
7
8
4 修订历史记录
Changes from Original (October 2015) to Revision A
Page
•
•
•
•
已删除 通篇数据表中对于 RS-422 的引用.............................................................................................................................. 1
Deleted TJ and VCC test conditions from |VOD|, RL = 100 Ω................................................................................................... 5
Changed |VOD|, RL = 100 Ω minimum from 2 V : to 1.8 V ..................................................................................................... 5
已添加 接收文档更新通知部分至器件和文档支持部分.......................................................................................................... 24
2
Copyright © 2015–2017, Texas Instruments Incorporated
SN55HVD75-EP
www.ti.com.cn
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
5 Pin Configuration and Functions
DRB Package
8-Pin VSON
Top View
VCC
R
1
2
3
4
8
7
6
5
B
RE
DE
D
A
GND
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
A
NO.
6
Bus I/O
Bus I/O
Driver output or receiver input (complementary to B).
Driver output or receiver input (complementary to A).
Driver data input.
B
7
D
4
Digital input
Digital input
Reference potential
Digital output
Digital input
Supply
DE
GND
R
3
Active-high driver enable.
5
Local device ground.
1
Receive data output .
RE
VCC
2
Active-low receiver enable.
3-V to 3.6-V supply.
8
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating range (unless otherwise specified)
(1)
MIN
–0.5
–13
MAX
5.5
UNIT
V
Supply voltage, VCC
Voltage at A or B inputs
16.5
5.7
V
Input voltage at any logic pin
Voltage input, transient pulse, A and B, through 100 Ω
Receiver output current
–0.3
–100
–24
V
100
24
V
mA
°C
°C
Junction temperature, TJ
170
150
Storage temperature, Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±8000
±1500
±300
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
All pins
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
JEDEC standard 22, test method A115 (machine model)
IEC 61000-4-2 ESD (air-gap discharge)(3)
All pins
All pins
Electrostatic
discharge
V(ESD)
Pins 5 to 7
Pins 5 to 7
Pins 5 to 7
Pins 5 to 7
±12000
±12000
±4000
±15000
V
IEC 61000-4-2 ESD (contact discharge)
IEC 61000-4-4 EFT (fast transient or burst)
IEC 60749-26 ESD HBM
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) By inference from contact discharge results, see Application and Implementation.
Copyright © 2015–2017, Texas Instruments Incorporated
3
SN55HVD75-EP
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
www.ti.com.cn
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
VCC
VI
Supply voltage
3.3
3.6
12
Input voltage at any bus terminal (separately or common mode)(1)
High-level input voltage (driver, driver enable, and receiver enable inputs)
Low-level input voltage (driver, driver enable, and receiver enable inputs)
Differential input voltage
–7
2
V
VIH
VIL
VID
IO
VCC
0.8
12
V
0
V
–12
–60
–8
54
V
Output current, driver
60
mA
mA
Ω
IO
Output current, receiver
8
RL
Differential load resistance
60
50
CL
Differential load capacitance
pF
Mbps
°C
°C
1/tUI
Signaling rate
20
125
150
(2)
TA
TJ
Operating free-air temperature (see Thermal Information)
Junction temperature
–55
–55
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables
the driver outputs when the junction temperature reaches 170°C.
6.4 Thermal Information
SN55HVD75-EP
THERMAL METRIC(1)
DRB (VSON)
8 PINS
40.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJC(bot)
RθJB
49.6
3.9
15.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.6
ψJB
15.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015–2017, Texas Instruments Incorporated
SN55HVD75-EP
www.ti.com.cn
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
6.5 Electrical Characteristics
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RL = 60 Ω, 375 Ω on each output to See
1.5
2
–7 V to 12 V
Figure 6
Driver differential output
voltage magnitude
|VOD
|
V
RL = 54 Ω (RS-485)
RL = 100 Ω
1.5
1.8
2
2.5
Change in magnitude of
Δ|VOD
|
driver differential output RL = 54 Ω, CL = 50 pF
voltage
–50
1
0
VCC/2
0
50
3
mV
V
Steady-state common-
mode output voltage
See
Figure 7
VOC(SS)
Change in differential
driver output common-
mode voltage
ΔVOC
–50
50
mV
Center of two 27-Ω load resistors
Peak-to-peak driver
common-mode output
voltage
VOC(PP)
200
15
mV
pF
Differential output
capacitance
COD
Positive-going receiver
differential input voltage
threshold
(1)
VIT+
See
–70
–20
mV
Negative-going receiver
differential input voltage
threshold
(1)
VIT–
–200
50
–150
80
See
mV
mV
Receiver differential
input voltage threshold
VHYS
hysteresis (VIT+ – VIT–
)
Receiver high-level
output voltage
VOH
VOL
IOH = –8 mA
IOL = 8 mA
2.4 VCC – 0.3
0.2
V
V
Receiver low-level
output voltage
0.4
2.75
1
Driver input, driver
enable, and receiver
enable input current
II
–2.75
µA
Receiver output high-
impedance current
IOZ
IOS
VO = 0 V or VCC, RE at VCC
–1
µA
Driver short-circuit
output current
–165
165
150
mA
VCC = 3 V to 3.6 V
or
VCC = 0 V
DE at 0 V
VI = 12 V
VI = –7 V
75
Bus input current
(disabled driver)
II
µA
µA
–100
–40
Driver and receiver
enabled
DE = VCC, RE = GND
No load
750
300
600
0.1
950
500
800
2
Driver enabled,
receiver disabled
DE = VCC, RE = VCC
No load
Supply current
(quiescent)
ICC
Driver disabled,
receiver enabled
DE = GND, RE = GND
No load
Driver and receiver
disabled
DE = GND, D = open
RE = VCC, No load
Supply current
(dynamic)
See Typical Characteristics
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–
.
Copyright © 2015–2017, Texas Instruments Incorporated
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
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6.6 Switching Characteristics: 20 Mbps Device, Bit Time ≥50 ns
over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
Driver differential output rise or
fall time
tr, tf
1
6
7
14
ns
RL = 54 Ω
CL = 50 pF
See Figure 8
tPHL, tPLH
tSK(P)
Driver propagation delay
11
0
17
2
ns
ns
ns
ns
µs
Driver pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
12
10
3
50
20
7
See Figure 9 and
Figure 10
Receiver enabled
Receiver disabled
tPZH, tPZL
Driver enable time
RECEIVER
tr, tf
Receiver output rise or fall time
Receiver propagation delay time CL = 15 pF
5
60
0
10
70
6
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
See Figure 11
Receiver pulse skew, |tPHL – tPLH
|
tPLZ, tPHZ
Receiver disable time
15
10
3
30
50
8
Driver enabled
Driver disabled
See Figure 12
See Figure 13
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
,
Receiver enable time
6
Copyright © 2015–2017, Texas Instruments Incorporated
SN55HVD75-EP
www.ti.com.cn
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
6.7 Typical Characteristics
3.5
3.5
100 W
60 W
V
OH
3
3
2.5
2
2.5
2
1.5
1.5
V
OL
1
0.5
0
1
0.5
0
0
20
40
60
80
100
0
20
I
40
60
- Driver Output Current - mA
80
100
I
- Driver Output Current - mA
O
O
VCC = 3.3 V
DE = VCC
D = 0 V
VCC = 3.3 V
DE = VCC
D = 0 V
Figure 1. Driver Output Voltage vs Driver Output Current
Figure 2. Driver Differential Output Voltage vs Driver Output
Current
40
35
30
25
20
15
10
5
70
60
50
40
30
20
10
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
2
4
6
8
10
12
14
16 18
20
VCC Supply Voltage - V
Signaling Rate - Mbps
TA = 25°C
DE = VCC
RL = 54 Ω
D = VCC
RL = 54 Ω
Figure 3. Driver Output Current vs Supply Voltage
Figure 4. Supply Current vs Signal Rate
3.5
3
2.5
2
VIT- (-7V)
VIT-(0V)
VIT-(12V)
VIT+(-7V)
VIT+(0V)
VIT+(12V)
1.5
1
0.5
0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
Differential Input Voltage (VID) mV
Figure 5. Receiver Output vs Input
Copyright © 2015–2017, Texas Instruments Incorporated
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SN55HVD75-EP
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
www.ti.com.cn
7 Parameter Measurement Information
Input generator rate is 100 kbps, 50% duty cycle, rise or fall time is less than 6 ns, output impedance is 50 Ω.
375 W ±1%
VCC
DE
A
B
D
VOD
0 V or 3 V
60 W ±1%
+
_
–7 V < V(test) < 12 V
375 W ±1%
S0301-01
Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
VA
A
B
RL/2
RL/2
A
B
VB
D
VOD
0 V or 3 V
VOC(PP)
DVOC(SS)
VOC
CL
VOC
S0302-01
Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
50%
50%
A
B
ö
ö
W
W
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3 V
A
B
S1
VO
D
VI
50%
50%
3 V
0 V
DE
0.5 V
RL = 110 W
± 1%
CL = 50 pF ±20%
tPZH
VOH
90%
Input
Generator
CL Includes Fixture
50 W
VI
and Instrumentation
Capacitance
VO
50%
» 0 V
tPHZ
S0304-01
D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
8
Copyright © 2015–2017, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
Parameter Measurement Information (continued)
3 V
RL = 110 W
±1%
» 3 V
A
B
VI
50%
50%
S1
D
VO
3 V
0 V
tPZL
tPLZ
DE
CL = 50 pF ±20%
» 3 V
Input
Generator
VI
50 W
CL Includes Fixture
VO
50%
and Instrumentation
Capacitance
10%
VOL
S0305-01
D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active Low Output and Pullup Load
3 V
A
VI
50%
50%
VO
R
Input
Generator
50 W
0 V
VI
B
tPLH
tPHL
1.5 V
0 V
CL = 15 pF ±20%
VOH
RE
90% 90%
VO
50%
10%
50%
10%
VOL
CL Includes Fixture
tr
tf
and Instrumentation
Capacitance
S0306-01
Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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Parameter Measurement Information (continued)
3 V
DE
VCC
A
B
VO
1 kW ± 1%
CL = 15 pF ±20%
R
D
0 V or 3 V
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
3 V
VI
50%
50%
0 V
tPZH(1)
tPHZ
VOH
D at 3 V
S1 to GND
90%
VO
50%
» 0 V
tPZL(1)
tPLZ
VCC
D at 0 V
S1 to VCC
VO
50%
10%
VOL
S0307-01
Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled
10
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
Parameter Measurement Information (continued)
VCC
A
B
VO
0 V or 1.5 V
1.5 V or 0 V
1 kW ± 1%
CL = 15 pF ±20%
R
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
3 V
VI
50%
0 V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to GND
VO
50%
GND
VCC
tPZL(2)
A at 0 V
B at 1.5 V
S1 to VCC
VO
50%
VOL
S0308-01
Figure 13. Measurement of Receiver Enable Times With Driver Disabled
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8 Detailed Description
8.1 Overview
The SN55HVD75-EP is a low-power, half-duplex RS-485 transceiver available in a speed grade suitable for data
transmission up to 20 Mbps.
This device has active-high driver enables and active-low receiver enables. A standby current of less than 2 µA
can be achieved by disabling both driver and receiver.
8.2 Functional Block Diagram
8.3 Feature Description
Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±12 kV, and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to
±4 kV.
The SN55HVD75-EP half-duplex family provides internal biasing of the receiver input thresholds in combination
with large input threshold hysteresis. At a positive input threshold of VIT+ = –20 mV and an input hysteresis of
VHYS = 50 mV, the receiver output remains logic high under a bus-idle or bus-short condition even in the
presence of 140-mVPP differential noise without the need for external failsafe biasing resistors.
Device operation is specified over a wide ambient temperature range from –55°C to 125°C.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pulldown resistor to ground; thus, when left open, the driver is disabled (high-impedance) by
default. The D pin has an internal pullup resistor to VCC; thus, when left open while the driver is enabled, output A
turns high and B turns low.
Table 1. Driver Function Table
INPUT
ENABLE
OUTPUTS
DESCRIPTION
D
DE
A
B
L
H
H
H
L
Actively drive bus high.
L
X
H
L
H
Z
Z
L
Actively drive bus low.
Driver disabled.
Z
Z
H
X
OPEN
H
Driver disabled by default.
Actively drive bus high by default.
OPEN
12
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output turns low.
If VID is between VIT+ and VIT–, the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VIT+ < VID
ENABLE
OUTPUT
DESCRIPTION
RE
R
H
?
L
Receive valid bus high.
VIT– < VID < VIT+
VID < VIT–
L
Indeterminate bus state.
Receive valid bus low.
Receiver disabled.
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default.
Failsafe high output.
Failsafe high output.
Failsafe high output.
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
D and RE Inputs
DE Input
R Output
Vcc
Vcc
Vcc
3M
1. 5k
1. 5k
D, RE
DE
R
9V
1M
9V
9V
Receiver Inputs
Driver Outputs
Vcc
Vcc
R2 R2
R1
R1
A
A
B
R
B
16V
R3 R3
16V
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Equivalent Input and Output Circuit Diagrams
Copyright © 2015–2017, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN55HVD75-EP is a half-duplex RS-485 transceiver commonly used for asynchronous data transmission.
The driver and receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
B
RE
A
B
RE
A
B
DE
D
DE
D
DE
D
D
D
D
a) Independent driver and
receiver enable signals
b) Combined enable signals for
use as directional control pin
c) Receiver always on
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
14
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9.2 Typical Application
An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over
long cable lengths.
R
R
R
R
A
B
A
B
RE
RE
R
T
R
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Typical RS-485 Network With SN55HVD75-EP Transceivers
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and
RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 17. Cable Length vs Data Rate Characteristic
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Typical Application (continued)
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where:
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
Per Equation 1, Table 3 shows the maximum cable-stub lengths for the minimum driver output rise times of the
SN55HVD75-EP half-duplex transceiver for a signal velocity of 78%.
Table 3. Maximum Stub Length
MAXIMUM STUB LENGTH
MINIMUM DRIVER OUTPUT RISE TIME
(ns)
DEVICE
(m)
(ft)
SN55HVD75-EP
2
0.05
0.16
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a receiver input current of 1 mA at 12 V, or a load impedance of approximately 12 kΩ. Because the
SN55HVD75-EP has a receiver input current of 150 µA at 12 V, they are 3/20 UL transceivers, and no more than
213 transceivers should be connected to the bus.
9.2.1.4 Receiver Failsafe
The differential receiver is failsafe to invalid bus states caused by:
•
•
•
Open bus conditions such as a disconnected connector
Shorted bus conditions such as cable damage shorting the twisted-pair together, or
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high so that the output of the receiver is
not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input-indeterminate range
does not include 0-V differential. To comply with RS-485 standards, the receiver output must output a high when
the differential input VID is more positive than 200 mV, and must output a low when VID is more negative than
–200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and VHYS (the
separation between VIT+ and VIT–). As shown in Electrical Characteristics, differential signals more negative than
–200 mV will always cause a low receiver output, and differential signals more positive than 200 mV will always
cause a high receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT+ threshold of –20 mV, and the
receiver output will be high. Only when the differential input is more than VHYS below VIT+ will the receiver output
transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition includes
the receiver hysteresis value, VHYS, as well as the value of VIT+
.
16
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
R
V
HYS-min
50mV
V
ID
- mV
-70
-20
0
70
V
= 140mVpp
noise-max
Figure 18. Noise Immunity
9.2.1.5 Transient Protection
The bus pins of the SN55HVD75-EP transceiver family possess on-chip ESD protection against ±15-kV human
body model (HBM) and ±12-kV IEC 61000-4-2 contact discharge. The IEC-ESD test is far more severe than the
HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD, of the IEC-
model produce significantly higher discharge currents than the HBM-model.
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap
testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact
discharge test results.
R
R
D
C
40
35
30
25
20
15
10
5
50M
(1M)
330ꢀ
10kV IEC
(1.5k)
High-Voltage
Pulse
Generator
Device
Under
Test
150pF
C
S
(100pF)
10kV HBM
0
0
50
100
150
200
250
300
Time - ns
Copyright © 2016, Texas Instruments Incorporated
Figure 19. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur due to human contact with connectors and cables. Designers may choose to implement
protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 20 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left-hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right-hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
Copyright © 2015–2017, Texas Instruments Incorporated
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3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
Figure 20. Power Comparison of ESD, EFT, and Surge Transients
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy which heats and destroys the protection cells, thus destroying the transceiver.
Figure 21 shows the large differences in transient energies for single ESD, EFT, and surge transients, as well as
for an EFT pulse train, commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 21. Comparison of Transient Energies
18
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
9.2.2 Detailed Design Procedure
9.2.2.1 External Transient Protection
To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is necessary. Figure 22 suggests two circuits that provide protection against light and heavy surge transients, in
addition to ESD and EFT transients. Table 4 presents the associated bill of materials.
Table 4. Bill of Materials
DEVICE
XCVR
FUNCTION
3.3-V, 250-kbps RS-485 transceiver
10-Ω, pulse-proof thick-film resistor
Bidirectional 400-W transient suppressor
Bidirectional surge suppressor
ORDER NUMBER
SN55HVD75DRBREP
CRCW060310RJNEAHP
CDSOT23-SM712
MANUFACTURER
TI
R1, R2
Vishay
Bourns
Bourns
TVS
TBU1, TBU2
TBU-CA-065-200-WH
200-mA Transient blocking unit, 200-V, metal-oxide
varistor
MOV1, MOV2
MOV-10D201K
Bourns
Vcc
10k
Vcc
Vcc
Vcc
0.1ꢀF
10k
0.1ꢀF
TBU1
MOV1
R1
R1
1
2
3
4
8
7
6
5
1
8
7
6
5
RxD
R
Vcc
B
RxD
MCU
R
Vcc
B
TVS
TVS
2
RE
DE
D
RE
MCU
DIR
XCVR
XCVR
3
4
A
DIR
TxD
DE
D
A
MOV2
TBU2
TxD
GND
GND
R2
R2
10k
10k
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Transient Protections against ESD, EFT, and Surge Transients
The left-hand circuit provides surge protection of ≥500-V surge transients, while the right-hand circuit can
withstand surge transients of up to 5 kV.
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www.ti.com.cn
9.2.2.2 Isolated Bus Node Design
Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their
disruptive impact on signal integrity. An isolated bus node typically includes a microcontroller that connects to the
bus transceiver via a multi-channel, digital isolator (Figure 23).
0.1ꢀF
2
MBR0520L
1:1.33
3.3V
ISO
3
1
4
1
2
Vcc
D2
IN
OUT
TLV70733
EN GND
SN6501
D1
10ꢀF 0.1ꢀF
10ꢀF
3
GND
4,5
10ꢀF
MBR0520L
L1
N
ISO-BARRIER
3.3V
0.1ꢀF
0.1ꢀF
PSU
PE
0.1ꢀF
0.1ꢀF
1
16
4.7k
4.7k
Vcc1
Vcc2
PE
2
7
6
3
4
5
10
11
14
13
12
8
EN1 ISO7241 EN2
DVcc
16
11
12
15
1
2
3
4
Vcc
OUTD
INA
IND
OUTA
OUTB
UCA0RXD
P3.0
R
R1
R2
5
6
7
6
XOUT
XIN
B
A
RE
MSP430
F2132
SN65
HVD72
INB
P3.1
DE
D
INC
OUTC
GND2
9,15
UCA0TXD
DVss
4
GND2
5
GND1
2,8
TVS
R
C
HV
HV
Short thick Earth wire or Chassis
PE
island
Protective Earth Ground,
Equipment Safety Ground
R1,R2, TVS: see Table1
= 1Mꢀ, 2kV high-voltageresistor, TT electronics, HVC 2010 1M0 G T3
R
HV
= 4.7nF, 2kV high-voltagecapacitor, NOVACAP, 1812 B 472 K 202 N T
C
HV
Floating RS-485 Common
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Isolated Bus Node with Transient Protection
Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.
Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are
pulled up via 4.7-kΩ resistors to limit their input currents during transient events.
While the transient protection is similar to the one in Figure 22 (left circuit), an additional high-voltage capacitor is
used to divert transient energy from the floating RS-485 common further toward Protective Earth (PE) ground.
This is necessary as noise transients on the bus are usually referred to Earth potential.
RHV refers to a high voltage resistor, and in some applications even a varistor. This resistance is applied to
prevent charging of the floating ground to dangerous potentials during normal operation.
Occasionally varistors are used instead of resistors to rapidly discharge CHV, if it is expected that fast transients
might charge CHV to high-potentials.
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire
connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically
the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are
connecting to the chassis at the other end.
20
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
9.2.3 Application Curve
RL = 60 Ω
Figure 24. 20 Mbps
Copyright © 2015–2017, Texas Instruments Incorporated
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www.ti.com.cn
10 Power Supply Recommendations
To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 is a linear voltage regulator
suitable for the 3.3-V supply.
See SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0) for isolated power supply designs.
11 Layout
11.1 Layout Guidelines
On-chip IEC ESD protection is sufficient for laboratory and portable equipment but often insufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-
frequency layout techniques must be applied during PCB design.
For a successful PCB design, start with the design of the protection circuit in mind.
•
•
Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
•
•
•
•
•
Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into
the transceiver and prevent it from latching up.
•
While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to 200 mA.
22
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SN55HVD75-EP
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ZHCSE84A –OCTOBER 2015–REVISED FEBRUARY 2017
11.2 Layout Example
5
Via to ground
Via to VCC
C
4
R
R
R
6
6
1
R
R
7
R
MCU
5
TVS
SN65HVD7x
5
Figure 25. SN55HVD75-EP Half-Duplex Layout Example
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12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏
24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN55HVD75DRBREP
V62/15608-01XE
ACTIVE
ACTIVE
SON
SON
DRB
DRB
8
8
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
HVD75M
HVD75M
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN55HVD75DRBREP
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SON DRB
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
SN55HVD75DRBREP
8
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DRB0008B
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.65 0.05
(0.2) TYP
4
5
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.1
C A B
C
0.5
0.3
8X
(OPTIONAL)
0.05
4218876/A 12/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.575)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218876/A 12/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.63)
SYMM
(1.06)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218876/A 12/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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