SN65C1154DW-00 [TI]
LINE TRANSCEIVER, PDSO20;
| 型号： | SN65C1154DW-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LINE TRANSCEIVER, PDSO20 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总16页 (文件大小：870K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
SN65C1154 . . . N PACKAGE
SN75C1154 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Very Low Power Consumption . . .
5 mW Typ
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
V
CC
DD
1RA
1DY
2RA
2DY
3RA
3DY
4RA
4DY
1RY
1DA
2RY
2DA
3RY
3DA
4RY
4DA
GND
Wide Driver Supply Voltage . . .
±4.5 V to ±15 V
Driver Output Slew Rate Limited to
30 V/µs Max
Receiver Input Hysteresis . . . 1000 mV Typ
Push-Pull Receiver Outputs
On-Chip Receiver 1-µs Noise Filter
V
SS
description/ordering information
The SN65C1164 and SN75C1154 are low-power BiMOS devices containing four independent drivers and
receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment
(DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1154
and SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver,
respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs and the
receivers have filters that reject input noise pulses of shorter than 1 µs. Both these features eliminate the need
for external components.
The SN65C1154 and SN75C1154 have been designed using low-power techniques in a BiMOS technology.
In most applications, the receivers contained in these devices interface to single inputs of peripheral devices
such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices usually are insensitive
to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the
SN65C1154 and SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the
HCMOS, ALS, or 74F logic families.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
–40°C to 85°C
PDIP (N)
PDIP (N)
Tube of 20
Tube of 20
Tube of 25
Reel of 2500
Reel of 2000
SN65C1154N
SN65C1154N
SN75C1154N
SN75C1154N
SN75C1154DW
SN75C1154DWR
SN75C1154NSR
0°C to 70°C
SOIC (DW)
SOP (NS)
SN75C1154
SN75C1154
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
logic diagram (positive logic)
Typical of Each Receiver
2, 4, 6, 8
RA
19, 17, 15, 13
18, 16, 14, 12
RY
DA
Typical of Each Driver
3, 5, 7, 9
DY
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
schematics of inputs and outputs
EQUIVALENT DRIVER INPUT
EQUIVALENT DRIVER OUTPUT
V
DD
V
DD
Internal
1.4-V Reference
Input
DA
160 Ω
Output
DY
V
SS
74 Ω
GND
72 Ω
V
SS
EQUIVALENT RECEIVER INPUT
EQUIVALENT RECEIVER OUTPUT
3.4 kΩ
Input
RA
V
CC
1.5 kΩ
ESD
Protection
ESD
Protection
Output
RY
530 Ω
GND
GND
Resistor values shown are nominal.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage: V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
SS
CC
V
V
Input voltage range, V : Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to V
I
SS
DD
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V
Output voltage range, V :Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V – 6 V) to (V + 6 V)
O
SS
DD
CC
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
+ 0.3 V)
Package thermal impedance, θ (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage s are with respect to the network GND terminal.
2. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable
J
JA
A
ambient temperature is P = (T (max) – T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.
D
J
A
JA
J
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN NOM
MAX
15
UNIT
V
DD
V
SS
V
CC
Supply voltage
Supply voltage
Supply voltage
4.5
–4.5
4.5
12
–12
5
V
V
V
–15
6
Driver
V
SS
+ 2
V
DD
V
Input voltage
V
I
Receiver
Driver
±25
V
V
High-level input voltage
Low-level input voltage
High-level output current
High-level output current
2
V
V
IH
Driver
0.8
–1
3.2
85
70
IL
I
I
Receiver
Receiver
SN65C1154
SN75C1154
mA
mA
OH
OL
–40
T
A
Operating free-air temperature
°C
0
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
DRIVER SECTION
electrical characteristics over operating free-air temperature range, V
= 12 V, V = –12 V,
DD
SS
V
= 5 V ±10% (unless otherwise noted)
CC
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
= 5 V,
V
V
V
V
= –5 V
4
4.5
10.8
V
= 0.8 V,
R
R
= 3 kΩ,
DD
DD
DD
DD
SS
SS
SS
SS
IL
See Figure 1
L
L
V
V
High-level output voltage
V
OH
= 12 V,
= 5 V,
= –12 V
= –5 V
10
–4.4
–4
–10
1
Low-level output voltage
(see Note 4)
V
= 2 V,
= 3 kΩ,
IH
See Figure 1
V
OL
= 12 V,
= –12 V
–10.7
I
I
High-level input current
Low-level input current
High-level short-circuit
V = 5 V,
I
See Figure 2
See Figure 2
µA
µA
IH
V = 0,
I
–1
IL
I
I
I
V = 0.8 V,
I
V
= 0 or V
,
SS
See Figure 1
See Figure 1
–7.5
–12 –19.5
mA
mA
µA
OS(H)
O
O
‡
output current
Low-level short-circuit
V = 2 V,
I
V
= 0 or V
,
DD
7.5
12
19.5
OS(L)
DD
‡
output current
V
DD
V
DD
V
DD
V
DD
= 5 V,
V
SS
V
SS
V
SS
V
SS
= –5 V
= –12 V
= –5 V
= –12 V
115
115
250
250
No load,
All inputs at 2 V or 0.8 V
Supply current from V
DD
= 12 V,
= 5 V,
–115
–115
400
–250
–250
No load,
All inputs at 2 V or 0.8 V
I
Supply current from V
Output resistance
µA
SS
SS
= 12 V,
r
V
DD
= V
= V
= 0,
V = –2 V to 2 V,
O
See Note 5
300
Ω
o
SS
CC
†
‡
All typical values are at T = 25°C.
Not more than one output should be shorted at one time.
A
NOTES: 4. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
5. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics, V
= 12 V, V = –12 V, V
= 5 V ±10%, T = 25°C (see Figure 3)
CC A
DD
SS
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
2.5
2
MAX
3
UNIT
µs
§
§
t
t
t
t
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
R
R
R
R
R
R
R
= 3 to 7 kΩ,
= 3 to 7 kΩ,
= 3 to 7 kΩ,
= 3 to 7 kΩ,
= 3 to 7 kΩ,
= 3 to 7 kΩ,
= 3 to 7 kΩ,
CL = 15 pF
PLH
PHL
TLH
THL
TLH
THL
L
L
L
L
L
L
L
CL = 15 pF
CL = 15 pF
CL = 15 pF
3.5
3.2
3.2
2
µs
¶
¶
#
#
Transition time, low- to high-level output
Transition time, high- to low-level output
Transition time, low- to high-level output
Transition time, high- to low-level output
Output slew rate
0.53
0.53
µs
2
µs
C
C
= 2500 pF
= 2500 pF
1
µs
L
L
1
2
µs
SR
CL = 15 pF
4
10
30
V/µs
§
¶
#
t
and t
include the additional time due to on-chip slew rate control and are measured at the 50% points.
PLH
PHL
Measured between 10% and 90% points of output waveform
Measured between 3 V and –3 V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
RECEIVER SECTION
electrical characteristics over operating free-air temperature range, V = 12 V, V = –12 V,
= 5 V ± 10% (unless otherwise noted)
V
CC
DD
SS
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Positive-going input
threshold voltage
V
IT+
V
IT–
V
hys
See Figure 5
See Figure 5
1.7
0.65
600
2.1
1
2.55
V
Negative-going input
threshold voltage
1.25
V
Input hysteresis voltage
1000
mV
(V
IT+
– V
)
IT–
V = 0.75 V,
I
= –20 µA,
See Figure 5 and Note 6
3.5
2.8
3.8
4.3
I
OH
V
CC
V
CC
V
CC
= 4.5 V
= 5 V
4.4
4.9
V
V
High-level output voltage
V
OH
V = 0.75 V,
I
See Figure 5
I
= –1 mA,
OH
= 5.5 V
5.4
Low-level output voltage
High-level input current
V = 3 V,
I
= 3.2 mA,
See Figure 5
0.17
4.6
0.4
8.3
1
V
OL
I
OL
V = 25 V
I
3.6
0.43
–3.6
I
IH
mA
V = 3 V
I
0.55
–5
V = –25 V
I
–8.3
–1
I
I
I
I
Low-level input current
mA
mA
mA
µA
IL
V = –3 V
I
–0.43 –0.55
Short-circuit output
at high level
V = 0.75 V,
I
V
V
= 0,
See Figure 4
See Figure 4
–8
–15
OS(H)
OS(L)
CC
O
Short-circuit output
at low level
V = V
I CC
,
= V
CC
,
13
25
O
V
V
= 5 V,
V
V
= –5 V
400
400
600
600
No load,
All inputs at 0 or 5 V
DD
SS
Supply current from V
CC
= 12 V,
= –12 V
DD
SS
†
All typical values are at T = 25°C.
A
NOTE 6: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs will remain in the high state.
switching characteristics, V
= 12 V, V = –12 V, V
= 5 V ± 10%, T = 25°C
CC A
DD
SS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time,
low- to high-level output
t
t
C
C
= 50 pF,
= 50 pF,
R
R
= 5 kΩ,
= 5 kΩ,
See Figure 6
See Figure 6
3
4
µs
PLH
L
L
L
L
Propagation delay time,
high- to low-level output
3
4
µs
PHL
t
t
Transition time, low- to high-level output
Transition time, high- to low-level output
Duration of longest pulse
C
C
= 50 pF,
= 50 pF,
R
R
= 5 kΩ,
= 5 kΩ,
See Figure 6
See Figure 6
300
100
450
300
ns
ns
TLH
L
L
L
L
THL
t
C
= 50 pF,
R
= 5 kΩ
1
4
µs
w(N)
L
L
‡
rejected as noise
‡
Thereceiverignoresanypositive-ornegative-goingpulsethatislessthantheminimumvalueoft
w(N)
andacceptsanypositive-ornegative-going
pulse greater than the maximum of t
.
w(N)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
I
OSL
V
DD
V
V
V
V
or GND
or GND
DD
DD
CC
–I
OSH
I
V
IH
CC
V
V
SS
I
V
I
–I
IL
R
= 3 kΩ
L
V
O
I
V
SS
V
SS
Figure 1. Driver Test Circuit
(V , V , I , I
Figure 2. Driver Test Circuit (I , I )
)
IL IH
OH OL OSL OSH
3 V
0 V
V
DD
Input
t
1.5
1.5
V
Input
CC
Pulse
t
Generator
PHL
PLH
90%
(see Note A)
V
OH
90%
C
L
R
L
50%
10%
50%
10%
(see Note B)
Output
V
OL
t
t
V
SS
THL
TLH
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: t = 25 µs, PRR = 20 kHz, Z = 50 Ω, t = t < 50 ns.
w
O
r
f
B.
C includes probe and jig capacitance.
L
Figure 3. Driver Test Circuit and Voltage Waveforms
V
DD
–I
OS(H)
V
DD
V
CC
V
CC
V
I
I
V , V
IT
OS(L)
I
V
CC
–I
OH
V
OH
V
OL
I
OL
V
SS
V
SS
Figure 4. Receiver Test Circuit (I
, I
)
Figure 5. Receiver Test Circuit (V , V , V
)
OSH OSL
IT OL OH
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65C1154, SN75C1154
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D – DECEMBER 1988 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
4 V
0 V
V
DD
Input
50%
50%
Input
V
CC
Pulse
Generator
(see Note A)
t
PHL
t
PLH
90%
V
V
OH
C
90%
L
R
L
(see Note B)
50%
10%
50%
10%
Output
OL
t
t
V
THL
TLH
SS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: t = 25 µs, PRR = 20 kHz, Z = 50 Ω, t = t < 50 ns.
VOLTAGE WAVEFORMS
w
O
r
f
B.
C includes probe and jig capacitance.
L
Figure 6. Receiver Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
Samples Not Available
Samples Not Available
SN65C1154DW
SN65C1154DWR
SN65C1154N
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
PDIP
DW
DW
N
20
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
20
20
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
Contact TI Distributor
or Sales Office
SN65C1154NE4
SN75C1154DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
N
20
20
20
20
20
20
20
20
20
Pb-Free (RoHS)
Contact TI Distributor
or Sales Office
DW
DW
DW
DW
DW
DW
N
25
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
SN75C1154DWE4
SN75C1154DWG4
SN75C1154DWR
SN75C1154DWRE4
SN75C1154DWRG4
SN75C1154N
25
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
25
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
2000
2000
2000
20
Green (RoHS
& no Sb/Br)
Purchase Samples
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free (RoHS)
Contact TI Distributor
or Sales Office
SN75C1154NE4
N
20
Pb-Free (RoHS)
Contact TI Distributor
or Sales Office
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75C1154DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN75C1154DWR
2000
Pack Materials-Page 2
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