SN65EPT22_10 [TI]
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer; 3.3 V双LVTTL / LVCMOS到差分LVPECL缓冲器
| 型号： | SN65EPT22_10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer |
| 文件： | 总10页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65EPT22
www.ti.com ............................................................................................................................................................................................ SLLS926–DECEMBER 2008
3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer
1
FEATURES
APPLICATIONS
•
Data and Clock Transmission Over Backplane
•
Dual 3.3V LVTTL to LVPECL Buffer
•
Signaling Level Conversion
•
Operating Range
–
LVPECL VCC = 3.0 V to 3.6 V With
GND = 0 V
DESCRIPTION
The SN65EPT22 is a low power dual LVTTL to
LVPECL translator device. The device includes
circuitry to maintain known logic HIGH level when
inputs are in open condition. The SN65EPT22 is
housed in an industry standard SOIC-8 package and
is also available in TSSOP-8 package option.
•
•
•
Support for Clock Frequencies to 2.0 GHz (typ)
420 ps Typical Propagation Delay
Deterministic HIGH Output Value for Open
Input Conditions
•
•
•
Built-in Temperature Compensation
Drop in Compatible to MC100ELT23
PNP Single Ended Inputs for Minimal Loading
PINOUT ASSIGNMENT
Q
Q
1
2
8
7
V
CC
0
D
D
0
0
1
LVPECL
LVTTL
Q
Q
3
4
6
5
1
GND
1
Table 1. Pin Description
PIN
FUNCTION
D0, D1
Q0, Q0, Q1, Q1
VCC
LVTTL data inputs
LVPECL outputs
Positive supply
Ground
GND
ORDERING INFORMATION(1)
PART NUMBER
SN65EPT22D
PART MARKING
SN65EPT22
PACKAGE
SOIC
LEAD FINISH
NiPdAu
SN65EPT22DGK
SN65EPT22
SOIC-TSSOP
NiPdAu
(1) Leaded device options not initially available. Contact sales representative for further details.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65EPT22
SLLS926–DECEMBER 2008............................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)
PARAMETER
CONDITION
VALUE
6
UNIT
Absolute supply voltage, VCC
Absolute input voltage, VI
Supply voltage LVPEL
V
V
V
GND = 0 and VI ≤ VCC
0 to 6
3.3
Continuous
Surge
50
Output current
mA
100
Operating temperature range
Storage temperature range
–40 to 85
–65 to 150
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS
POWER RATING THERMAL RESISTANCE,
DERATING FACTOR
TA > 25°C
POWER RATING
TA = 85°C
(mW)
CIRCUIT BOARD
MODEL
JUNCTION TO AMBIENT
PACKAGE
TA < 25°C
(mW)
NO AIRFLOW
(mW/°C)
SOIC
Low-K
High-K
Low-K
High-K
719
840
469
527
139
119
213
189
7
8
5
5
288
336
188
211
SOIC-TSSOP
THERMAL CHARACTERISTICS
PARAMETER
Junction-to Board Thermal Resistance
PACKAGE
SOIC
VALUE
UNIT
θJB
79
120
98
°C/W
SOIC-TSSOP
SOIC
θJC
Junction-to Case Thermal Resistance
°C/W
SOIC-TSSOP
74
KEY ATTRIBUTES
CHARACTERISTICS
VALUE
Moisture sensitivity level
Lead free package
SOIC-8
TSSOP-8
Level 1
Level 3
Flammability rating (Oxygen Index: 28 to 34)
ESD-HBM
UL 94 V-0 at 0.125 in
4 kV
ESD-machine model
200 V
ESD-charge device model
2 kV
Meets or exceeds JEDEC Spec EIA/JESD78 latchup test
2
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN65EPT22
SN65EPT22
www.ti.com ............................................................................................................................................................................................ SLLS926–DECEMBER 2008
TTL INPUT DC CHARACTERISTICS(1) (VCC = 3.3 V, GND = 0, TA = –40°C to 85°C)
CHARACTERISTIC
Input HIGH current
CONDITION
MIN
TYP MAX
UNIT
µA
µA
mA
V
IIH
VIN = 2.7 V
VIN = VCC
20
100
–0.6
–1
IIHH
IIL
Input HIGH current max
Input LOW current
Input clamp voltage
Input high voltage
Input low voltage
VIN = 0.5 V
IIN = –18 mA
VIK
VIH
VIL
2.0
V
0.8
V
(1) Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
(2)
PECL OUTPUT DC CHARACTERISTICS(1) (VCC = 3.3 V; GND = 0.0V)
–40°C
25°C
TYP MAX
42 47
85°C
TYP MAX
45 50
CHARACTERISTIC
UNIT
MIN TYP MAX MIN
MIN
ICC
Power supply current
39
45
mA
mV
mV
(3)
VOH
VOL
Output HIGH voltage
Output LOW voltage(3)
2155 2224 2405 2155
1355 1441 1605 1355
2224 2405
1438 1605
2155
1355
2224 2405
1435 1605
(1) Device will meet the specifications after thermal balance has been established when mounted in a socket or printed circuit board with
maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating temperature
range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
(2) Output parameters vary 1:1 with VCC
(3) All loading with 50Ω to VCC –2.0V
AC CHARACTERISTICS (1)(VCC = 3.0 V to 3.6 V; GND = 0 V)(2)
–40°C
TYP MAX
25°C
MIN TYP
2.0
85°C
TYP
2.0
CHARACTERISTIC
UNIT
MIN
MAX
MIN
MAX
fMAX
Max switching frequency(3), see Figure 5
2.1
GHz
ps
tPLH / tPHL Propagation delay to differential output
230
550
50
230
550
50
230
550
50
Within device skew(4)
Device to device skew(5)
25
25
25
100
0.2
ps
tSKEW
100 200
100
200
0.8
300
200
0.8
300
ps
tJITTER
tr / tf
Random clock jitter (RMS)
0.2
0.8
0.2
ps
Output rise/fall times (20%–80%)
150
300
150
150
ps
(1) Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained transverse airflow greater than 500 lfpm. Electrical parameters are assured only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
(2) Measured using a 2.4 V source, 50% duty cycle clock source. All loading with 50 Ω to VCC – 2.0 V.
(3) Maximum switching frequency mearured at output amplitude of 300 mVpp
.
(4) Skew is measured between outputs under identical transitions and conditions on any one device.
(5) Device−to−Device Skew for identical transitions at identical VCC levels.
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN65EPT22
SN65EPT22
SLLS926–DECEMBER 2008............................................................................................................................................................................................ www.ti.com
Typical Termination for Output Driver
Z
O
= 50 W
P
P
Driver
Receiver
N
N
Z
O
= 50 W
50 W
50 W
V
TT
= V
V
- 2 V
CC
TT
Figure 1. Termination for Output Driver
1.5 V
1.5 V
IN
OUT
OUT
t
t
PHL
PLH
Figure 2. Output Propagation Delay
80%
20%
t
t
f
r
Figure 3. Output Rise and Fall Times
4
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN65EPT22
SN65EPT22
www.ti.com ............................................................................................................................................................................................ SLLS926–DECEMBER 2008
1.5 V
1.5 V
IN
Q
Q
O
O
t
t
PLH0
PHL0
Q1
Q1
t
t
PHL0
PLH1
Device Skew =
- t ), (t
Higher [(t
- t
)]
PLH1 PLH0 PHL1 PHL0
Figure 4. Device Skew
1000
900
800
700
600
500
V
= 3 V,
CC
GND = 0 V,
= 0.8 V - 2 V
V
swing
T
= -40°C
A
T
= 25°C
A
T
= 85°C
400
300
A
200
100
0
2500
0
1000
1500
f - Frequency - MHz
2000
500
Figure 5. Output Amplitude versus Frequency
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): SN65EPT22
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65EPT22DGKR
SN65EPT22DR
MSOP
SOIC
DGK
D
8
8
2500
2500
330.0
330.0
12.4
12.4
5.3
6.4
3.4
5.2
1.4
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65EPT22DGKR
SN65EPT22DR
MSOP
SOIC
DGK
D
8
8
2500
2500
346.0
346.0
346.0
346.0
29.0
29.0
Pack Materials-Page 2
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