SN65HVD01 [TI]
具有 1.65V I/O 电源和可选数据速率的 3.3V RS-485 收发器;
| 型号： | SN65HVD01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.65V I/O 电源和可选数据速率的 3.3V RS-485 收发器 |
| 文件： | 总31页 (文件大小：1479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65HVD01
ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
SN65HVD01 3.3V RS-485，具有灵活 I/O 电源和可选速度
1 特性
3 说明
1
•
超过 TIA-485 标准的要求
针对数据和使能信号的 1.65V 至 3.6V 电源
SN65HVD01 是一款低功耗，250ksps 或 20Mbps 数
据速率可选 RS-485 收发器，此收发器采用 1.65V 至
3.6V 电源用于数据和使能信号，而针对总线信号采用
一个 3.3V ± 10% 电源。 此器件被设计用于要求同
步（并行收发器）信号时序的应用。 片上瞬态抑制保
护此器件不受 IEC 61000 静电放电 (ESD) 和电快速瞬
变 (EFT) 瞬态的影响而损坏。
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•
•
•
•
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针对总线信号的 3V 至 3.6V 电源
SLR 引脚可选数据速率：250ksps 或 20Mbps
1/8 单位负载在一条总线上支持多达 256 个节点
小型 3mm x 3mm 小外形尺寸无引线 (SON) 封装
故障安全接收器（总线开路、总线短接、总线闲
置）
此器件组合有一个差分驱动器和一个差分接收器，这些
器件被内部连接以形成一个适用于半双工（两线制总
线）通信的总线端口。 此器件特有一个宽共模电压范
围，这使得此器件适合于长线缆运行上的多点应用。
SN65HVD01 采用极小型，3mm x 3mm，SON 封
装，运行温度范围 -40°C 至 125°C。
•
•
运行温度范围：-40°C 至 125°C
总线引脚保护大于：
–
–
–
–
±15kV 人体模型 (HBM) 保护
±16kV IEC61000-4-2 接触放电
±16kV IEC61000-4-2 空气放电
4kV IEC61000-4-4 快速瞬态突发
器件信息
2 应用范围
订货编号
封装
封装尺寸
SN65HVD01DRC
SON (10)
3mm x 3mm
•
•
•
电信基础设施
高速数据链路
低压 µC 通信
空白
空白
空白
空白
空白
空白
典型应用
1.8V
1.8V
3.3V
3.3V
V
L
SLR
V
V
SLR
V
L
CC
CC
D
R
A
B
A
B
DE
R
RE
D
120
120
RE
DE
GND
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLSEH0
SN65HVD01
ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
www.ti.com.cn
目录
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 15
Applications and Implementation ...................... 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Dissipation Ratings ................................................... 6
6.6 Electrical Characteristics........................................... 7
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 11
Detailed Description ............................................ 15
9
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 商标....................................................................... 22
12.2 静电放电警告......................................................... 22
12.3 术语表 ................................................................... 22
13 机械封装和可订购信息 .......................................... 22
7
8
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2014) to Revision F
Page
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•
Changed Figure 22 image and CH3 scale from: 100 V/div To 2 V/div ................................................................................ 20
Changed Figure 23 CH3 scale from: 100 V/div To 2 V/div .................................................................................................. 20
Changes from Revision D (November 2013) to Revision E
Page
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已将数据表更改为全新的 TI 标准格式..................................................................................................................................... 1
已添加器件信息表 .................................................................................................................................................................. 1
Added the Handling Ratings table.......................................................................................................................................... 5
Added the Detailed Description section................................................................................................................................ 15
Changed Figure 17............................................................................................................................................................... 17
Added the Applications and Implementation section............................................................................................................ 18
Deleted the Application Information section ......................................................................................................................... 18
Added the Power Supply Recommendations....................................................................................................................... 21
Added the Layout section .................................................................................................................................................... 21
2
版权 © 2013–2014, Texas Instruments Incorporated
SN65HVD01
www.ti.com.cn
ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
Changes from Revision C (November 2013) to Revision D
Page
•
已将特性从：小型 3mm x 3mm 超薄四方扁平无引线 (VQFN) 封装更改为：小型 3mm x 3mm 小外形尺寸无引线
(SON) 封装 ............................................................................................................................................................................. 1
已将特性从：总线引脚保护：更改为：总线引脚保护大于...................................................................................................... 1
已将特性从：≤ 15kV 更改为：±15kV HBM 保护.................................................................................................................... 1
已将特性从：≤ 15kV 更改为：±16kV 接触放电...................................................................................................................... 1
已将特性从：≤ 15kV 更改为：±16kV 空气放电...................................................................................................................... 1
已将说明文本从：3mm x 3mm，VQFN 封装更改为：3mm x 3mm，SON 封装 ................................................................... 1
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Changed the ABSOLUTE MAXIMUM RATINGS for IEC 61000-4-2 ESD (Air-Gap Discharge) From MAX = ±15 To:
MAX = ±16.............................................................................................................................................................................. 5
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•
Changed the ABSOLUTE MAXIMUM RATINGS for IEC 61000-4-2 ESD (Contact Discharge) From MAX = ±15 To:
MAX = ±16.............................................................................................................................................................................. 5
Changed the Thermal Information table package From VQFN (DRC) To; SON (DRC)........................................................ 5
Changes from Revision B (October 2013) to Revision C
Page
•
已更改 从产品预览改为生产数据 ............................................................................................................................................ 1
Changes from Revision A (October 2013) to Revision B
Page
•
Added 8 Typical Characteristics curves ................................................................................................................................. 9
Changes from Original (July 2013) to Revision A
Page
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•
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已将特性从：针对数据和使能信号的 1.8V 至 3.3V 电源更改为：针对数据和使能信号的 1.65V 至 3.6V 电源 ...................... 1
已将特性从：针对总线信号的 3.3V 电源更改为：针对总线信号的 3V 至 3.6V 电源.............................................................. 1
已将特性从：可选数据速率：250ksps 或 20Mbps 更改为：SLR 引脚可选数据速率：250ksps 或 20Mbps ......................... 1
已更改应用范围列表 ............................................................................................................................................................... 1
已更改说明.............................................................................................................................................................................. 1
在典型应用电路中，已将：100Ω 电阻器更改为：120Ω 电阻器 ............................................................................................. 1
Changed the ELECTRICAL CHARACTERISTICS table values ............................................................................................ 7
Changed the SWITCHING CHARACTERISTICS table values .............................................................................................. 8
Changed VCC and 3 V to VL in Figure 9 through Figure 16.................................................................................................. 11
Changed Figure 17............................................................................................................................................................... 17
Copyright © 2013–2014, Texas Instruments Incorporated
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SN65HVD01
ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
www.ti.com.cn
5 Pin Configuration and Functions
DRC 10 PIN
(TOP VIEW)
V
R
DE 3
1
2
10 V
9 B
8 A
L
CC
4
7 SLR
6 GND
RE
D
5
Pin Functions
NAME
NO.
1
I/O
DESCRIPTION
VL
R
Logic Supply 1.65 V to 3.6 V supply for logic I/O signals R, RE, D, DE, and SLR)
Digital Output Receive data output
2
DE
RE
D
3
Digital Input Driver enable input
4
Digital Input Receiver enable input
5
Digital Input Transmission data input
Reference
GND
6
Local device ground
Potential
SLR
A
7
8
Digital Input Slew rate select: Low = 20 Mbps, High = 250 kbps. Defaults to 20 Mbps if SLR is left floating
Bus I/O
Bus I/O
Digital bus I/O, A
Digital bus I/O, B
B
9
VCC
10
Bus Supply 3 V to 3.6 V supply for A and B bus lines
6 Specifications
6.1 Absolute Maximum Ratings(1)
VALUE
UNIT
MIN
–0.5
–0.5
–13
MAX
4
Control supply voltage, VL
V
V
Bus supply voltage, VCC
5.5
16.5
5.7
100
12
Voltage range at A or B Inputs
Input voltage range at any logic terminal
Voltage input range, transient pulse, A and B, through 100Ω
Receiver output current
V
–0.3
–100
–12
V
V
mA
°C
Junction temperature, TJ
170
Continuous total power dissipation
See the Thermal Information table
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
Copyright © 2013–2014, Texas Instruments Incorporated
SN65HVD01
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
6.2 Handling Ratings
MIN
MAX
150
±15
±16
±16
±4
UNIT
°C
TSTG
Storage temperature range
–65
IEC 60749-26 ESD (Human Body Model), bus terminals and GND
IEC 61000-4-2 ESD (Air-Gap Discharge), bus terminals and GND
IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND
kV
(1)
kV
kV
IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND
kV
VESD
JEDEC Standard 22, Test Method A114 (Human Body Model), all
terminals
±8
kV
JEDEC Standard 22, Test Method C101 (Charged Device Model), all
terminals
±1.5
kV
(1) As stated in the IEC 61000-4-2 standard, contact discharge is the preferred transient protection test method. Although IEC air-gap
testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results.
6.3 Recommended Operating Conditions
MIN
1.65
3
NOM
MAX UNIT
VL
Control supply voltage
3.6
3.6
12
V
V
V
V
VCC
VI
Bus supply voltage
3.3
(1)
Input voltage at any bus terminal (separately or common mode)
–7
VIH
High-level input voltage (Driver, driver enable, receiver enable inputs, and slew rate
select)
0.7×VL
VL
VIL
Low-level input voltage (Driver, driver enable, receiver enable inputs, and slew rate
select)
0
0.3×VL
V
VID
IO
Differential input voltage
–12
–80
–2
12
80
2
V
Driver
Output current
mA
mA
Ω
Receiver
RL
CL
Differential load resistance
Differential load capacitance
54
60
50
pF
SLR = '0'
Signaling rate
20 Mbps
1/tUI
SLR = '1'
250
125
kbps
°C
(2)
TA
Operating free-air temperature Thermal Information
–40
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
6.4 Thermal Information
PARAMETER(1)
Junction-to-Ambient Thermal Resistance
Junction-to-Case(top) Thermal Resistance
Junction-to-Board Thermal Resistance
SON (DRC)
41.4
48.7
18.8
0.6
UNIT
ΘJA
ΘJC(top)
ΘJB
°C/ W
ΨJT
Junction-to-Top characterization parameter
Junction-to-Board characterization parameter
Junction-to-Case(bottom) Thermal Resistance
Thermal Shut-down junction temperature
ΨJB
19
ΘJC(bottom)
TTSD
3.7
170
°C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
Copyright © 2013–2014, Texas Instruments Incorporated
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
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6.5 Dissipation Ratings
PARAMETER
TEST CONDITIONS
VALUE
UNIT
250 kbps
125
175
165
215
200
250
RL = 300 Ω,
CL = 50 pF (driver)
Unterminated
RS-422 load
RS-485 load
mW
20 Mbps
250 kbps
20 Mbps
250 kbps
20 Mbps
Power Dissipation driver and receiver
enabled,
RL = 100 Ω,
CL = 50 pF (driver)
PD
VCC = VL = 3.6 V, TJ = 150°C,
50% duty cycle square-wave signal at
signaling rate
mW
mW
RL = 54 Ω,
CL = 50 pF (driver)
6
Copyright © 2013–2014, Texas Instruments Incorporated
SN65HVD01
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
6.6 Electrical Characteristics
over recommended operating range (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
1.5
1.5
2
TYP
2
MAX
UNIT
RL = 60 Ω, 375 Ω on each output
See Figure 9
V
V
V
to –7 V to 12 V
Driver differential output voltage
magnitude
|VOD
|
RL = 54 Ω (RS-485)
2
RL = 100 Ω (RS-422) TJ ≥ 0°C,
VCC ≥ 3.2V
Change in magnitude of driver
differential output voltage
Δ|VOD
|
RL = 54 Ω, CL = 50 pF
–50
1
0
VCC/2
0
50
3
mV
V
See Figure 10
Steady-state common-mode output
voltage
VOC(SS)
Change in differential driver output
common-mode voltage
ΔVOC
Center of two 27-Ω load resistors
–50
50
mV
Peak-to-peak driver common-mode
output voltage
VOC(PP)
COD
500
15
mV
pF
Differential output capacitance
Positive-going receiver differential
input voltage threshold
(1)
VIT+
See
–60
–20
mV
Negative-going receiver differential
input voltage threshold
(1)
VIT–
–200
40
–130
70
See
mV
mV
Receiver differential input voltage
threshold hysteresis
VHYS
(VIT+ – VIT–
)
VL = 1.65 V, IOH = -2 mA
VL = 3 V, IOH = -2 mA
VL = 1.65 V, IOL = 2 mA
VL = 3 V, IOL = 2 mA
1.3
2.8
1.45
2.9
VOH
Receiver high-level output voltage
Receiver low-level output voltage
V
V
0.2
0.35
0.2
VOL
0.1
Driver input, driver enable, and
receiver enable input current
II
IOZ
IOS
–2
2
1
µA
µA
Receiver output high-impedance
current
VO = 0 V or VL, RE at VL
–1
Driver short-circuit output current
–150
150
125
mA
µA
µA
µA
µA
VI = 12 V
85
–60
750
VL = 1.8 V,
VCC = 3.3 V, DE at 0 V
II
Bus input current (disabled driver)
VI = –7 V
–100
1100
1000
Driver and Receiver
enabled
DE=VL, RE =
GND, No load
TJ ≤ 85°C
Driver enabled, receiver
disabled
DE=VCC, RE = VL, No load
DE=GND, RE = GND, No load
DE=GND, RE = VL, No load
350
650
0.1
650
800
5
µA
µA
µA
ICC
Supply current (quiescent)
Supply current (dynamic)
Driver disabled, receiver
enabled
Driver and receiver
disabled
See the Typical Characteristics section
(1) Under any specific conditions, VIT+ is specified to be at least VHYS higher than VIT–
.
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6.7 Switching Characteristics
over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER, SLR = '1', 250 kbps, bit time ≥ 4 µs
tr, tf
Driver differential output rise/fall time
Driver propagation delay
0.4
0.4
0.8
0.8
1.2
1.2
0.2
0.1
1
µs
µs
µs
µs
µs
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF
See Figure 11
Driver pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
0.025
0.6
See Figure 12 and
Figure 13
Receiver enabled
Receiver disabled
tPZH, tPZL
Driver enable time
3.5
8
DRIVER, SLR = '0', 20 Mbps, bit time ≥ 50 ns
tr, tf
Driver differential output rise/fall time
Driver propagation delay
5
6
10
15
15
25
4
ns
ns
ns
ns
ns
µs
RL = 54 Ω,
CL = 50 pF
tPHL, tPLH
tSK(P)
See Figure 11
Driver pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Driver disable time
20
14
3
35
30
7
See Figure 12 and
Figure 13
Receiver enabled
Receiver disabled
tPZH, tPZL
Driver enable time
RECEIVER, SLR = 'X'
tr, tf
Receiver output rise/fall time
5
15
90
15
20
80
8
ns
ns
ns
ns
ns
µs
See Figure 14
tPHL, tPLH
tSK(P)
Receiver propagation delay time
Receiver pulse skew, |tPHL – tPLH
Receiver disable time
CL = 15 pF
30
60
|
tPLZ, tPHZ
10
15
3
Driver enabled
Driver disabled
See Figure 15
See Figure 16
tpZL(1), tPZH(1)
tPZL(2), tPZH(2)
Receiver enable time
8
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SN65HVD01
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
6.8 Typical Characteristics
3.5
2.2
2.15
2.1
3
60:ꢀ
100:ꢀ
2.5
2
2.05
2
1.5
1
V
T
= V = 3.3V,
L
V
T
= V = 3.3V,
CC
= 25oC,
CC
L
= 25oC,
A
1.95
1.9
0.5
0
A
See Figure 1
DE = High
0
10
20
30
40
50
60
70
80
-7
-5
-3
-1
1
3
5
7
9
11
Driver Output Current (mA)
Driver Common Mode Load Voltage (V)
Figure 1. Differential Driver Output Voltage vs Driver Output
Current
Figure 2. Differential Driver Output Voltage vs Driver
Common Mode Load Voltage
20
18
16
14
12
10
8
845
835
825
815
805
795
785
775
V
T
= V = 3.3V,
L
CC
= 25oC,
A
SLR = High
6
V
T
= V = 3.3V,
L
CC
= 25oC,
4
2
0
A
SLR = Low
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
Figure 3. Transition Time vs Temperature
Figure 4. Transition Time vs Temperature
16
14
12
10
8
850
845
840
835
830
825
820
815
810
805
800
V
T
= V = 3.3V,
L
CC
= 25oC,
A
SLR = High
6
V
T
= V = 3.3V,
L
4
CC
= 25oC,
A
2
SLR = Low
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
Figure 5. Propagation Delay vs Temperature
Figure 6. Propagation Delay vs Temperature
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Typical Characteristics (continued)
70
60
50
40
30
20
10
0
60
50
40
30
V
T
= V = 3.3V,
L
V
T
= V = 3.3V,
L
CC
= 25oC,
CC
= 25oC,
20
10
0
A
A
SLR = High,
SLR = Low,
R
= 54:ꢀ
R
= 54:ꢀ
L
L
0
5
10
Signaling Rate (Mbps)
15
20
0
50
100
150
200
250
Signaling Rate (kbps)
Figure 7. Supply Current vs Signaling Rate
Figure 8. Supply Current vs Signaling Rate
10
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
7 Parameter Measurement Information
Input generator rate is 100 kbps, 50% duty cycle, rise and fall times less than 6 nsec.
375 W ±1%
VL
DE
A
B
D
VOD
0 V or VL
60 W ±1%
+
_
–7 V < V(test) < 12 V
375 W ±1%
Figure 9. Measurement of Driver Differential Output Voltage with Common-Mode Load
VL
DE
VA
A
B
RL/2
RL/2
A
B
VB
D
VOD
0 V or VL
VOC(PP)
DVOC(SS)
VOC
CL
VOC
Figure 10. Measurement of Driver Differential and Common-Mode Output with RS-485 Load
VL
VL
50%
50%
A
B
»
»
W
W
Figure 11. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
VL
A
B
S1
VO
D
VI
50%
50%
VL
0 V
DE
0.5 V
RL = 110 W
± 1%
CL = 50 pF ±20%
tPZH
VOH
90%
Input
Generator
CL Includes Fixture
50 W
VI
and Instrumentation
Capacitance
VO
50%
» 0 V
tPHZ
D at VL to test non-inverting output, D at 0 V to test inverting output.
Figure 12. Measurement of Driver Enable and Disable Times with Active High Output and Pull-Down
Load
Copyright © 2013–2014, Texas Instruments Incorporated
11
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www.ti.com.cn
Parameter Measurement Information (continued)
VL
RL = 110 W
±1%
» VL
A
B
VI
50%
50%
S1
D
VO
VL
0 V
tPZL
tPLZ
DE
CL = 50 pF ±20%
» 3 V
Input
Generator
VI
50 W
CL Includes Fixture
VO
50%
and Instrumentation
Capacitance
10%
VOL
D at 0V to test non-inverting output, D at VL to test inverting output.
Figure 13. Measurement of Driver Enable and Disable Times with Active Low Output and Pull-Up Load
VL
A
VI
50%
50%
VO
R
Input
Generator
50 W
0 V
VI
B
tPLH
tPHL
1.5 V
0 V
CL = 15 pF ±20%
VOH
RE
90% 90%
VO
50%
10%
50%
10%
VOL
CL Includes Fixture
tr
tf
and Instrumentation
Capacitance
Figure 14. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
12
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
Parameter Measurement Information (continued)
VL
DE
VL
A
B
VO
1 kW ± 1%
CL = 15 pF ±20%
R
D
0 V or VL
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
VL
VI
50%
50%
0 V
tPZH(1)
tPHZ
VOH
D at VL
90%
S1 to GND
VO
50%
» 0 V
tPZL(1)
tPLZ
VL
D at 0 V
S1 to VL
VO
50%
10%
VOL
Figure 15. Measurement of Receiver Enable/Disable Times with Driver Enabled
Copyright © 2013–2014, Texas Instruments Incorporated
13
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
www.ti.com.cn
Parameter Measurement Information (continued)
VL
A
B
VO
0 V or 1.5 V
1.5 V or 0 V
1 kW ± 1%
CL = 15 pF ±20%
R
S1
RE
CL Includes Fixture
and Instrumentation
Capacitance
Input
Generator
50 W
VI
VL
VI
50%
0 V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to GND
VO
50%
GND
VL
tPZL(2)
A at 0 V
B at 1.5 V
S1 to VL
VO
50%
VOL
Figure 16. Measurement of Receiver Enable Times with Driver Disabled
14
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SN65HVD01
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
8 Detailed Description
8.1 Overview
The SN65HVD01 is a low-power, half-duplex RS-485 transceiver whose maximum data rate can be set to either
250 kbps or 20 Mbps via a selection terminal, SLR.
The device possesses two power supply inputs, one for logic control functions, VL, and the other for the bus
supply, VCC. VL can range from 1.65 V minimum up to 3.6 V maximum and allows for the direct interface to low-
voltage FPGAs and micro controllers. VCC requires a supply between 3 V to 3.6 V to assure sufficient output
drive capability across a wide common-mode range.
8.2 Functional Block Diagram
V
L
V
SLR CC
D
DE
R
A
B
RE
GND
8.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic discharges (ESD) according to
IEC61000-4-2 of up to ±16 kV, and against electrical fast transients (EFT) according to IEC61000-4-4 of up to ±4
kV.
The SN65HVD01 provides internal biasing of the receiver input thresholds in combination with large input-
threshold hysteresis. At a positive input threshold of VIT+ = –60 mV and an input hysteresis of VHYS = 70 mV,
the receiver output remains logic high even in the presence of 130 mVPK differential noise without the need for
external failsafe biasing resistors.
Device operation is specified over a wide temperature range from –40°C to 125°C.
8.4 Device Functional Modes
When driver enable terminal, DE, is logic high, the differential outputs A and B follow the logic states at data
input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage
defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and
VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE
terminal has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance)
by default. The D terminal has an internal pull-up resistor to VL, thus, when left open while the driver is enabled,
output A turns high and B turns low.
Table 1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
B
L
H
H
H
L
Actively drive bus High
Actively drive bus Low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus High by default
OPEN
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When the receiver enable terminal, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and less than the negative and lower than the negative input threshold, VIT-, the
receiver output, R, turns low. If VID is between VIT+ and VIT- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VIT+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus High
Indeterminate bus state
Receive valid bus Low
Receiver disabled
VIT– < VID < VIT+
VID < VIT–
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
Connecting SLR to VL limits the maximum data rate to 250 kbps and increases the driver rise and fall times to
800 ns. Connecting SLR to GND increases the upper data rate limit to 20 Mbps and reduces the driver rise and
fall times to 10 ns.
Table 3. SLR-Terminal Configuration
SLR-INPUT
VL
DATA RATE
250 kbps
TYP tr / tf
800 ns
GND or OPEN
20 Mbps
10 ns
16
Copyright © 2013–2014, Texas Instruments Incorporated
SN65HVD01
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
8.4.1 Equivalent Input and Output Schematic Diagrams
D and RE Inputs
DE Input
R Output
Vcc
Vcc
Vcc
100k
1k
1k
1k
D,RE
DE
R
100k
9V
9V
9V
Driver Outputs
Vcc
Receiver Inputs
Vcc
16V
16V
R1
R2
R3
R2
R3
A
B
A
B
R
R1
16V
16V
Figure 17. Equivalent Input and Output Schematic Diagrams
Copyright © 2013–2014, Texas Instruments Incorporated
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9 Applications and Implementation
9.1 Application Information
The SN65HVD01 is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions. The
driver and receiver enable terminals allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
B
RE
A
B
RE
A
B
DE
D
DE
D
DE
D
D
D
D
a) Independent driver and
b) Combined enable signals for
c) Receiver always on
receiver enable signals
use as directional control pin
Figure 18. SN65HVD01 Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single, direction-control signal.
Thus, when the direction- control line is high, the transceiver is configured as a driver, while for a low the device
operates as a receiver.
Tying the receiver-enable to ground and controlling only the driver-enable input, also uses one control line only.
In this configuration, a node not only receives the data from the bus but also the data it sends and thus can verify
that the correct data have been transmitted.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
R
R
A
B
A
B
RE
RE
R
T
R
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Figure 19. Typical RS-485 Network with SN65HVD01 Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
18
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SN65HVD01
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Typical Application (continued)
9.2.1.1 Data Rate and Bus Length
The maximum bus length is limited by the transmission line losses and the signal jitter at a given data rate.
Because data reliability sharply decreases for a jitter of 10% or more of the baud period, Figure 20 shows the
cable length versus data rate characteristic of a conventional RS-485 cable for signal jitter of 10%.
10000
1000
100
10
0.1
1 10
Data Rate (Mbps)
100
Figure 20. Cable Length vs Data Rate
9.2.1.2 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12kΩ. Because the SN65HVD01 is a 1/8 UL transceiver, it is
possible to connect up to 256 devices to the bus.
9.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is therefore necessary. Figure 21 suggests a protection circuit against 10 kV ESD, 4 kV EFT, and 1 kV
surge transients.
1.8V
3.3V
100nF
100nF
10k
V
SLR
HVD01
GND
V
CC
L
R1
R
RxD
MCU/
UART
TVS
RE
DE
D
A
B
DIR
TxD
R2
10k
Figure 21. Transient Protection Against ESD, EFT, and Surge Transients
Copyright © 2013–2014, Texas Instruments Incorporated
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Typical Application (continued)
Table 4. Recommended Materials
Device
XCVR
R1,R2
TVS
Function
Order Number
3.3V, 250kbps RS-485 Transceiver
10Ω, Pulse-Proof Thick-Film Resistor
Bidirectional 400W Transient Suppressor
SN65HVD01D
CRCW0603010RJNEAHP
CDSOT23-SM712
9.2.3 Application Performance Curves
2 V/div
2 V/div
CH1 - D
CH1 - D
2 V/div
2 V/div
CH2 - VOD
CH2 - VOD
2 V/div
2 V/div
CH3 - R
CH3 - R
Time = 25 ns/div
Time = 2 ms/div
VCC = 3.3 V
VL = 1.8 V
SLR = GND
VCC = 3.3 V
VL = 1.8 V
SLR = VL
Figure 22. VOD and R Transient Response - 20 Mbps
Figure 23. VOD and R Transient Response - 250 kbps
20
Copyright © 2013–2014, Texas Instruments Incorporated
SN65HVD01
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ZHCSBS4F –JULY 2013–REVISED AUGUST 2014
10 Power Supply Recommendations
To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100 nF
ceramic capacitor located as close to the supply terminals as possible. Linear voltage regulators for the 1.8 V
logic and 3.3 V bus supplies are TPS76318 and TPS76333 respectively.
11 Layout
On-chip IEC-ESD protection is good for laboratory and portable equipment but never sufficient for EFT and surge
transients occurring in industrial environments. Therefore robust and reliable bus node design requires the use of
external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-
frequency layout techniques must be applied during PCB design.
In order for your PCB design to be successful start with the design of the protection circuit in mind.
11.1 Layout Guidelines
•
•
•
•
•
•
•
Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
Apply 100 nF to 220 nF bypass capacitors as close as possible to the VCC terminals of transceiver, UART,
controller ICs on the board.
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
Use 1k to 10k pull-up/down resistors for enable lines to limit noise currents in theses lines during transient
events.
Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
•
While pure TVS protection is sufficient for surge transients up to 1kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
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12 器件和文档支持
12.1 商标
All trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2013–2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65HVD01DRCR
SN65HVD01DRCT
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
HVD01
HVD01
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD01DRCR
SN65HVD01DRCT
VSON
VSON
DRC
DRC
10
10
2500
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD01DRCR
SN65HVD01DRCT
VSON
VSON
DRC
DRC
10
10
2500
250
335.0
182.0
335.0
182.0
25.0
20.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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