SN65HVD09DGG [TI]
9ch - RS-485 / RS-422 Transceiver 56-TSSOP -40 to 85;
| 型号： | SN65HVD09DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 9ch - RS-485 / RS-422 Transceiver 56-TSSOP -40 to 85 |
| 文件： | 总25页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD09
www.ti.com ............................................................................................................................................................................................ SLLS941–DECEMBER 2008
9-CHANNEL RS-422 / RS-485 TRANSCEIVER
Each of the nine half-duplex channels of the HVD09
is designed to operate with either RS-422 or RS-485
communication networks.
1
FEATURES
•
Designed to Operate at up to 20 Million Data
Transfers per Second on Each RS-422/RS-485
Channel
The SN65HVD09 is characterized for operation over
an ambient air temperature range of –40°C to 85°C.
•
SN65HVD09 Packaged in Thin Shrink
Small-Outline Package with 0.5-mm Pin Pitch
SN65HVD09 DGG
(TOP VIEW)
•
•
•
•
•
ESD Protection on Bus Pins Exceeds 12kV
Low Disabled Supply Current 8 mA Typ
Thermal Shutdown Protection
GND
BSR
GRE
CDE2
CDE1
CDE0
9B+
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
3
Positive- and Negative-Current Limiting
Power-Up/Down Glitch Protection
4
1A
1DE/RE
2A
9B-
5
6
8B+
8B-
7B+
7B-
6B+
6B-
VCC
7
2DE/RE
3A
DESCRIPTION
8
The SN65HVD09 is a 9-channel RS-422 / RS-485
transceiver suitable for industrial applications. It offers
improved switching performance, a small package,
and high ESD protection. The precise skew limits
ensures that the propagation delay times, not only
from channel-to-channel but from device-to-device,
are closely matched for the tight skew budgets
associated with high-speed parallel data buses.
9
3DE/RE
4A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
4DE/RE
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
GND
VCC
Patented thermal enhancements are used in the thin
shrink, small-outline package (TSSOP), allowing
operation over the industrial temperature range. The
TSSOP package offers very small board area
requirements while reducing the package height to
1 mm. This provides more board area and allows
component mounting to both sides of the printed
circuit boards for low-profile, space-restricted
applications such as small form-factor hard disk
drives.
5B+
5B-
5A
5DE/RE
6A
6DE/RE
7A
4B+
4B-
3B+
3B-
2B+
2B-
1B+
1B-
7DE/RE
8A
8DE/RE
9A
9DE/RE
The HVD09 can withstand electrostatic discharges
exceeding 12 kV using the human-body model, and
600 V using the machine model on the RS-485 I/O
terminals. This provides protection from the noise that
can be coupled into external cables. The other
terminals of the device can withstand discharges
exceeding 4 kV and 400 V respectively.
Terminals 13 through 17, and 40 through 44 are
connected together to the package lead frame
and signal ground.
9 Differential
RS-422/RS-485
I/O Channels
Configuration and
Control Logic
HVD09
9 Single-ended TTL
I/O Channels
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD09
SLLS941–DECEMBER 2008............................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PIN FUNCTIONS
PIN
LOGIC
LEVEL
I/O
TERMINATION
DESCRIPTION
NAME
NO.
4,6,8,10,
19,21,23,
25,27
1A to 9A
TTL
I/O
Pullup
1A to 9A carry data to and from the communication controller.
29,31,33,
35,37,.46
,
1B– to 9B–
RS-485
I/O
Pulldown
1B– to 9B– are the inverted data signals of the balanced pair to/from the bus.
1B+ to 9B+ are the noninverted data signals of the balanced pair to/from the bus.
48,50,52
30,32,34,
1B+ to 9B+ 36,38,47,
49,51,53
RS-485
TTL
I/O
Pullup
Pullup
BSR is the bit significant response. BSR disables receivers 1 through 8 and enables
wired-OR drivers when BSR and DE/RE and CDE1 or CDE2 are high. Channel 9 is
placed in a high-impedance state with BSR high.
BSR
2
Input
CDE0 is the common driver enable 0. Its input signal enables all drivers when CDE0 and
1DE/RE – 9DE/RE are high.
CDE0
CDE1
54
55
TTL
TTL
Input
Input
Pulldown
Pulldown
CDE1 is the common driver enable 1. Its input signal enables drivers 1 to 4 when CDE1 is
high and BSR is low.
CDE2 is the common driver enable 2. When CDE2 is high and BSR is low, drivers 5 to 8
are enabled.
CDE2
CRE
56
3
TTL
TTL
Input
Input
Pulldown
Pullup
CRE is the common receiver enable. When high, CRE disables receiver channels 5 to 9.
5,7,9,11,
20,22,24,
26,28
1DE/RE–9DE/RE are direction controls that transmit data to the bus when it and CDE0
are high. Data is received from the bus when 1DE/RE–9DE/RE and CRE and BSR are
low and CDE1 and CDE2 are low.
1DE/RE to
9DE/RE
TTL
Input
Pullup
1,13,14,
15,16,17,
40,41,42,
43,44
GND is the circuit ground. All GND terminals except terminal 1 are physically tied to the
die pad for improved thermal conductivity.(1)
GND
VCC
NA
NA
Power
Power
NA
NA
12,18,39,
45
Supply voltage
(1) Terminal 1 must be connected to signal ground for proper operation.
2
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www.ti.com ............................................................................................................................................................................................ SLLS941–DECEMBER 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
54
CDE0
55
CDE1
2
BSR
30
1B+
1B−
4
1A
29
5
1DE/RE
6
7
8
32
31
34
2B+
2B−
3B+
3B−
4B+
4B−
2A
2DE/RE
3A
Channel 2
Channel 3
Channel 4
9
33
36
35
3DE/RE
4A
10
11
4DE/RE
56
CDE2
3
CRE
5A
38
37
5B+
5B−
19
20
5DE/RE
21
22
23
47
46
49
48
6B+
6B−
7B+
6A
6DE/RE
7A
Channel 6
Channel 7
Channel 8
24
25
26
7B−
8B+
7DE/RE
8A
51
50
8DE/RE
8B−
2
3
54
53
52
BSR
BSR
CRE
CDE0
9B+
9B−
27
28
9A
9DE/RE
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SN65HVD09
SLLS941–DECEMBER 2008............................................................................................................................................................................................ www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
UNIT
V
VCC Supply voltage range(2)
Bus voltage range
–0.3 to 6
–10 to 15
V
Data I/O and control (A side) voltage range
–0.3 to VCC +0.5
V
IO
Receiver output current
±40
mA
kV
V
B side and GND, Class 3, A(3)
B side and GND, Class 3, B(3)
All terminals, Class 3, A
12
400
Electrostatic discharge
4
400
kV
V
All terminals, Class 3, B
(4)
Continuous total power dissipation
Internally Limited
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.r
(2) All voltage values are with respect to the GND terminals.
(3) This absolute maximum rating is tested in accordance with MIL-PRF-38535, Method 3015.7.
(4) The maximum operating junction temperature is internally limited. Use the Dissipation Rating Table to operate below this temperature.
DISSIPATION RATINGS
OPERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
TA ≤ 25°C
DGG
2500 mW
20 mW/°C
1600 mW
1300 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
PACKAGE THERMAL CHARACTERISTICS
MIN
NOM
MAX
UNIT
Junction-to-ambient thermal
resistance
DGG, board-mounted, no air flow
50
θJA
°C/W
θJC
Junction-to-case thermal resistance DGG
Thermal shutdown temperature
27
°C/W
°C
TSD
165
RECOMMENDED OPERATING CONDITIONS
MIN
4.75
2
NOM
MAX
UNIT
V
VCC
Supply voltage
5
5.25
VIH
High-level input voltage
V
Except nB+, nB–(1)
VIL
Low-level input voltage
0.8
12
60
8
V
VO, VI, or VIC
Voltage at any bus terminal (separately or common-mode)
nB+ or nB–
Driver
–7
–60
–8
V
mA
mA
°C
IO
Output current
Receiver
TA
Ambient temperature
SN65HVD09
–40
85
(1) n = 1 - 9
4
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SN65HVD09
www.ti.com ............................................................................................................................................................................................ SLLS941–DECEMBER 2008
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
SN65HVD09
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP(1)
1.6
1.4
1.5
4.5
3
MAX
RS-422 load,
RL = 100 Ω
RL = 54 Ω
1
See Figure 1
Driver differential output voltage
magnitude
|VOD
|
RS-485 load,
V
Pull-Up Pull-Down Load
See Figure 2
See Figure 4
See Figure 2
See Figure 4
See Figure 2
1
4
A side, IOH = –8 mA, VID = 200 mV,
V
V
V
V
VOH
High-level output voltage
Low-level output voltage
B side,
A side, IOH = 8 mA, VID = –200 mV,
B side,
0.6
1
0.8
0.2
VOL
VIT+
Receiver positive-going differential
input threshold voltages
IOH = –8 mA,
IOL = 8 mA,
See Figure 4
SeeFigure 4
V
V
VIT–
Vhys
Receiver negativegoing differential
input threshold voltage
–0.2
24
Receiver input hysteresis
VCC = 5 V,
TA = 25°C
45
mV
(VIT+ – VIT–
)
VIH = 12 V
VIH = 12 V
VIH = –7 V
VIH = –7 V
VCC = 5 V,
VCC = 0,
1
1
mA
mA
mA
mA
µA
II
Bus input current
Other input at 0 V
VCC = 5 V,
VCC = 0,
–0.8
–0.8
–100
–0.4
–0.3
nA, BSR, DE/RE, and CRE,
CDE0, CDE1, and CDE2,
nA, BSR, DE/RE, and CRE,
CDE1, CDE1, and CDE2,
nB+ or nB–
VIH = 2 V
VIH = 2V
IIH
High-level input current
100
µA
VIL = 0.8 V
VIL = 0.8 V
–100
µA
IIL
Low-level input current
100
µA
IOS
IOZ
Short circuit output current
±260
mA
nA
See IIH and IIL
See III
High-impedance-state output
current
nB+ or nB–
Disabled
10
60
45
25
ICC
Supply current
All drivers enabled, no load
All receivers enabled, no load
nB+ or nB– to GND
Receiver
mA
CO
Output capacitance
18
40
pF
pF
(2)
Cpd
Power dissipation capacitance
Driver
100
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) Cpd determines the no-load dynamic supply current consumption, IS = CPD × VCC × f + ICC
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SN65HVD09
SLLS941–DECEMBER 2008............................................................................................................................................................................................ www.ti.com
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65HVD09
MIN TYP(1) MAX
PARAMETER
TEST CONDITIONS
UNIT
tpd
Propagation delay time, tPHL or tPLH (see Figure 2 and Figure 3)
2.5
13.5
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsk(p)
tf
Pulse skew, |tPHL – tPLH
|
Fall time
S1 to B, See Figure 3
See Figure 3
4
8
tr
Rise time
ten
Enable time, control inputs to active output
50
tdis
tPHZ
tPLZ
tPZH
tPZL
Disable time, control inputs to high-impedance output
Propagation delay time, high-level to high-impedance output
Propagation delay time, low-level to high-impedance output
Propagation delay time, high-impedance to high-level output
Propagation delay time, high-impedance to low-level output
100
17 100
25 100
See Figure 6 and
Figure 7
17
17
50
50
(1) All typical values are at VCC = 5 V, TA = 25°C.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
SN65HVD09
MIN TYP(1) MAX
PARAMETER
TEST CONDITIONS
UNIT
tpd
Propagation delay time, tPHL or tPLH (see Figure 2 and Figure 3)
8.5
14.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tsk(lim)
tsk(p)
tt
Skew limit, maximum tpd – minimum tpd
Pulse skew, |tPHL – tPLH
|
0.6
2
4
Transition time (tr or tf)
See Figure 5
ten
Enable time, control inputs to active output
50
60
60
50
50
50
tdis
Disable time, control inputs to high-impedance output
Propagation delay time, high-level to high-impedance output
Propagation delay time, low-level to high-impedance output
Propagation delay time, high-impedance to high-level output
Propagation delay time, high-impedance to low-level output
tPHZ
tPLZ
tPZH
tPZL
See Figure 8 and
Figure 9
(1) All typical values are at VCC = 5 V, TA = 25°C.
(2) This parameter is applicable at one VCC and operating temperature within the recommended operating conditions and to any two
devices.
6
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www.ti.com ............................................................................................................................................................................................ SLLS941–DECEMBER 2008
PARAMETER MEASUREMENT INFORMATION
R /2
L
B+
A
Input
VOC
B-
CL = 50 pF ±20%
R /2
L
CL Includes Fixture and
Instrumentation Capacitance
Figure 1. Driver Test Circuit, RS-422 and RS-485 Loading
5 V
165 Ω
PU
S1
PD
B+
I
I
O
15 pF
I
I
165 Ω
375 Ω
375 Ω
A
V
OD
Input
(see Note A)
75 Ω
V
O
V
I
O
B−
S2
V
O
15 pF
†
†
CDEO and DE/RE are at 2 V, BSR is at 0.8V, and all others are open.
All nine drivers are enabled, similarly loaded, and switching.
‡
Figure 2. Driver Test Circuit, Pull-Up and Pull-Down Loading‡
3 V
Input
1.5 V
1.5 V
0 V
t
t
PHL
PLH
V
V
OD(H)
90%
90%
Output, V
0V
10%
0V
10%
OD
S1 to PU or PD
OD(L)
t
r
t
f
Figure 3. Driver Delay and Transition Time Test Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Input B+
Generator
50 Ω
(see Note A)
I
O
V
ID
Output
Input B−
Generator
V
O
C
= 15 pF
L
50 Ω
(see Note A)
†
† CDEO, CDE1, CDE2, BSR, CRE, and DE/RE at 0.8 V
‡
All nine receivers are enabled and switching.
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit
A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz,
duty cycle = 50%, ZO = 50 Ω.
B. All resistances are in Ω and ±5%, unless otherwise indicated.
C. All capacitances are in pF and ±10%, unless otherwise indicated.
D. All indicated voltages are ±10 mV.
3 V
0 V
Input B−
Input B+
1.5 V
1.5 V
t
t
PHL
PLH
V
V
OH
90%
90%
Output
1.4 V
10%
1.4 V
10%
OL
t
r
t
f
Figure 5. Receiver Delay and Transition Time Waveforms
4.5 V
165 Ω
PU
S1
PD
B+
50 pF
75 Ω
165 Ω
375 Ω
375 Ω
A
V
OD
0 V or 3 V
B−
S2
DE/RE
†
50 pF
See Table 1
Input
†
Includes probe and jig capacitance in two places.
Figure 6. Driver Enable and Disable Time Test Circuit
8
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Table 1. Enabling for Driver Enable and Disable Time
DRIVER
BSR
H
CDE0
CDE1
CDE2
CRE
X
1–8
9
H
H
L
L
L
H
H
H
3 V
0 V
Input, DE/RE
1.5 V
1.5 V
t
t
PHZ
PZH
V
OD(H)
A at 3V
0 V
0 V
Output, V
Output, V
OD
OD
S1 to PD
∼ −1 V
∼ 1 V
t
t
PLZ
PZL
A at 0V
0 V
0 V
S1 to PU
V
OD(L)
Figure 7. Driver Enable Time Waveforms
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz,
duty cycle = 50%, ZO = 50 Ω.
B. All resistances are in Ω and ±5%, unless otherwise indicated.
C. All capacitances are in pF and ±10%, unless otherwise indicated.
D. All indicated voltages are ±10 mV.
V
T
620 Ω
Output
B+
A
0 V or 3 V
Input
DE/RE
†
3 V or 0 V
‡
40 pF
B−
†
‡
CDEO is high, CDE1, CDE2, BSR, and CRE are low,
all others are open.
Includes probe and jig capacitance.
Figure 8. Receiver Enable and Disable Time Test Circuit
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3 V
Input
1.4 V
1.4 V
0 V
t
t
PZL
PLZ
B+ at 0 V
B− at 3 V
1.4 V
1.4 V
Output
V
T
= V
CC
V
OD
Indeterminate
t
t
PZH
PHZ
B+ at 3 V
B− at 0 V
1.4 V
1.4 V
Output
V
T
= 0
Indeterminate
V
OD
Figure 9. Receiver Enable and Disable Time Waveforms
NOTES: A.
All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz,
duty cycle = 50%, ZO = 50 Ω.
B.
C.
D.
All resistances are in Ω and ±5%, unless otherwise indicated.
All capacitances are in pF and ±10%, unless otherwise indicated.
All indicated voltages are ±10 mV.
10
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TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
LOGIC INPUT CURRENT
vs
vs
FREQUENCY
INPUT VOLTAGE
−30
−25
250
200
150
100
A, DE/RE,CRE,BSR
−20
−15
−10
9 Drivers
50
0
−5
0
9 Receivers
0
1
2
3
4
5
0.001
0.01
0.1
1
10
100
V − Input Voltage − V
I
f − Frequency − MHz
Figure 10.
Figure 11.
BUS
INPUT CURRENT
vs
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
INPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
15
10
2.5
2
1.5
1
5
0
0.5
0
−5
−10
0
10 20 30 40 50 60 70 80 90 100
−20 −15 −10 −5
0
5
10
15
20
I
− Low-Level Output Current − mA
V − Input Voltage − V
I
OL
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TEMPERATURE
4
3.5
3
1.9
1.8
1.7
R
= 100 W
L
PU/PD Load
1.6
1.5
1.4
1.3
1.2
2.5
2
R
= 54 W
L
1.5
1
0.5
0
1.1
1
-40
-20
0
20
40
60
80
0
−20
−40
−60
−80
−100
Temperature - °C
I
− High-Level Output Current − mA
OH
Figure 14.
Figure 15.
RECEIVER
PROPAGATION DELAY TIME
vs
DRIVER
PROPAGATION DELAY TIME
vs
TEMPERATURE
TEMPERATURE
13
12
11
13
12.5
12
t
PHL
t
PHL
11.5
10
9
t
11
10.5
10
PLH
8
t
PLH
7
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
Temperature - °C
Temperature - °C
Figure 16.
Figure 17.
12
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TYPICAL CHARACTERISTICS (continued)
DRIVER
OUTPUT CURRENT
vs
SUPPLY VOLTAGE
100
T
A
= 25°C
80
60
40
20
0
I
OH
−20
−40
−60
−80
I
OL
0
1
2
3
4
5
6
V
CC
− Supply Voltage − V
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
SCHEMATICS OF INPUTS AND OUTPUTS
DE/RE, CRE, BSR, AND
A Inputs
CDE0, CDE1, AND CDE2 Inputs
V
CC
V
CC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
8 V
8 V
B+ Input
B− Input
V
CC
V
CC
100 kΩ
18 kΩ
2 kΩ
2 kΩ
16 V
16 V
18 kΩ
Input
Input
100 kΩ
4 kΩ
4 kΩ
16 V
16 V
B+ AND B− Outputs
V
CC
A Output
V
CC
2 kΩ
16 V
Output
40 Ω
Output
18 kΩ
8 V
4 kΩ
16 V
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SN65HVD09
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APPLICATION INFORMATION
FUNCTION TABLES
RECEIVER
DRIVER
B+
B−
B+
B−
A
A
INPUTS
OUTPUT
A
OUTPUTS
INPUT
1
1
B+
B−
A
B+
B−
L
H
L
L
L
L
H
L
H
H
H
H
TRANSCEIVER
DRIVER WITH ENABLE
B+
B−
A
B+
A
B−
DE/RE
DE/RE
INPUTS
OUTPUTS
INPUTS
OUTPUTS
1
1
B−
DE/RE
A
B+
B−
B−
DE/RE
A
B+
A
B+
L
L
Z
Z
L
Z
Z
H
L
L
−
−
L
L
H
−
−
H
L
−
−
L
H
−
−
−
−
L
−
−
H
L
L
H
L
L
H
H
H
H
H
H
H
H
WIRED-OR DRIVER
TWO-ENABLE INPUT DRIVER
B+
B−
A
A
B+
B−
DE/RE
OUTPUTS
INPUTS
DE/RE
OUTPUTS
INPUT
A
B−
B+
B−
A
B+
L
Z
Z
L
L
L
Z
H
L
Z
L
H
L
H
H
L
H
L
H
H
H
H
NOTE: H = high level, L = low level, X = irrelevant, Z = high impedance (off)
(1) An H in this column represents a voltage of 200 mV or higher than the other bus input. An L represents a voltage of
200 mV or lower than the other bus input. Any voltage less than 200 mV results in an indeterminate receiver output.
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V
CC
V
CC
1
1
620 Ω
620 Ω
nA
Connector
nB+
nB−
Connector
nB+
nB−
+
−
−
+
nA
I/O
EN
I/O
EN
nDE/RE
nDE/RE
(a) ACTIVE-HIGH BIDIRECTIONAL I/O
WITH SEPARATE ENABLE
(b) ACTIVE-LOW BIDIRECTIONAL I/O
WITH SEPARATE ENABLE
V
CC
V
CC
V
CC
1
620 Ω
Connector
1
Connector
620 Ω
1
620 Ω
nB+
nB−
I
nB+
nB−
+
+
−
nA
nA
2
O
I
−
EN
O
nDE/RE
nDE/RE
(d) SEPARATE ACTIVE-HIGH INPUT, OUTPUT,
AND ENABLE
(c) WIRED-OR DRIVER AND ACTIVE-HIGH INPUT
V
CC
V
CC
1
Connector
1
620 Ω
620 Ω
Connector
nB+
nB−
nB+
nB−
−
+
I
2
nA
−
+
nA
I
O
O
EN
nDE/RE
nDE/RE
620 Ω
(f) WIRED-OR DRIVER AND ACTIVE-LOW INPUT
(e) SEPARATE ACTIVE-LOW INPUT AND
OUTPUT AND ACTIVE-HIGH ENABLE
1: When 0 is open drain
2: Must be open-drain or 3-state output
(1) When 0 is open drain
(2) Must be open-drain or 3-state output
NOTE: The BSR, CRE, A, and DE/RE inputs have internal pullup resistors. CDE0, CDE1, and CDE2 have internal pulldown
resistors.
Figure 19. Typical Transceiver Connections
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CHANNEL LOGIC CONFIGURATIONS WITH CONTROL INPUT LOGIC
The following logic diagrams show the positive-logic representation for all combinations of control inputs. The
control inputs are from MSB to LSB; the BSR, CDE0, CDE1, CDE2, and CRE bit values are shown below the
diagrams. Channel 1 is at the top of the logic diagrams; channel 9 is at the bottom of the logic diagrams.
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 19. 00000
Figure 20. 00001
Figure 21. 00010
Figure 22. 00011
Figure 23. 00100
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Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Figure 24. 00101
Figure 25. 00110
Figure 26. 00111
Figure 28. 01001
Figure 27. 01000
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Figure 32. 01101
Figure 33. 01110
Figure 29. 01010
Figure 30. 01011
Figure 31. 01100
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V
V
CC
CC
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
V
V
CC
CC
CC
CC
CC
CC
V
CC
Hi-Z
Hi-Z
V
V
Hi-Z
Hi-Z
V
CC
V
V
Hi-Z
V
CC
Figure 35.
10000
and 10001
Figure 34. 01111
V
CC
Hi-Z
V
CC
Hi-Z
Hi-Z
V
CC
Hi-Z
Hi-Z
Hi-Z
V
Figure 36. 10010
and 10011
Figure 37. 10100
and 10101
CC
V
CC
Hi-Z
Figure 38. 10110
and 10111
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Hi-Z
Figure 39. 11000
and 11001
Hi-Z
Hi-Z
Figure 40. 11010
and 11011
Figure 41. 11100
and 11101
Hi-Z
Figure 42. 11110
and 11111
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PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65HVD09DGGR
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
SN65HVD09DGGR
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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