SN65HVD10QDR [TI]
3.3-V RS-485 TRANSCEIVERS; 3.3 V RS - 485收发器
| 型号： | SN65HVD10QDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V RS-485 TRANSCEIVERS |
| 文件： | 总28页 (文件大小：908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
3.3-V RS-485 TRANSCEIVERS
Check for Samples: SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11, SN65HVD11Q, SN75HVD11, SN65HVD12, SN75HVD12
1
FEATURES
DESCRIPTION
The SN65HVD10, SN75HVD10, SN65HVD11,
•
•
•
Operates With a 3.3-V Supply
SN75HVD11,
combine
SN65HVD12,
3-state differential line driver and
and
SN75HVD12
Bus-Pin ESD Protection Exceeds 16 kV HBM
a
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
differential input line receiver that operate with a
single 3.3-V power supply. They are designed for
balanced transmission lines and meet or exceed
ANSI standard TIA/EIA-485-A and ISO 8482:1993.
These differential bus transceivers are monolithic
integrated circuits designed for bidirectional data
communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and
active-low enables respectively, that can be externally
connected together to function as direction control.
Very low device standby supply current can be
achieved by disabling the driver and the receiver.
•
Optional Driver Output Transition Times for
(1)
Signaling Rates of 1 Mbps, 10 Mbps, and
32 Mbps
•
•
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
Bus-Pin Short Circuit Protection From –7 V to
12 V
•
•
Low-Current Standby Mode . . . 1 µA Typical
Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
disabled or VCC = 0. These parts feature wide positive
and negative common-mode voltage ranges, making
them suitable for party-line applications.
•
•
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
•
SN75176 Footprint
APPLICATIONS
D OR P PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
Digital Motor Control
Utility Meters
R
RE
DE
D
VCC
B
1
2
3
4
8
7
6
5
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
A
GND
Point-of-Sale (POS) Terminals and Networks
1
2
R
RE
3
4
DE
D
6
A
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
7
B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE
SIGNALING
RATE
UNIT LOADS
TA
SOIC MARKING
SOIC(1)
PDIP
32 Mbps
10 Mbps
1 Mbps
1/2
1/8
1/8
1/2
1/8
1/8
1/2
1/8
SN65HVD10D
SN65HVD11D
SN65HVD12D
SN75HVD10D
SN75HVD11D
SN75HVD12D
SN65HVD10QD
SN65HVD11QD
SN65HVD10P
SN65HVD11P
SN65HVD12P
SN75HVD10P
SN75HVD11P
SN75HVD12P
SN65HVD10QP
SN65HVD11QP
VP10
VP11
–40°C to 85°C
VP12
32 Mbps
10 Mbps
1 Mbps
VN10
VN11
VN12
VP10Q
VP11Q
–0°C to 70°C
32 Mbps
10 Mbps
–40°C to 125°C
(1) The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1) (2)
UNIT
VCC Supply voltage range
–0.3 V to 6 V
–9 V to 14 V
–0.5 V to VCC + 0.5 V
–50 V to 50 V
–11 mA to 11 mA
±16 kV
Voltage range at A or B
Input voltage range at D, DE, R or RE
Voltage input range, transient pulse, A and B, through 100 Ω, see Figure 11
IO
Receiver output current
A, B, and GND
All pins
Human body model(3)
Electrostatic
discharge
±4 kV
Charged-device model(4)
All pins charge
±1 kV
Continuous total power dissipation
Electrical Fast Transient/Burst(5)
Junction temperature
See Dissipation Rating Table
±4 kV
A, B, and GND
TJ
170°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749-26.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
(5) Tested in accordance with IEC 61000-4-4.
PACKAGE DISSIPATION RATINGS
PACKAGE
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
POWER RATING
D(2)
D(3)
P
597 mW
4.97 mW/°C
8.26 mW/°C
10.75 mW/°C
373 mW
620 mW
806 mW
298 mW
496 mW
645 mW
100 mW
165 mW
215 mW
990 mW
1290 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
2
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Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD11Q SN75HVD11
SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted
MIN
3
–7(1)
NOM
MAX
3.6
12
UNIT
VCC
Supply voltage
VI or VIC Voltage at any bus terminal (separately or common mode)
VIH
VIL
VID
High-level input voltage
Low-level input voltage
Differential input voltage
D, DE, RE
D, DE, RE
Figure 7
Driver
2
VCC
0.8
12
V
0
–12
–60
–8
IOH
High-level output current
Low-level output current
mA
mA
Receiver
Driver
60
8
IOL
Receiver
RL
CL
Differential load resistance
Differential load capacitance
54
60
50
Ω
pF
HVD10
HVD11
HVD12
32
10
Signaling rate
Mbps
°C
1
(2)
TJ
Junction temperature
145
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP(1) MAX UNIT
VIK
II = –18 mA
IO = 0
–1.5
2
V
VCC
|VOD
|
Differential output voltage(2)
RL = 54 Ω, See Figure 1
1.5
1.5
V
Vtest = –7 V to 12 V, See Figure 2
Change in magnitude of differential output
voltage
Δ|VOD
|
See Figure 1 and Figure 2
–0.2
0.2
V
VOC(PP)
VOC(SS)
Peak-to-peak common-mode output voltage
Steady-state common-mode output voltage
400
mV
V
1.4
2.5
See Figure 3
Change in steady-state common-mode output
voltage
–0.0
5
ΔVOC(SS)
0.05
V
IOZ
High-impedance output current
See receiver input currents
D
–100
0
0
100
250
II
Input current
DE
μA
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
–250
mA
pF
C(OD)
Differential output capacitance
VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
16
9
RE at VCC
D & DE at VCC,
No load
,
Receiver disabled and
driver enabled
15.5
5
mA
RE at VCC
,
D at VCC
,
Receiver disabled and
ICC
Supply current
1
9
μA
DE at 0 V,
No load
driver disabled (standby)
RE at 0 V,
D & DE at VCC
No load
Receiver enabled and
driver enabled
,
15.5
mA
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) For TA > 85°C, VCC is ±5%.
Copyright © 2002–2013, Texas Instruments Incorporated
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
HVD10
5
18
135
5
8.5
25
16
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL – tPLH|)
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
HVD10
HVD11
HVD12
40
300
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
8.5
25
18
135
3
40
200
4.5
20
300
10
RL = 54 Ω, CL = 50 pF,
See Figure 4
10
100
3
30
170
4.5
20
300
10
tf
10
100
30
170
300
1.5
2.5
7
tsk(p)
tsk(pp)
tPZH
tPHZ
tPZL
tPLZ
6
(2)
Part-to-part skew
11
100
31
Propagation delay time, high-impedance-to-high-
level output
55
300
25
RL = 110 Ω, RE at 0 V,
See Figure 5
Propagation delay time, high-level-to-high-
impedance output
55
300
26
Propagation delay time, high-impedance-to-low-
level output
55
300
26
RL = 110 Ω, RE at 0 V,
See Figure 6
Propagation delay time, low-level-to-high-
impedance output
75
400
RL = 110 Ω, RE at 3 V,
See Figure 5
tPZH
tPZL
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
6
6
μs
μs
RL = 110 Ω, RE at 3 V,
See Figure 6
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD11Q SN75HVD11
SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
–0.065 –0.01
MAX UNIT
VIT+
VIT–
Positive-going input threshold voltage IO = –8 mA
V
Negative-going input threshold
IO = 8 mA
–0.2
–0.1
35
voltage
Vhys
VIK
Hysteresis voltage (VIT+ - VIT-
Enable-input clamp voltage
High-level output voltage
Low-level output voltage
)
mV
V
II = –18 mA
–1.5
2.4
VOH
VOL
IOZ
VID = 200 mV,
VID = –200 mV,
IOH = –8 mA,
IOL = 8 mA,
RE at VCC
See Figure 7
See Figure 7
V
0.4
1
V
High-impedance-state output current VO = 0 or VCC
VA or VB = 12 V
–1
μA
0.05
0.06
0.11
0.13
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
HVD11, HVD12,
Other input at 0 V
mA
mA
–0.1
–0.05
–0.04
0.2
VA or VB = –7 V, VCC = 0 V
VA or VB = 12 V
–0.05
II
Bus input current
0.5
0.5
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
0.25
HVD10,
Other input at 0 V
–0.4
–0.4
–30
–30
–0.2
VA or VB = –7 V, VCC = 0 V
VIH = 2 V
–0.15
IIH
High-level input current, RE
Low-level input current, RE
Differential input capacitance
0
0
μA
μA
pF
IIL
VIL = 0.8 V
CID
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
15
4
RE at 0 V,
D & DE at 0 V,
No load
Receiver enabled and driver
disabled
8
5
mA
RE at VCC
,
D at VCC
DE at 0 V,
No load
,
Receiver disabled and driver
disabled (standby)
ICC
Supply current
1
9
μA
RE at 0 V,
D & DE at VCC
No load
Receiver enabled and driver
enabled
,
15.5
mA
(1) All typical values are at 25°C and with a 3.3-V supply.
Copyright © 2002–2013, Texas Instruments Incorporated
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Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD11Q SN75HVD11
SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output HVD10
Propagation delay time, high-to-low-level output HVD10
12.5
12.5
20
20
25
ns
25
HVD11
Propagation delay time, low-to-high-level output
HVD12
tPLH
tPHL
30
30
55
55
70
70
ns
ns
VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 8
HVD11
Propagation delay time, high-to-low-level output
HVD12
HVD10
1.5
4
tsk(p)
Pulse skew (|tPHL – tPLH|)
Part-to-part skew
HVD11
HVD12
HVD10
HVD11
HVD12
ns
4
8
(2)
tsk(pp)
15
15
5
ns
ns
tr
tf
Output signal rise time
1
1
2
2
CL = 15 pF,
See Figure 8
Output signal fall time
5
(1)
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
Output enable time to high level
Output enable time to low level
Output disable time from high level
Output disable time from low level
15
15
20
15
6
(1)
CL = 15 pF, DE at 3 V,
See Figure 9
ns
(2)
(2)
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
CL = 15 pF, DE at 0,
See Figure 10
μs
6
(1) All typical values are at 25°C and with a 3.3-V supply
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
High−K board(3), No airflow
No airflow(4)
MIN
TYP
121
93
MAX
UNIT
D pkg
P pkg
D pkg
P pkg
D pkg
P pkg
Junction−to−ambient thermal
θJA
θJB
θJC
resistance(2)
High−K board
67
Junction−to−board thermal
resistance
°C/W
(4)
See
57
41
Junction−to−case thermal
resistance
55
HVD10
(32 Mbps)
198
250
176
161
RL= 60 Ω, CL = 50 pF,
DE at VCC, RE at 0 V,
Input to D a 50% duty cycle square
wave at indicated signaling rate
HVD11
(10 Mbps)
141
133
PD
Device power dissipation
Ambient air temperature
mW
°C
HVD12
(500 kbps)
High−K board, No airflow
No airflow(4)
D pkg
P pkg
–40
–40
116
123
TA
TJSD Thermal shutdown junction temperature
165
(1) See Application Information section for an explanation of these parameters.
(2) The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
(4) JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION
375 Ω ±1%
V
CC
V
CC
I
I
DE
OA
I
I
DE
A
B
A
B
D
V
OD
54 Ω ±1%
0 or 3 V
V
OD
60 Ω ±1%
0 or 3 V
+
_
−7 V < V
< 12 V
OB
(test)
V
I
375 Ω ±1%
V
OB
V
OA
Figure 1. Driver VOD Test Circuit and Voltage and
Current Definitions
Figure 2. Driver VOD With Common-Mode Loading
Test Circuit
V
A
B
A
V
CC
27 Ω ± 1%
27 Ω ± 1%
V
B
DE
A
B
D
V
OC(PP)
∆V
Input
OC(SS)
V
OC
V
C
L
= 50 pF ±20%
OC
C
L
Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t <6ns, t <6ns, Z = 50 Ω
r
f
O
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3 V
V
CC
1.5 V
1.5 V
V
I
DE
C = 50 pF ±20%
L
A
B
V
OD
D
t
t
PHL
C Includes Fixture
PLH
L
and Instrumentation
Capacitance
≈ 2 V
Input
Generator
R = 54 Ω
± 1%
90%
90%
L
V
I
50 Ω
0 V
10%
0 V
10%
V
OD
≈ –2 V
t
r
t
f
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
3 V
0 V
A
S1
D
V
O
V
1.5 V
1.5 V
I
3 V
B
C
DE
0.5 V
R
L
= 110 Ω
= 50 pF ±20%
t
L
PZH
Input
Generator
± 1%
V
OH
V
I
C
Includes Fixture
50 Ω
L
and Instrumentation
Capacitance
V
O
2.3 V
≈ 0 V
t
PHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
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SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
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PARAMETER MEASUREMENT INFORMATION (continued)
3 V
R
± 1%
= 110 Ω
L
≈ 3 V
A
V
I
1.5 V
1.5 V
S1
D
V
O
3 V
0 V
B
C
t
t
PLZ
PZL
DE
50 Ω
≈ 3 V
= 50 pF ±20%
Input
Generator
L
V
I
0.5 V
C
Includes Fixture
L
V
O
2.3 V
and Instrumentation
Capacitance
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
A
B
I
O
R
V
A
V
I
ID
V
B
V
IC
V
O
B
V
A
+ V
2
B
Figure 7. Receiver Voltage and Current Definitions
A
V
O
R
Input
Generator
V
I
50 Ω
B
1.5 V
0 V
C = 15 pF ±20%
L
RE
C Includes Fixture
L
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
1.5 V
V
I
0 V
t
t
PHL
PLH
V
V
OH
90% 90%
V
O
1.5 V
10%
1.5 V
10%
OL
t
r
t
f
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
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SN65HVD12 SN75HVD12
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SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
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SLLS505M –FEBRUARY 2002–REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
DE
3 V
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
R
V
O
D
S1
B
0 V or 3 V
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
V
I
1.5 V
1.5 V
0 V
V
t
t
PHZ
PZH(1)
OH
D at 3 V
S1 to B
V
OH
–0.5 V
1.5 V
V
O
≈ 0 V
t
t
PLZ
PZL(1)
≈ 3 V
D at 0 V
S1 to A
1.5 V
V
O
V
OL
+0.5 V
V
OL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Copyright © 2002–2013, Texas Instruments Incorporated
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
0 V or 1.5 V
1.5 V or 0 V
R
V
O
S1
B
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
V
I
0 V
V
t
PZH(2)
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL(2)
3 V
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
RE
A
R
B
100 Ω
± 1%
Pulse Generator,
15 µs Duration,
1% Duty Cycle
D
+
_
t , t ≤ 100 ns
r
f
DE
3 V or 0 V
:
NOTE This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
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SLLS505M –FEBRUARY 2002–REVISED JULY 2013
PARAMETER MEASUREMENT INFORMATION (continued)
FUNCTION TABLES
Table 1. DRIVER(1)
OUTPUTS
INPUT
D
ENABLE
A
B
DE
H
L
H
H
L
L
H
Z
L
H
X
L
Z
H
Open
H
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? =
indeterminate
Table 2. RECEIVER(1)
DIFFERENTIAL INPUTS
VID = VA – VB
ENABLE
RE
OUTPUT
R
VID ≤ –0.2 V
–0.2 V < VID < –0.01 V
−0.01 V ≤ VID
X
L
L
L
H
L
L
L
?
H
Z
H
H
Open Circuit
Short circuit
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? =
indeterminate
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
16 V
R3
R1
R1
R3
R2
Input
Input
R2
16 V
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
R1/R2
9 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
SN65HVD10
SN65HVD11
SN65HVD12
36 kΩ
36 kΩ
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Product Folder Links: SN65HVD10 SN65HVD10Q SN75HVD10 SN65HVD11 SN65HVD11Q SN75HVD11
SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
TYPICAL CHARACTERISTICS
HVD10
RMS SUPPLY CURRENT
vs
HVD11
RMS SUPPLY CURRENT
vs
SIGNALING RATE
SIGNALING RATE
70
70
T
= 25°C
R = 54 Ω
L
C = 50 pF
L
A
T
= 25°C
R = 54 Ω
L
A
V
CC
= 3.6 V
RE at V
DE at V
CC
CC
RE at V
DE at V
C
L
= 50 pF
CC
CC
V
CC
= 3.6 V
60
50
60
50
V
CC
= 3 V
V
CC
= 3 V
V
CC
= 3.3 V
V
= 3.3 V
40
30
40
30
CC
0
2.5
5
7.5
10
0
5
10
15
20
25
30
35
40
Signaling Rate − Mbps
Signaling Rate − Mbps
Figure 12.
Figure 13.
HVD12
HVD10
RMS SUPPLY CURRENT
vs
BUS INPUT CURRENT
vs
SIGNALING RATE
BUS INPUT VOLTAGE
70
300
250
200
T
= 25°C
R = 54 Ω
L
C = 50 pF
L
A
T
A
= 25°C
RE at V
DE at V
CC
CC
DE at 0 V
V
CC
= 3.6 V
60
50
V
CC
= 0 V
150
100
50
V
= 3.3 V
CC
V
= 3 V
CC
V
CC
= 3.3 V
0
−50
40
30
−100
−150
−200
100
400
700
1000
−7−6−5 −4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
Signaling Rate − kbps
V − Bus Input Voltage − V
I
Figure 14.
Figure 15.
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
HVD11 OR HVD12
BUS INPUT CURRENT
vs
HIGH-LEVEL OUTPUT CURRENT
vs
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
BUS INPUT VOLTAGE
150
100
50
90
80
70
60
50
40
T
= 25°C
T
= 25°C
A
A
DE at 0 V
DE at V
D at V
V
CC
CC
= 3.3 V
CC
V
CC
= 0 V
30
20
0
10
0
−50
−100
−150
−200
V
CC
= 3.3 V
−10
−20
−30
−40
−50
−60
−7−6−5−4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
−4
−2
0
2
4
6
V
OH
− Driver High-Level Output Voltage − V
V − Bus Input Voltage − V
I
Figure 16.
Figure 17.
LOW-LEVEL OUTPUT CURRENT
vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE
DRIVER DIFFERENTIAL OUTPUT
vs
FREE-AIR TEMPERATURE
200
180
160
140
120
100
2.5
T
= 25°C
V
= 3.3 V
A
CC
2.4
2.3
DE at V
DE at V
D at V
CC
CC
D at 0 V
= 3.3 V
CC
V
CC
2.2
2.1
2.0
1.9
1.8
1.7
1.6
80
60
40
20
0
−20
1.5
−40
−15
T
10
35
60
85
−4
−2
0
2
4
6
8
− Free-Air Temperature − °C
V
− Driver Low-Level Output Voltage − V
A
OL
Figure 18.
Figure 19.
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SN65HVD12 SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
TYPICAL CHARACTERISTICS (continued)
ENABLE TIME
vs
DRIVER OUTPUT CURRENT
vs
COMMON-MODE VOLTAGE
(SEE Figure 22)
SUPPLY VOLTAGE
600
500
400
−40
T
= 25°C
A
DE at V
D at V
R = 54 Ω
CC
−35
−30
−25
−20
−15
−10
CC
L
HVD12
HVD11
300
200
HVD10
100
0
−5
0
-7
-2
3
8
13
0
0.50
1
1.50
2
2.50
3
3.50
V
CC
− Supply Voltage − V
V
− Common-Mode Voltage − V
(TEST)
Figure 20.
Figure 21.
375 W ± 1%
Y
-7 V < V(TEST) < 12 V
D
60 W
± 1%
VOD
0 or 3 V
Z
DE
50 W
375 W ± 1%
Input
V
Generator
50%
tpZH(diff)
VOD (high)
1.5 V
0 V
tpZL(diff)
-1.5 V
VOD (low)
Figure 22. Driver Enable Time From DE to VOD
The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
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15
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
APPLICATION INFORMATION
R
T
R
T
Stub
Device
HVD10
HVD11
HVD12
Number of Devices on Bus
64
256
256
:
NOTE The line should be terminated at both ends with its characteristic impedance (R = Z ). Stub lengths off the main line
T
O
should be kept as short as possible.
Figure 23. Typical Application Circuit
Driver Input
Driver Output
Receiver Input
Receiver Output
Figure 24. HVD12 Input and Output Through 2000 Feet of Cable
An example application for the HVD12 is illustrated in Figure 23. Two HVD12 transceivers are used to
communicate data through a 2000 foot (600 m) length of Commscope 5524 category 5e+ twisted pair cable. The
bus is terminated at each end by a 100-Ω resistor, matching the cable characteristic impedance. Figure 24
illustrates operation at a signaling rate of 250 kbps.
LOW-POWER STANDBY MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this
state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
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SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
www.ti.com
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
•
•
•
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards.
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 25.
Figure 25. Thermal Resistance
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SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505M –FEBRUARY 2002–REVISED JULY 2013
www.ti.com
REVISION HISTORY
Changes from Revision J (February 2009) to Revision K
Page
•
Added new section 'LOW-POWER STANDBY MODE', in the Application Information section ......................................... 16
Changes from Revision K (September 2011) to Revision L
Page
•
•
Added TYP = –0.65 V to VIT+ ................................................................................................................................................ 5
Added TYP = –0.1 V to VIT– .................................................................................................................................................. 5
Changes from Revision L (July 2013) to Revision M
Page
•
Changed the VIT+ TYP value From: –0.65 V To: –0.065 V ................................................................................................... 5
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2013
PACKAGING INFORMATION
Orderable Device
SN65HVD10D
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
VP10
VP10
VP10
VP10
SN65HVD10DG4
SN65HVD10DR
SN65HVD10DRG4
SN65HVD10P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
P
P
D
D
D
D
D
D
D
D
P
P
D
75
2500
2500
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
65HVD10
65HVD10
VP10Q
VP10Q
VP10Q
VP10Q
VP11
SN65HVD10PE4
SN65HVD10QD
SN65HVD10QDG4
SN65HVD10QDR
SN65HVD10QDRG4
SN65HVD11D
50
Pb-Free
(RoHS)
N / A for Pkg Type
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
75
Green (RoHS
& no Sb/Br)
2500
2500
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN65HVD11DG4
SN65HVD11DR
SN65HVD11DRG4
SN65HVD11P
75
Green (RoHS
& no Sb/Br)
VP11
2500
2500
50
Green (RoHS
& no Sb/Br)
VP11
Green (RoHS
& no Sb/Br)
VP11
Pb-Free
(RoHS)
65HVD11
65HVD11
VP11Q
SN65HVD11PE4
SN65HVD11QD
50
Pb-Free
(RoHS)
N / A for Pkg Type
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN65HVD11QDG4
SN65HVD11QDR
ACTIVE
SOIC
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
VP11Q
ACTIVE
D
2500
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
VP11Q
SN65HVD11QDRG4
SN65HVD12D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
TBD
Call TI
Call TI
-40 to 125
-40 to 85
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
VP12
SN65HVD12DG4
SN65HVD12DR
SN65HVD12DRG4
SN65HVD12P
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
D
D
D
P
P
D
D
D
D
P
P
D
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
VP12
2500
2500
50
Green (RoHS
& no Sb/Br)
VP12
Green (RoHS
& no Sb/Br)
VP12
Pb-Free
(RoHS)
65HVD12
65HVD12
VN10
SN65HVD12PE4
SN75HVD10D
50
Pb-Free
(RoHS)
N / A for Pkg Type
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SN75HVD10DG4
SN75HVD10DR
SN75HVD10DRG4
SN75HVD10P
75
Green (RoHS
& no Sb/Br)
0 to 70
VN10
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
VN10
Green (RoHS
& no Sb/Br)
0 to 70
VN10
Pb-Free
(RoHS)
0 to 70
75HVD10
75HVD10
VN11
SN75HVD10PE4
SN75HVD11D
50
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
SN75HVD11DG4
SN75HVD11DR
75
Green (RoHS
& no Sb/Br)
0 to 70
VN11
2500
Green (RoHS
& no Sb/Br)
0 to 70
VN11
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN75HVD11DRG4
SN75HVD12D
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
8
8
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
VN11
VN12
VN12
VN12
VN12
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
P
P
75
75
Green (RoHS
& no Sb/Br)
0 to 70
SN75HVD12DG4
SN75HVD12DR
SN75HVD12DRG4
SN75HVD12P
Green (RoHS
& no Sb/Br)
0 to 70
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Pb-Free
(RoHS)
0 to 70
75HVD12
75HVD12
SN75HVD12PE4
50
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :
Enhanced Product: SN65HVD10-EP, SN65HVD12-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD10DR
SN65HVD10QDR
SN65HVD11DR
SN65HVD11QDR
SN65HVD12DR
SN75HVD10DR
SN75HVD11DR
SN75HVD12DR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65HVD10DR
SN65HVD10QDR
SN65HVD11DR
SN65HVD11QDR
SN65HVD12DR
SN75HVD10DR
SN75HVD11DR
SN75HVD12DR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
340.5
340.5
340.5
340.5
340.5
340.5
340.5
340.5
338.1
338.1
338.1
338.1
338.1
338.1
338.1
338.1
20.6
20.6
20.6
20.6
20.6
20.6
20.6
20.6
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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相关型号：
SN65HVD10QPE4
IC LINE TRANSCEIVER, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8, Line Driver or Receiver
TI
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