SN65HVD11-HT_15 [TI]
3.3-V RS-485 Transceiver;
| 型号： | SN65HVD11-HT_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V RS-485 Transceiver |
| 文件： | 总30页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD11-HT
www.ti.com
SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
3.3-V RS-485 TRANSCEIVER
Check for Samples: SN65HVD11-HT
1
FEATURES
SUPPORTS EXTREME TEMPERATURE
APPLICATIONS
•
Operates With a 3.3-V Supply
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Extreme (–55°C/210°C)
Temperature Range(2)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Texas Instruments' high temperature products
utilize highly optimized silicon (die) solutions
with design and process enhancements to
maximize performance over extended
temperatures.
•
Bus-Pin ESD Protection Exceeds 16-kV
Human-Body Model (HBM)
•
•
1/8 Unit-Load Option Available (up to 256
Nodes on Bus)
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 10 Mbps, and
32 Mbps
•
•
•
•
•
•
Based on ANSI TIA/EIA-485-A
Bus-Pin Short Circuit Protection From
–7 V to 12 V
•
•
•
Open-Circuit, Idle-Bus, and Shorted-Bus
Fail-Safe Receiver
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
DESCRIPTION/ORDERING INFORMATION
SN75176 Footprint
The SN65HVD11 combines a 3-state differential line
driver and differential input line receiver that operates
with a single 3.3-V power supply. It is designed for
balanced transmission lines and meets or exceeds
ANSI TIA/EIA-485-A and ISO 8482:1993, with the
exception that the thermal shutdown is removed. This
differential bus transceiver is a monolithic integrated
circuit designed for bidirectional data communication
on multipoint bus-transmission lines. The driver and
receiver have active-high and active-low enables,
respectively, that can be externally connected
together to function as direction control.
APPLICATIONS
•
•
•
•
•
•
•
•
•
Down-Hole Drilling
High Temperature Environments
Digital Motor Controls
Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus when the driver is
disabled or VCC = 0.
Point-of-Sale (POS) Terminals and Networks
D OR JD OR HKJ PACKAGE
(TOP VIEW)
R
RE
DE
D
VCC
B
1
2
3
4
8
7
6
5
A
GND
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bits per second (bps).
(2) Custom temperature ranges available
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD11-HT
SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
www.ti.com
BARE DIE INFORMATION
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
DIE THICKNESS
BACKSIDE FINISH
15 mils.
Silicon with backgrind
GND
Cu-Ni-Pd
Table 1. Bond Pad Coordinates in Microns - Rev A
DESCRIPTION(1)
PAD NUMBER
a
b
c
d
R
1
2
69.30
372.15
71.50
185.30
503.75
839.40
1008.40
1289.80
1869.35
2022.35
2395.55
2848.50
2808
489.15
186.50
172.40
172.40
186.50
180.40
180.40
184.50
486.50
1810.10
1810.10
1800.65
1810.10
1810.10
1796.20
1783.50
1783.50
~RE
DNC
DNC
DE
388.75
722.40
891.40
1174.80
1754.35
1907.35
2280.55
2733.50
2691
3
55.40
4
55.40
5
71.50
DNC
DNC
D
6
65.40
7
65.40
8
69.50
DNC
GND
GND
DNC
A
9
371.50
1693.10
1693.10
1685.65
1693.10
1693.10
1681.20
1668.50
1668.50
10
11
12
13
14
15
16
17
2535
2652
2253.45
1961.55
799.55
498.35
244.80
91.80
2368.45
2078.55
916.55
613.35
359.80
206.80
B
DNC
VCC
VCC
(1) DNC = Do Not Connect
2
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Product Folder Link(s): SN65HVD11-HT
SN65HVD11-HT
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
Copyright © 2008–2010, Texas Instruments Incorporated
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Product Folder Link(s): SN65HVD11-HT
SN65HVD11-HT
SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PACKAGE(2)
SIGNALING RATE
UNIT LOADS
TA
TOP-SIDE MARKING
CDIP
10 Mbps
10 Mbps
10 Mbps
10 Mbps
1/8
1/8
1/8
1/8
–55°C to 210°C
–55°C to 210°C
–55°C to 210°C
–55°C to 175°C
SN65HVD11SJD
SN65HVD11SKGDA
SN65HVD11SHKJ
SN65HVD11HD
SN65HVD11SJD
SN65HVD11SHKJ
HD11
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTIONAL BLOCK DIAGRAM
1
R
2
RE
3
DE
6
A
4
D
7
B
ABSOLUTE MAXIMUM RATINGS(1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 6
–9 to 14
–0.5 to VCC + 0.5
–50 to 50
–11 to 11
16
UNIT
V
VCC Supply voltage range
Voltage range at A or B
V
Input voltage range at D, DE, R, or RE
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 12)
V
V
IO
Receiver output current range
mA
A, B, and GND
All pins
Human-Body Model
(HBM)(3)
4
Electrostatic discharge
kV
Charged-Device Model
(CDM)(4)
All pins charge
1
Continuous total power dissipation
See Dissipation Ratings Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
4
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
RECOMMENDED OPERATING CONDITIONS
TA = –55°C to 125°C
TA = 175°C
NOM
TA = 210°C
NOM MAX
UNIT
MIN
NOM MAX
MIN
MAX
MIN
VCC
Supply voltage
3
3.6
3
3.6
3
3.6
12
V
V
VI or
VIC
Voltage at any bus terminal (separately or common mode)
-7(1)
12
-7(1)
12
-7(1)
VIH
VIL
VID
High-level input voltage
Low-level input voltage
Differential input voltage
D, DE, RE
D, DE, RE
Figure 8
Driver
2
0
VCC
0.8
12
2
0
VCC
0.8
12
2
0
VCC
0.8
12
V
V
V
-12
-60
-8
-12
-60
-8
-12
-60
-8
IOH
High-level output current
Low-level output current
mA
mA
Receiver
Driver
60
60
8
60
8
IOL
Receiver
8
RL
CL
Differential load resistance
Differential load capacitance
Signaling rate
54
60
50
54
60
50
54
60
50
Ω
pF
10
10
10
Mbps
°C
(2)
TJ
Operating junction temperature
129
179
214
(1) The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet.
(2) See Thermal Characteristics table for information regarding this specification.
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TA = –55°C to 125°C
TA = 175°C(1)
TYP
TA = 210°C(2)
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
Input clamp
voltage
VIK
II = –18 mA
–1.5
–1.5
–1.5
V
IO = 0
2
VCC
2
1
VCC
2
1
VCC
Differential
output voltage
RL = 54 Ω, See Figure 2
1.0
|VOD
|
V
V
Vtest = –7 V to 12 V,
See Figure 3
1.0
1
1
Change in
magnitude of
differential
Vtest = –7 V to 12 V,
See Figure 2 and Figure 3
Δ|VOD
|
-0.2
0.2
-0.25
0.25
-0.25
0.25
output voltage
Peak-to-peak
common-mode
output voltage
VOC(PP)
See Figure 4
See Figure 4
400
400
400
mV
V
Steady-state
common-mode
output voltage
VOC(SS)
1.4
2.5
1.4
2.5
1.4
2.5
Change in
steady-state
common-mode
output voltage
ΔVOC(SS)
See Figure 4
–0.06
0.06
–0.06
0.06
–0.06
0.06
V
High-impedance
output current
IOZ
See receiver input currents
D
–100
0
0
–100
0
3
–100
0
3
Input
current
II
mA
DE
100
100
100
Short-circuit
output current
IOS
–7 V ≤ VO ≤ 12 V
–250
250
–250
250
–250
250
mA
Differential
output
capacitance
VOD = 0.4 sin (4E6pt) + 0.5 V,
DE = 0 V
C(OD)
18
11
18
18
14
pF
RE = VCC
D and
DE = VCC,
No load
,
Receiver
disabled and
driver enabled
15.5
20
11.5
17.5
150
18
450
18
mA
RE = VCC
,
Receiver
D = VCC
DE = 0 V,
No load
,
disabled and
driver disabled
(standby)
ICC
Supply current
2.5
11
20
11
175
11
mA
RE = 0 V,
D and
Receiver
enabled and
driver enabled
15.5
17.5
mA
DE = VCC
,
No load
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
6
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Product Folder Link(s): SN65HVD11-HT
SN65HVD11-HT
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TA = –55°C to 125°C
TA = 175°C(1)
TYP
TA = 210°C(2)
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
TYP
MAX
Propagation delay time,
low-to-high-level output
tPLH
tPHL
tr
18
18
10
10
25
40
40
30
18
25
25
22
22
40
18
25
40
40
30
ns
ns
ns
Propagation delay time,
high-to-low-level output
25
21
21
18
10
10
40
30
18
10
10
25
22
22
Differential output signal
rise time
RL = 54 Ω,
CL = 50 pF,
See Figure 5
Differential output signal
fall time
tf
30
2.5
11
30
2.5
11
30
2.5
11
ns
ns
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
Part-to-part skew (tPHL or
(3)
tsk(pp)
tPLH
)
Propagation delay time,
high-impedance to
high-level output
RL = 110 Ω,
RE = 0 V,
See Figure 6
tPZH
tPHZ
tPZL
tPLZ
tPZH
tPZL
55
55
55
75
6
55
55
55
75
6
55
55
55
75
6
ns
ns
ns
ns
ms
ms
Propagation delay time,
high-level to
high-impedance output
Propagation delay time,
high-impedance to
low-level output
RL = 110 Ω,
RE = 0 V,
See Figure 7
Propagation delay time,
low-level to
high-impedance output
Propagation delay time,
standby to high-level
output
RL = 110 Ω,
RE = 3 V,
See Figure 6
RL = 110 Ω,
RE = 3 V,
See Figure 7
Propagation delay time,
standby to low-level output
6
6
6
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2008–2010, Texas Instruments Incorporated
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TA = –55°C to 125°C
TA = 175°C(1)
TYP
TA = 210°C(2)
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
TYP
MAX
Positive-going
VIT+ input threshold IO = –8 mA
voltage
–0.01
–0.01
–0.01
V
Negative-going
VIT– input threshold IO = 8 mA
voltage
–0.2
–0.2
–0.2
V
Hysteresis
Vhys voltage
35
41
41
mV
(VIT+ –VIT–
)
Enable-input
clamp voltage
VIK
II = –18 mA
–1.5
2.4
–1.5
2.4
–1.5
2.4
V
V
V
High-level
output voltage
VID = 200 mV, IOH = –8 mA,
See Figure 8
VOH
VOL
Low-level
output voltage
VID = –200 mV, IOL = 8 mA,
See Figure 8
0.4
1
0.4
1
0.4
1
High-
impedance
state output
current
IOZ
VO = 0 or VCC, RE = VCC
–1
–1
–1
mA
VA or VB = 12 V
0.075
0.085
–0.05
–0.05
0.11
0.13
0.1
0.15
0.16
0.1
0.15
0.16
Other
input
at 0 V
VA or VB = 12 V, VCC = 0 V
VA or VB = –7 V
0.12
0.12
Bus input
current
II
mA
–0.1
–0.1
–0.3
–0.3
–0.15
–0.15
–0.3
–0.3
–0.15
–0.15
VA or VB = –7 V, VCC = 0 V
High-level input
current, RE
IIH
IIL
VIH = 2 V
–30
–30
0
0
–30
–30
3
0
–30
–30
3
0
mA
mA
Low-level input
current, RE
VIL = 0.8 V
Differential
CID input
capacitance
VID = 0.4 sin (4E6pt) + 0.5 V,
DE at 0 V
15
5
18
18
pF
RE = 0 V,
D and DE = 0 V, and driver
No load
Receiver enabled
8
7.5
8.5
200
17.5
7.5
10
450
18
mA
disabled
RE = VCC
,
Receiver disabled
and driver
disabled (standby)
D = VCC
,
ICC
Supply current
2.5
11
20
12.5
11.5
175
14
mA
DE = 0 V,
No load
RE = 0 V,
D and DE = VCC
No load
Receiver enabled
and driver enabled
,
15.5
mA
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
8
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Product Folder Link(s): SN65HVD11-HT
SN65HVD11-HT
www.ti.com
SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TA = –55°C to 125°C
TA = 175°C(1)
TYP
TA = 210°C(2)
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
TYP
MAX
Propagation delay time,
low-to-high-level output
tPLH
tPHL
30
30
55
70
70
30
55
55
70
30
55
70
70
ns
ns
VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 9
Propagation delay time,
high-to-low-level output
55
30
70
30
55
tsk(p)
tsk(pp)
tr
Pulse skew (|tPHL – tPLH|)
Part-to-part skew
4
15
5
4
15
5
4
15
5
ns
ns
ns
ns
(3)
Output signal rise time
Output signal fall time
1
1
3
3
1
1
4
4
1
1
4
4
CL = 15 pF,
See Figure 9
tf
5
5
5
Output enable time to high
level
(2)
tPZH
tPZL
tPHZ
tPLZ
15
15
20
15
15
15
20
15
15
15
20
15
ns
ns
ns
ns
Output enable time to low
level
(2)
CL = 15 pF, DE = 3 V,
See Figure 10
Output disable time from
high level
Output disable time from
low level
Propagation delay time,
standby-to-high-level
output
(3)
tPZH
6
6
6
6
6
6
ms
ms
CL = 15 pF, DE = 0,
See Figure 11
Propagation delay time,
standby-to-low-level output
(3)
tPZL
(1) Minimum and maximum parameters are characterized for operation at TA = 175°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
(2) Minimum and maximum parameters are characterized for operation at TA = 210°C but may not be production tested at that temperature.
Production test limits with statistical guardbands are used to ensure high temperature performance.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
THERMAL CHARACTERISTICS FOR JD PACKAGE
over operating free-air temperature range unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
High-K board(3), No airflow
No airflow
MIN
TYP
64.9
83.4
MAX
UNIT
JD pkg
JD pkg
Junction-to-ambient thermal
resistance(2)
qJA
°C/W
Junction-to-board thermal
resistance
qJB
qJC
High-K board without underfill
JD pkg
JD pkg
27.9
6.49
°C/W
°C/W
Junction-to-case thermal
resistance
RL= 60 Ω, CL = 50 pF,
DE = VCC, RE = 0 V,
Input to D a 50% duty cycle square
wave at indicated signaling rate
HVD11
(10 Mbps)
PD
Device power dissipation
165
mW
(1) See Application Information section for an explanation of these parameters.
(2) The intent of qJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
(3) JED51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
THERMAL CHARACTERISTICS FOR HKJ PACKAGE
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
MAX
5.7
UNIT
Junction-to-case thermal resistance (to bottom of case)
qJC
°C/W
Junction-to-case thermal resistance (to top of case lid - as if formed dead bug)
13.7
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THERMAL CHARACTERISTICS FOR D PACKAGE
over operating free-air temperature range (unless otherwise noted)
PARAMETERS
MAX
UNIT
qJC
Junction-to-case thermal resistance (to bottom of case)
39.4
°C/W
xxx
1000000
100000
Electromigration Fail Mode
10000
Wirebond Fail Mode
1000
110
120
130
140
150
160
170
180
190
200
210
Continuous TJ (°C)
(1) See data sheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the
dominant failure mechanism affecting device wearout for the specific device process and design characteristics.
(4) Wirebond fail mode applicable for D package only.
Figure 1. SN65HVD11SJD/SN65HVD11SKGDA/SN65HVD11SHKJ/SN65HVD11HD
Operating Life Derating Chart
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION
375 Ω ±1%
V
CC
V
CC
I
I
DE
OA
I
I
DE
A
B
A
B
D
V
OD
54 Ω ±1%
0 or 3 V
V
OD
60 Ω ±1%
0 or 3 V
+
_
−7 V < V
< 12 V
OB
(test)
V
I
375 Ω ±1%
V
OB
V
OA
Figure 2. Driver VOD Test Circuit and Voltage and
Current Definitions
Figure 3. Driver VOD With Common-Mode Loading
Test Circuit
V
A
B
A
V
CC
27 Ω ± 1%
27 Ω ± 1%
V
B
DE
A
B
D
V
OC(PP)
∆V
Input
OC(SS)
V
OC
V
OC
C
L
= 50 pF ±20%
Input: PRR = 500 kHz, 50% Duty Cycle, t <6ns, t <6ns, Z = 50 Ω
O
A.
r
f
B. C Includes fixture and instrumentation capacitance
L
Figure 4. Test Circuit and Definitions for Driver Common-Mode Output Voltage
3 V
V
CC
1.5 V
1.5 V
V
I
DE
C
C
= 50 pF ±20%
L
A
B
V
OD
D
t
t
PHL
Includes Fixture
and Instrumentation
Capacitance
PLH
L
≈ 2 V
Input
Generator
R
± 1%
= 54 Ω
90%
90%
L
V
I
50 Ω
0 V
10%
0 V
10%
V
OD
≈ –2 V
t
r
t
f
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
3 V
0 V
A
S1
D
V
O
V
1.5 V
1.5 V
I
3 V
B
C
DE
0.5 V
R
L
= 110 Ω
= 50 pF ±20%
t
L
PZH
Input
Generator
± 1%
V
OH
V
I
C
Includes Fixture
50 Ω
L
and Instrumentation
Capacitance
V
O
2.3 V
≈ 0 V
t
PHZ
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 6. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
3 V
R
± 1%
= 110 Ω
L
≈ 3 V
A
V
I
1.5 V
1.5 V
S1
D
V
O
3 V
0 V
B
C
t
t
PLZ
PZL
DE
50 Ω
≈ 3 V
= 50 pF ±20%
Input
Generator
L
V
I
0.5 V
C
Includes Fixture
L
V
O
2.3 V
and Instrumentation
Capacitance
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
A
B
I
O
R
V
A
V
I
ID
V
B
V
IC
V
O
B
V
A
+ V
2
B
Figure 8. Receiver Voltage and Current Definitions
A
V
O
R
Input
Generator
V
I
50 Ω
B
1.5 V
0 V
C = 15 pF ±20%
L
RE
C Includes Fixture
L
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
1.5 V
V
I
0 V
t
t
PHL
PLH
V
V
OH
90% 90%
V
O
1.5 V
10%
1.5 V
10%
OL
t
r
t
f
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION (continued)
3 V
DE
3 V
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
R
V
O
D
S1
B
0 V or 3 V
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
V
I
1.5 V
1.5 V
0 V
V
t
t
PHZ
PZH(1)
OH
D at 3 V
S1 to B
V
OH
–0.5 V
1.5 V
V
O
≈ 0 V
t
t
PLZ
PZL(1)
≈ 3 V
D at 0 V
S1 to A
1.5 V
V
O
V
OL
+0.5 V
V
OL
Figure 10. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
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PARAMETER MEASUREMENT INFORMATION (continued)
3 V
A
B
A
1 kΩ ± 1%
= 15 pF ±20%
0 V or 1.5 V
1.5 V or 0 V
R
V
O
S1
B
C
C
L
RE
Includes Fixture
and Instrumentation
Capacitance
L
Input
Generator
V
I
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r
f
o
3 V
1.5 V
V
I
0 V
V
t
PZH(2)
OH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
V
O
GND
t
PZL(2)
3 V
A at 0 V
B at 1.5 V
S1 to A
1.5 V
V
O
V
OL
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
RE
A
R
B
100 Ω
± 1%
Pulse Generator,
15 µs Duration,
1% Duty Cycle
D
+
_
t , t ≤ 100 ns
r
f
DE
3 V or 0 V
:
NOTE This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 12. Test Circuit, Transient Over Voltage Test
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION (continued)
FUNCTION TABLES
Table 2. DRIVER(1)
OUTPUTS
INPUT
D
ENABLE
A
B
DE
H
L
H
H
L
L
H
Z
L
H
X
L
Z
H
Open
H
(1) H = high level
L = low level
Z = high impedance
X = irrelevant
? = indeterminate
Table 3. RECEIVER(1)
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE
RE
OUTPUT
R
V
ID ≤ −0.2 V
L
L
L
H
L
L
L
?
−0.2 V < VID < −0.01 V
−0.01 V ≤ VID
X
H
Z
H
H
Open circuit
Short circuit
(1) H = high level
L = low level
Z = high impedance
X = irrelevant
? = indeterminate
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www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
V
CC
V
CC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
16 V
R3
R1
R1
R3
Input
Input
R2
R2
16 V
16 V
A and B Outputs
R Output
V
CC
V
CC
16 V
5 Ω
Output
9 V
Output
16 V
R1/R2 = 36 kΩ
R3 = 180 kΩ
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT
BUS INPUT CURRENT
vs
vs
SIGNALING RATE
BUS INPUT VOLTAGE
70
90
80
70
60
50
40
30
20
T
= 25°C
R = 54 Ω
L
C = 50 pF
L
T
A
= 25°C
A
V
= 3.6 V
RE at V
DE at V
DE at 0 V
CC
CC
CC
60
50
V
CC
= 0 V
10
0
V
CC
= 3.3 V
V
= 3 V
CC
−10
V
CC
= 3.3 V
−20
−30
−40
−50
−60
40
30
−7−6−5−4−3−2−1 0 1 2 3 4 5 6 7 8 9 1011 12
0
2.5
5
7.5
10
V − Bus Input Voltage − V
I
Signaling Rate − Mbps
Figure 13.
Figure 14.
HIGH-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT CURRENT
vs
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
150
100
50
200
180
160
140
120
100
T
= 25°C
T
= 25°C
A
A
DE at V
D at V
V
DE at V
CC
CC
D at 0 V
= 3.3 V
CC
= 3.3 V
V
CC
CC
0
80
60
40
20
0
−50
−100
−150
−200
−20
−4
−2
0
2
4
6
−4
−2
0
2
4
6
8
V
OH
− Driver High-Level Output Voltage − V
V
OL
− Driver Low-Level Output Voltage − V
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
DRIVER DIFFERENTIAL OUTPUT
DRIVER OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
−40
−35
−30
−25
−20
−15
−10
T
= 25°C
A
VCC = 3.3 V
VTest = 12 V
DE at V
D at V
R
CC
CC
= 54 Ω
L
−5
0
0
0.50
1
1.50
2
2.50
3
3.50
-100
-50
0
50
100
150
200
250
V
CC
− Supply Voltage − V
TA – Free-Air Temperature – °C
Figure 17.
Figure 18.
ENABLE TIME
vs
COMMON-MODE VOLTAGE
(SEE Figure 20)
600
500
400
300
200
100
0
-7
-2
3
8
13
V
− Common-Mode Voltage − V
(TEST)
Figure 19.
18
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SN65HVD11-HT
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
TYPICAL CHARACTERISTICS (continued)
375 W ± 1%
Y
-7 V < V(TEST) < 12 V
D
60 W
± 1%
VOD
0 or 3 V
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0 V
tpZL(diff)
-1.5 V
VOD (low)
Figure 20. Driver Enable Time From DE to VOD
The time tpZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
www.ti.com
APPLICATION INFORMATION
256 Devices on Bus
Figure 21. Typical Application Circuit
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SLLS934D –NOVEMBER 2008–REVISED DECEMBER 2010
THERMAL CHARACTERISTICS OF IC PACKAGES
qJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
qJA is not a constant and is a strong function of:
•
•
•
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
qJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. qJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in qJA can be measured between these two test cards.
qJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
qJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with qJB in 1-dimensional thermal
simulation of a package system.
qJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. qJB is only defined for the high-k test card.
qJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 22.
Figure 22. Thermal Resistance
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN65HVD11HD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11SHKJ
SN65HVD11SHKQ
SN65HVD11SJD
ACTIVE
PREVIEW
ACTIVE
CFP
CFP
HKJ
HKQ
JDJ
8
8
8
0
1
25
1
TBD
TBD
TBD
TBD
Call TI
Call TI
N / A for Pkg Type
Call TI
CDIP SB
XCEPT
POST-PLATE N / A for Pkg Type
Call TI N / A for Pkg Type
SN65HVD11SKGDA
ACTIVE
KGD
130
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD11-HT :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2012
Catalog: SN65HVD11
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
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