SN65HVD235DR [TI]
3.3-V CAN TRANSCEIVERS; 3.3 -V CAN收发器![SN65HVD235DR](http://pdffile.icpdf.com/pdf1/p00114/img/icpdf/SN65HVD233_622494_icpdf.jpg)
型号: | SN65HVD235DR |
厂家: | ![]() |
描述: | 3.3-V CAN TRANSCEIVERS |
文件: | 总27页 (文件大小:346K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
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FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
D
Bus-Pin Fault Protection Exceeds 36 V
The SN65HVD233, SN65HVD234, and SN65HVD235
are used in applications employing the controller area
network (CAN) serial communication physical layer in
accordance with the ISO 11898 standard. As a CAN
transceiver, each provides transmit and receive capability
between the differential CAN bus and a CAN controller,
with signaling rates up to 1 Mbps.
Bus-Pin ESD Protection Exceeds 16-kV HBM
GIFT/ICT Compliant (SN65HVD234)
Compatible With ISO 11898
(1)
Signaling Rates up to 1 Mbps
Extended –7-V to 12-V Common-Mode Range
High-Input Impedance Allows for 120 Nodes
LVTTL I/Os Are 5-V Tolerant
Designed for operation in especially harsh environments,
the devices feature cross-wire, overvoltage and loss of
ground protection to 36 V, with overtemperature
protection and common-mode transient protection of
100 V. These devices operate over a –7-V to 12-V
common-mode range with a maximum of 60 nodes on a
Adjustable Driver Transition Times for
Improved Signal Quality
D
Unpowered Node Does Not Disturb the Bus
bus.
D
Low-Current Standby Mode . . . 200-µA
Typical
SN65HVD233
FUNCTIONAL BLOCK DIAGRAM
8
D
Low-Current Sleep Mode . . . 50-nA Typical
(SN65HVD234)
R
S
7
6
CANH
CANL
1
D
D
Thermal Shutdown Protection
D
Power-Up / Down Glitch-Free Bus Inputs and
Outputs
4
5
R
− High Input Impedance With Low V
CC
LBK
− Monolithic Output During Power Cycling
SN65HVD234
FUNCTIONAL BLOCK DIAGRAM
D
D
D
Loopback for Diagnostic Functions Available
(SN65HVD233)
8
R
S
D
7
6
Loopback for Autobaud Function Available
(SN65HVD235)
CANH
CANL
1
5
4
DeviceNet Vendor ID #806
EN
R
APPLICATIONS
SN65HVD235
FUNCTIONAL BLOCK DIAGRAM
D
CAN Data Bus
D
Industrial Automation
5
AB
−
−
DeviceNet Data Buses
Smart Distributed Systems (SDS)
8
R
S
7
6
CANH
CANL
1
D
D
D
D
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
4
R
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
(1)
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
DeviceNet is a trademark of Open DeviceNet Vendor Association.
Other trademarks are the property of their respective owners.
ꢒꢏ ꢓ ꢆꢔ ꢌ ꢎꢑ ꢓꢁ ꢆ ꢍꢎꢍ ꢕꢖ ꢗꢘ ꢙ ꢚꢛ ꢜꢕꢘꢖ ꢕꢝ ꢞꢟ ꢙ ꢙ ꢠꢖꢜ ꢛꢝ ꢘꢗ ꢡꢟꢢ ꢣꢕꢞ ꢛꢜꢕ ꢘꢖ ꢤꢛ ꢜꢠꢊ ꢒꢙ ꢘꢤꢟ ꢞꢜꢝ
ꢞ ꢘꢖ ꢗꢘꢙ ꢚ ꢜꢘ ꢝ ꢡꢠ ꢞ ꢕ ꢗꢕ ꢞ ꢛ ꢜꢕ ꢘꢖꢝ ꢡ ꢠꢙ ꢜꢥꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢎꢠꢦ ꢛꢝ ꢑꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ ꢝꢜ ꢛꢖꢤ ꢛꢙ ꢤ ꢧ ꢛꢙ ꢙ ꢛ ꢖꢜꢨꢊ
ꢒꢙ ꢘ ꢤꢟꢞ ꢜ ꢕꢘ ꢖ ꢡꢙ ꢘ ꢞ ꢠ ꢝ ꢝ ꢕꢖ ꢩ ꢤꢘ ꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢨ ꢕꢖꢞ ꢣꢟꢤ ꢠ ꢜꢠ ꢝꢜꢕ ꢖꢩ ꢘꢗ ꢛꢣ ꢣ ꢡꢛ ꢙ ꢛꢚ ꢠꢜꢠ ꢙ ꢝꢊ
Copyright 2002−2003, Texas Instruments Incorporated
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DESCRIPTION (Continued)
If the common-mode range is restricted to the ISO-11898 Standard range of –2 V to 7 V, up to 120 nodes may be connected
on a bus. These transceivers interface the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications.
The RS, pin 8 of the SN65HVD233, SN65HVD234, and SN65HVD235 provides for three modes of operation: high-speed,
slope control, or low-power standby mode. The high-speed mode of operation is selected by connecting pin 8 directly to
ground, allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise and fall
slope. The rise and fall slope can be adjusted by connecting a resistor to ground at pin 8, since the slope is proportional
to the pin’s output current. Slope control is implemented with a resistor value of 10 kΩ to achieve a slew rate of ≈15 V/us
and a value of 100 kΩ to achieve ≈ 2.0 V/µs slew rate. For more information about slope control, refer to the application
information section.
The SN65HVD233, SN65HVD234, and SN65HVD235 enter a low-current standby mode during which the driver is
switched off and the receiver remains active if a high logic level is applied to pin 8. The local protocol controller reverses
this low-current standby mode when it needs to transmit to the bus.
A logic high on the loopback LBK pin 5 of the SN65HVD233 places the bus output and bus input in a high-impedance state.
The remaining circuit remains active and available for driver to receiver loopback, self-diagnostic node functions without
disturbing the bus.
The SN65HVD234 enters an ultralow-current sleep mode in which both the driver and receiver circuits are deactivated if
a low logic level is applied to EN pin 5. The device remains in this sleep mode until the circuit is reactivated by applying
a high logic level to pin 5.
The AB pin 5 of the SN65HVD235 implements a bus listen-only loopback feature which allows the local node controller
to synchronize its baud rate with that of the CAN bus. In autobaud mode, the driver’s bus output is placed in a
high-impedance state while the receiver’s bus input remains active. For more information on the autobaud mode, refer to
the application information section.
2
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
SLOPE
CONTROL
DIAGNOSTIC
LOOPBACK
AUTOBAUD
LOOPBACK
PART NUMBER
LOW POWER MODE
SN65HVD233D
SN65HVD234D
SN65HVD235D
200-µA standby mode
200-µA standby mode or 50-nA sleep mode
200-µA standby mode
Adjustable
Adjustable
Adjustable
Yes
No
No
No
No
Yes
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
ORDERING INFORMATION
PACKAGE (D)
SN65HVD233D
MARKED AS
VP233
(1)
SN65HVD233DR
SN65HVD234D
VP234
VP235
(1)
SN65HVD234DR
SN65HVD235D
(1)
SN65HVD235DR
(1)
R suffix indicated tape and reel
POWER DISSIPATION RATINGS
(1)
DERATING FACTOR
CIRCUIT
T
A
≤ 25°C
T
A
= 85°C POWER
T = 125°C POWER
A
PACKAGE
BOARD
POWER RATING
ABOVE T = 25°C
RATING
255.7 mW
461.5 mW
RATING
A
D
D
Low-K
High-K
596.6 mW
5.7 mW/°C
28.4 mW
51.3 mW
1076.9 mW
10.3 mW/°C
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(1) (2)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
PARAMETER
VALUE
Supply voltage range, V
CC
−0.3 V to 7 V
−36 V to 36 V
−100 V to 100 V
−0.5 V to 7 V
−10 mA to 10 mA
16 kV
Voltage range at any bus terminal (CANH or CANL)
Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7)
Input voltage range, V (D, R, R , EN, LBK, AB)
I
S
Receiver output current, I
O
(3)
(3)
Electrostatic discharge
Human Body Model
CANH, CANL and GND
All pins
Human Body Model
3 kV
Electrostatic discharge
(4)
Charged-DeviceMode
All pins
1 kV
Continuous total power dissipation
Operating junction temperature, T
See Dissipation Rating Table
150°C
J
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114−A.
(2)
(3)
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101.
3
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
3
TYP
MAX
3.6
12
UNIT
Supply voltage, V
CC
Voltage at any bus terminal (separately or common mode)
−7
2
High−level input voltage, V
IH
D, EN, AB, LBK
D, EN, AB, LBK
5.5
0.8
6
V
Low−level input voltage, V
IL
0
Differential input voltage, V
ID
−6
0
Resistance from R to ground
100
5.5
kΩ
S
Input Voltage at R for standby, V
I(Rs)
0.75V
CC
V
S
Driver
Receiver
−50
−10
High−level output current, I
mA
mA
OH
Driver
50
10
Low−level output current, I
OL
Receiver
Operating junction temperature, T
(1)
HVD233, HVD234, HVD235
HVD233, HVD234, HVD235
150
125
°C
°C
J
Operating free−air temperature , T
−40
A
(1)
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
(1)
PARAMETER
TEST CONDITIONS
D at 0 V, R at 0 V, See Figures 1 and 2
MIN TYP
MAX
UNIT
CANH
CANL
CANH
CANL
2.45
V
CC
S
V
V
V
Bus output voltage (Dominant)
V
O(D)
0.5
1.25
2.3
2.3
2
Bus output voltage (Recessive)
Differential output voltage (Dominant)
Differential output voltage (Recessive)
D at 3 V, R at 0 V, See Figures 1 and 2
V
V
O
S
D at 0 V, R at 0 V, See Figures 1 and 2
1.5
1.2
3
3
S
OD(D)
D at 0 V, R at 0 V, See Figures 2 and 3
2
S
D at 3 V, R at 0 V, See Figures 1 and 2
−120
−0.5
12
mV
V
S
V
V
OD
D at 3 V, R at 0 V, No Load
S
0.05
Peak-to-peak common-mode output voltage
High-level input current; D, EN, LBK, AB
Low-level input current; D, EN, LBK, AB
See Figure 10
D at 2 V
1
V
OC(pp)
I
I
−30
−30
30
30
µA
µA
IH
D at 0.8 V
IL
V
V
V
V
= −7 V, CANL Open, See Figure 15
= 12 V, CANL Open, See Figure 15
= −7 V, CANH Open, See Figure 15
= 12 V, CANH Open, See Figure 15
−250
CANH
CANH
CANL
CANL
1
I
Short−circuit output current
Output capacitance
mA
OS
−1
250
C
See receiver input capacitance
at 0.75 V
O
I
R
S
input current for standby
R
−10
µA
µA
IRs(s)
S
CC
Sleep
EN at 0 V, D at V , R at 0 V or V
0.05
200
2
CC CC
S
R
at V , D at V , AB at 0 V, LBK at 0 V,
S
CC
CC
CC
Standby
600
EN at V
I
Supply current
D at 0 V, No Load, AB at 0 V, LBK at 0 V,
at 0 V, EN at V
CC
Dominant
Recessive
6
6
R
S
CC
mA
D at V , No Load, AB at 0 V,
CC
LBK at 0 V, R at 0 V, EN at V
S
CC
(1)
All typical values are at 25°C and with a 3.3 V supply.
4
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
(1)
MIN TYP
TEST CONDITIONS
at 0 V, See Figure 4
MAX
85
UNIT
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
35
70
with 10 kΩ to ground, See Figure 4
with 100 kΩ to ground, See Figure 4
at 0 V, See Figure 4
125
870
120
180
1200
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
ns
PLH
PHL
sk(p)
500
70
with 10 kΩ to ground, See Figure 4
with 100 kΩ to ground, See Figure 4
at 0 V, See Figure 4
130
870
35
ns
ns
with 10 kΩ to ground, See Figure 4
with 100 kΩ to ground, See Figure 4
60
Pulse skew (|t |)
– t
PHL PLH
370
t
t
t
t
t
t
t
t
Differential output signal rise time
Differential output signal fall time
Differential output signal rise time
Differential output signal fall time
Differential output signal rise time
Differential output signal fall time
Enable time from standby to dominant
Enable time from sleep to dominant
20
20
70
70
r
R
R
R
at 0 V, See Figure 4
ns
ns
ns
µs
S
S
S
f
30
135
135
1400
1400
1.5
r
with 10 kΩ to ground, See Figure 4
with 100 kΩ to ground, See Figure 4
30
f
350
350
r
f
0.6
1
en(s)
en(z)
See Figures 8 and 9
5
(1)
All typical values are at 25°C and with a 3.3 V supply.
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
(1)
MIN TYP
TEST CONDITIONS
MAX
UNIT
V
IT+
V
IT−
V
hys
V
OH
V
OL
Positive-going input threshold voltage
Negative-going input threshold voltage
750
900
500
2.4
650
100
AB at 0 V, LBK at 0 V, EN at V , See Table 1
CC
mV
Hysteresis voltage (VIT+ −V
High-level output voltage
Low-level output voltage
)
IT−
I
= −4 mA, See Figure 6
= 4 mA, See Figure 6
O
V
I
0.4
O
CANH or CANL at 12 V
150
200
500
CANH or CANL at 12 V,
Other bus pin at 0 V,
D at 3 V, AB at 0 V,
600
−150
−130
V
CC
at 0 V
I
I
Bus input current
µA
LBK at 0 V, R at 0 V,
CANH or CANL at −7 V
−610
−450
S
EN at V
CC
CANH or CANL at −7 V,
V
CC
at 0 V
Pin-to-ground, V = 0.4 sin (4E6πt) + 0.5V,
I
C
C
Input capacitance (CANH or CANL)
Differential input capacitance
40
20
I
D at 3 V, AB at 0 V, LBK at 0 V, EN at V
CC
pF
Pin-to-pin, V = 0.4 sin (4E6πt) + 0.5V,
I
ID
D at 3 V, AB at 0 V, LBK at 0 V, EN at V
CC
CC
R
R
Differential input resistance
Input resistance (CANH or CANL)
Sleep
40
20
100
50
2
ID
D at 3 V, AB at 0 V, LBK at 0 V, EN at V
kΩ
µA
IN
EN at 0 V, D at V , Rs at 0 V or V
CC CC
0.05
200
R
at V , D at V , AB at 0 V, LBK at 0 V,
S
CC
CC
CC
Standby
600
6
EN at V
I
Supply current
Dominant
D at 0 V, No Load, R at 0 V, LBK at 0 V,
AB at 0 V, EN at V
CC
CC
S
mA
D at V , No Load, R at 0 V, LBK at 0 V,
CC
S
Recessive
6
AB at 0 V, EN at V
CC
(1)
All typical values are at 25°C and with a 3.3 V supply.
5
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
MAX
60
UNIT
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
35
35
7
PLH
PHL
sk(p)
r
60
Pulse skew (|t |)
− t
See Figure 6
ns
PHL PLH
Output signal rise time
Output signal fall time
2
5
5
2
f
(1)
All typical values are at 25°C and with a 3.3 V supply.
DEVICE SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
HVD233 See Figure 12
MAX
12
UNIT
ns
t
t
t
Loopback delay, driver input to receiver output
Loopback delay, driver input to receiver output
Loopback delay, bus input to receiver output
7.5
10
35
70
(LBK)
(AB1)
(AB2)
See Figure 13
See Figure 14
20
ns
HVD235
60
ns
R
R
at 0 V, See Figure 11
135
S
with 10 kΩ to ground,
S
105
190
Total loop delay, driver input to receiver output, recessive to
dominant
See Figure 11
t
ns
ns
(loop1)
R
with 100 kΩ to ground,
S
535
70
1000
135
See Figure 11
R
R
at 0 V, See Figure 11
S
with 10 kΩ to ground,
S
105
190
Total loop delay, driver input to receiver output, dominant to
recessive
See Figure 11
t
(loop2)
R
with 100 kΩ to ground,
S
535
1000
See Figure 11
(1)
All typical values are at 25°C and with a 3.3 V supply.
6
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
I
O(CANH)
D
R
I
I
60 Ω 1%
V
OD
V
O(CANH)
V
+ V
2
O(CANH)
O(CANL)
I
IRs
S
V
I
V
OC
I
+
O(CANL)
V
V
I(Rs)
−
O(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
Dominant
≈ 3 V
V
O(CANH)
Recessive
≈ 2.3 V
≈ 1 V
V
O(CANL)
Figure 2. Bus Logic State Voltage Definitions
330 Ω 1%
CANH
D
V
OD
V
I
60 Ω 1%
+
−7 V ≤ V
TEST
≤ 12 V
R
S
_
CANL
330 Ω 1%
Figure 3. Driver V
OD
CANH
CANL
V
CC
V
/2
CC
V /2
CC
C
= 50 pF 20%
(see Note B)
L
V
I
0 V
V
D
V
O
t
t
PHL
PLH
R
= 60 Ω 1%
L
V
I
R
S
O(D)
+
90%
10%
0.9 V
V
O
V
0.5 V
I(Rs)
(see Note A)
V
O(R)
−
t
r
t
f
NOTES:A. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle,
t ≤ 6ns, t ≤ 6ns, Z = 50Ω.
L
r
C
f
O
B.
includes fixture and instrumentation capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
7
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
CANH
R
I
O
V
V
I(CANH)
ID
V
+ V
2
I(CANH
I(CANL)
V
IC
=
V
O
CANL
V
I(CANL)
Figure 5. Receiver Voltage and Current Definitions
2.9 V
1.5 V
CANH
CANL
2.2 V
2.2 V
V
I
R
I
O
V
I
t
t
PLH
PHL
C
L
= 50 pF 20%
(see Note D)
1.5 V
V
V
V
O
OH
(see Note C)
90% 90%
50%
10%
50%
10%
V
O
OL
t
r
t
f
NOTES:C. The input pulse is supplied by a generator having the following characteristics: Pulse repetition rate (PRR) ≤ 125 kHz, 50% duty cycle,
t ≤ 6ns, t ≤ 6ns, Z = 50Ω.
L
r
C
f
O
D.
includes fixture and instrumentation capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
Table 1. Differential Input Voltage Threshold Test
INPUT
OUTPUT
R
MEASURED
|V
V
V
|
ID
CANH
CANL
−6.1 V
12 V
−1 V
12 V
−6.5 V
12 V
−7 V
6 V
−7 V
L
L
L
L
900 mV
900 mV
6 V
11.1 V
−7 V
6 V
V
OL
6 V
−7 V
11.5 V
−1 V
12 V
open
H
H
H
H
H
500 mV
500 mV
6 V
6 V
X
V
OH
open
CANH
R
CANL
100 Ω
Pulse Generator
15 µs Duration
1% Duty Cycle
D at 0 V or V
CC
Rs, AB, EN, LBK, at 0 V or V
CC
t , t ≤ 100 ns
r
f
:
NOTE This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 7. Test Circuit, Transient Over Voltage Test
8
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
HVD234
HVD233 or HVD235
R
R
S
S
CANH
CANH
60 Ω 1%
V
V
I
I
D
D
60 Ω 1%
0 V
0 V
CC
AB or LBK
EN
V
CANL
CANL
R
V
O
V
O
+
−
+
−
15 pF 20%
15 pF 20%
V
CC
50%
V
I
0 V
V
V
OH
50%
V
O
OL
t
en(s)
:
NOTE All V input pulses are supplied by a generator having the following characteristics: t or t ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50%
I
r
f
duty cycle.
Figure 8. t
Test Circuit and Voltage Waveforms
en(s)
HVD234
R
S
V
CC
CANH
60 Ω 1%
50%
V
I
D
0 V
0 V
V
EN
V
I
OH
CANL
50%
V
O
R
V
OL
t
V
O
en(z)
+
15 pF 20%
−
:
NOTE All V input pulses are supplied by a generator having the following characteristics:
I
t or t ≤ 6 ns, pulse repetition rate (PRR) = 50 kHz, 50% duty cycle.
r
f
Figure 9. t
Test Circuit and Voltage Waveforms
en(z)
27 Ω 1%
CANH
CANL
V
OC(PP)
D
V
OC
V
I
R
S
V
OC
27 Ω 1%
50 pF 20%
:
NOTE All V input pulses are supplied by a generator having the following characteristics:
I
t or t ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
r
f
Figure 10. V
Test Circuit and Voltage Waveforms
OC(pp)
9
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
0Ω, 10 kΩ,
DUT
or 100 kΩ 5%
R
S
CANH
60 Ω 1%
V
CC
50%
50%
D
V
I
V
I
0 V
LBK or AB
HVD233/235
EN
t
t
(loop2)
(loop1)
CANL
V
V
OH
V
50%
50%
V
O
CC
HVD234
R
OL
+
−
V
O
15 pF 20%
:
NOTE All V input pulses are supplied by a generator having the following characteristics:
I
t or t ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
r
f
Figure 11. t
Test Circuit and Voltage Waveforms
(loop)
HVD233
V
R
CC
S
CANH
50%
50%
V
I
+
D
0 V
V
I
V
OD
−
60 Ω 1%
t
t
(LBK1)
(LBK2)
V
LBK
R
OH
OL
V
CC
CANL
50%
50%
V
O
V
t
=t
=t
(LBK) (LBK1) (LBK2)
V
≈ 2.3 V
OD
+
−
V
O
15 pF 20%
:
NOTE All V input pulses are supplied by a generator having the following characteristics:
I
t or t ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
r
f
Figure 12. t
Test Circuit and Voltage Waveforms
(LBK)
HVD235
V
≈ 2.3 V
OD
R
S
CANH
V
CC
+
V
−
D
50%
50%
60 Ω 1%
V
I
V
I
OD
0 V
CANL
t
t
(ABH)
(ABL)
AB
R
V
V
OH
V
CC
50%
50%
V
O
OL
t
= t
= t
(AB1) (ABH) (ABL)
+
−
V
O
15 pF 20%
:
NOTE All V input pulses are supplied by a generator having the following characteristics: t
I
r
or t ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
f
Figure 13. t
Test Circuit and Voltage Waveforms
(AB1)
10
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
HVD235
R
S
CANH
2.9 V
2.2 V
2.2 V
V
I
D
V
CC
60 Ω 1%
V
I
1.5 V
t
t
1.5 V
(ABH)
(ABL)
CANL
AB
R
V
OH
OL
V
CC
50%
50%
V
O
V
t
= t
= t
(AB2) (ABH) (ABL)
+
−
V
O
15 pF 20%
:
NOTE All V input pulses are supplied by a generator having the following characteristics:
I
t or t ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
r
f
Figure 14. t
Test Circuit and Voltage Waveforms
(AB2)
I
OS
I
OS
15 s
CANH
D
0 V
0 V or V
+
_
CC
I
OS
V
I
12 V
CANL
V
I
0 V
0 V
and
10 µs
V
I
−7 V
Figure 15. I
Test Circuit and Waveforms
OS
3.3 V
T
V
= 25°C
A
= 3.3 V
CC
R2 1%
R1 1%
CANH
CANL
+
ID
−
R
V
V
ac
R1 1%
V
I
R2 1%
The R Output State Does Not Change During
Application of the Input Waveform.
V
ID
R1
R2
500 mV
50 Ω
50 Ω
280 Ω
130 Ω
900 mV
12 V
−7 V
V
I
:
NOTE All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 16. Common-Mode Voltage Rejection
11
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DEVICE INFORMATION
SN65HVD233D
(Marked as VP233)
(TOP VIEW)
SN65HVD234D
(Marked as VP234)
(TOP VIEW)
SN65HVD235D
(Marked as VP235)
(TOP VIEW)
D
R
D
R
D
R
S
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
S
S
GND
CANH
CANL
LBK
GND
CANH
CANL
EN
GND
CANH
CANL
AB
V
V
V
CC
R
CC
R
CC
R
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D INPUT
R
S
INPUT
V
CANH INPUT
V
CC
CC
V
CC
110 kΩ
45 kΩ
9 kΩ
100 kΩ
1 kΩ
INPUT
INPUT
40 V
9 V
9 kΩ
+
_
INPUT
CANL INPUT
CANH and CANL OUTPUTS
CC
R OUTPUT
V
V
CC
V
CC
110 kΩ
45 kΩ
9 kΩ
5 Ω
OUTPUT
9 V
INPUT
40 V
OUTPUT
9 kΩ
40 V
EN INPUT
LBK or AB INPUT
V
CC
V
CC
1 kΩ
1 kΩ
INPUT
INPUT
100 kΩ
100 kΩ
9 V
9 V
12
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
Table 2. Thermal Characteristics
PARAMETERS
TEST CONDITIONS
VALUE
185
UNIT
(2)
Low-K board, no air flow
(1)
Junction-to-ambient thermal resistance
Θ
Θ
°C/W
JA
(3)
High-K board, no air flow
101
(3
Junction-to-board thermal resistance
Junction-to-case thermal resistance
High-K ) board, no air flow
82.8
26.5
°C/W
°C/W
JB
JC
Θ
R
L
= 60 Ω, R at 0 V, input to D a 1-MHz 50%
S
P
Average power dissipation
duty cycle square wave
at 3.3 V, T = 25°C
36.4
170
mW
(AVG)
V
CC
A
T
Thermal shutdown junction temperature
°C
(SD)
(1)
(2)
(3)
See TI literature number SZZA003 for an explanation of this parameter.
JESD51−3 low effective thermal conductivity test board for leaded surface mount packages.
JESD51−7 high effective thermal conductivity test board for leaded surface mount packages.
FUNCTION TABLES
DRIVER (SN65HVD233 OR SN65HVD235)
INPUTS
OUTPUTS
CANL
D
X
L
LBK/AB
R
S
CANH
BUS STATE
Recessive
Dominant
X
> 0.75 V
Z
H
Z
Z
Z
L
Z
Z
CC
L or open
≤ 0.33 V
≤ 0.33 V
CC
H or open
X
H
Recessive
Recessive
X
CC
RECEIVER (SN65HVD233)
INPUTS
OUTPUT
BUS STATE
V
ID
= V
−V
≥ 0.9 V
LBK
D
R
L
(CANH) (CANL)
Dominant
V
L or open
L or open
L or open
X
ID
≤ 0.5 V or open
Recessive
V
H or open
H
?
ID
?
X
X
0.5 V < V < 0.9 V
ID
H or open
X
X
L
L
H
H
H
RECEIVER (SN65HVD235)
INPUTS
OUTPUT
BUS STATE
Dominant
Recessive
?
V
ID
= V
−V
≥ 0.9 V
AB
D
R
L
(CANH) (CANL)
V
L or open
X
ID
≤ 0.5 V or open
V
L or open
H or open
H
?
ID
0.5 V < V < 0.9 V
L or open
H or open
ID
≥ 0.9 V
Dominant
Recessive
Recessive
?
V
H
H
H
H
X
H
L
L
ID
V
V
≤ 0.5 V or open
≤ 0.5 V or open
H
L
ID
ID
0.5 V < V < 0.9 V
ID
L
L
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DRIVER (SN65HVD234)
INPUTS
OUTPUTS
D
L
EN
R
CANH
CANL
Bus State
Dominant
Recessive
Recessive
Recessive
Recessive
S
H
≤ 0.33 V
≤ 0.33 V
X
H
Z
Z
Z
Z
L
Z
Z
Z
Z
CC
H
X
CC
Open
X
X
X
> 0.75 V
CC
X
L or open
X
RECEIVER (SN65HVD234)
INPUTS
OUTPUT
Bus State
Dominant
Recessive
?
V
ID
= V
−V
≥ 0.9 V
EN
R
L
(CANH) (CANL)
V
H
ID
≤ 0.5 V or open
V
ID
H
H
H
?
0.5 V < V < 0.9 V
ID
X
X
L or open
H
H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
14
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
TYPICAL CHARACTERISTICS
RECESSIVE-TO-DOMINANT LOOP TIME
DOMINANT-TO-RECESSIVE LOOP TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
95
90
85
80
75
90
Rs, LBK, AB = 0 V
EN = V
Rs, LBK, AB = 0 V
EN = V
CC
CC
85
80
V
= 3 V
CC
V
CC
= 3.6 V
V
CC
= 3.3 V
V
CC
= 3.6 V
75
70
65
V
CC
= 3.3 V
70
65
V
CC
= 3 V
60
−40
5
45
80
125
−40
5
45
80
125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 17
Figure 18
SUPPLY CURRENT
vs
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
FREQUENCY
LOW-LEVEL OUTPUT VOLTAGE
20
160
140
120
100
V
= 3.3 V,
V
= 3.3 V,
CC
Rs, LBK, AB = 0 V,
EN = V
CC
Rs, LBK, AB = 0 V,
EN = V
,
,
CC
= 25°C
CC
= 25°C
19
18
T
A
T
A
80
60
40
20
0
17
16
15
1000
200
300
500
700
0
1
2
3
4
f − Frequency − kbps
V
OL
− Low-Level Output Voltage − V
Figure 19
Figure 20
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DIFFERENTIAL OUTPUT VOLTAGE
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT VOLTAGE
2.2
2
0.12
0.1
V
= 3.3 V,
CC
Rs, LBK, AB = 0 V,
EN = V
V
= 3.6 V
= 3.3 V
CC
,
CC
T
A
= 25°C
V
CC
1.8
1.6
1.4
0.08
V
= 3 V
CC
0.06
0.04
0.02
0
R
L
= 60 Ω
Rs, LBK, AB = 0 V
EN = V
1.2
1
CC
0
0.5
V
1
1.5
2
2.5
3
3.5
−40
5
45
80
125
− High-Level Output Voltage − V
OH
T
A
− Free-Air Temperature − °C
Figure 21
Figure 22
RECEIVER LOW-TO-HIGH PROPAGATION DELAY
RECEIVER HIGH-TO-LOW PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
38
45
Rs, LBK, AB = 0 V
Rs, LBK, AB = 0 V
44
43
42
41
EN = V
CC
EN = V
CC
See Figure 6
See Figure 6
37
36
35
34
V
CC
= 3.3 V
V
CC
= 3 V
40
39
V
CC
= 3 V
V
CC
= 3.3 V
38
37
V
= 3.6 V
CC
33
32
V
CC
= 3.6 V
5
36
35
−40
−40
45
80
5
45
80
125
125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 23
Figure 24
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
DRIVER LOW-TO-HIGH PROPAGATION DELAY
DRIVER HIGH-TO-LOW PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
55
50
45
40
35
65
Rs, LBK, AB = 0 V
EN = V
CC
See Figure 4
60
55
V
= 3 V
CC
V
CC
= 3.3 V
V
CC
= 3 V
50
V
= 3.3 V
CC
45
40
V
= 3.6 V
CC
V
CC
= 3.6 V
Rs, LBK, AB = 0 V
EN = V
See Figure 4
30
25
35
30
CC
−40
5
45 80
−40
125
5
45
80
125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 25
Figure 26
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
35
30
25
20
15
10
Rs, LBK, AB = 0 V,
EN = V
,
CC
T
= 25°C
= 60 Ω
A
R
L
5
0
−5
0
0.6
1.2
1.8
2.4
3
3.6
V
− Supply Voltage − V
CC
Figure 27
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SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
APPLICATION INFORMATION
Diagnostic Loopback (SN65HVD233)
The loopback (LBK) function of the HVD233 is enabled with a high-level input to pin 5. This forces the driver into a
recessive state and redirects the data (D) input at pin 1 to the received-data output (R) at pin 4. This allows the host
controller to input and read back a bit sequence to perform diagnostic routines without disturbing the CAN bus. A
typical CAN bus application is displayed in Figure 28.
If the LBK pin is not used it may be tied to ground (GND). However, it is pulled low internally (defaults to a low−level
input) and may be left open if not in use.
Autobaud Loopback (SN65HVD235)
The autobaud feature of the HVD235 is implemented by placing a logic high on pin 5 (AB). In autobaud, the
bus-transmit function of the transceiver is disabled, while the bus-receive function and all of the normal operating
functions of the device remain intact. With the autobaud function engaged, normal bus activity can be monitored by
the device. However, if an error frame is generated by the local CAN controller, it is not transmitted to the bus. Only
the host microprocessor can detect the error frame.
Autobaud detection is best suited to applications that have a known selection of baud rates. For example, a popular
industrial application has optional settings of 125 kbps, 250 kbps, or 500 kbps. Once the logic high has been applied
to pin 5 (AB) of the HVD235, assume a baud rate such as 125 kbps, then wait for a message to be transmitted by
another node on the bus. If the wrong baud rate has been selected, an error message is generated by the host CAN
controller. However, since the bus-transmit function of the device has been disabled, no other nodes receive the error
message of the controller.
This procedure makes use of the CAN controller’s status register indications of message received and error warning
status to signal if the current baud rate is correct or not. The warning status indicates that the CAN chip error counters
have been incremented. A message received status indicates that a good message has been received.
If an error is generated, reset the CAN controller with another baud rate, and wait to receive another message. When
an error-free message has been received, the correct baud rate has been detected. A logic low may now be applied
to pin 5 (AB) of the HVD235, returning the bus-transmit normal operating function to the transceiver.
Bus Lines −− 40 m max
CANH
Ω
Ω
Stub Lines −− 0.3 m max
120
120
CANL
5 V
3.3 V
Vcc
3.3 V
Vref
Rs
Vcc
Rs
Vref
Rs
Vcc
µ
0.1
SN65HVD251
0.1
µ
F
SN65HVD233
0.1
F
SN65HVD230
µ
F
GND
GND
GND
D
R
D
R
D
R
LBK
CANTX
CANRX
CANTX
CANRX
CANTX
CANRX
GPIO
TMS320LF243
TMS320F2812
TMS320LF2407A
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Sensor, Actuator, or Control
Equipment
Figure 28. Typical HVD233 Application
Interoperability With 5-V CAN Systems
ISO−11898 specifies the interface characteristics to a CAN bus with the purpose of insuring interchangeability among
compatible transceivers. While the levels specified in the standard assume a 5-V supply, there is nothing in the
standard that makes this a requirement. The SN65HVD233 is compatible with these requirements with a 3.3-V
supply, assuring interoperability with 5-V supplied transceivers.
Bus Cable
The ISO 11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a maximum
of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes
to a bus. A large number of nodes requires a transceiver with high input impedance such as the HVD233.
18
ꢀ
ꢀ
ꢀ
ꢁ
ꢁ
ꢁ
ꢂ
ꢂ
ꢂ
ꢃ
ꢃ
ꢃ
ꢄꢅ
ꢄꢅ
ꢄꢅ
ꢆꢇ
ꢆꢇ
ꢆꢇ
ꢈ
ꢈ
ꢈ
ꢈ
ꢉ
ꢃ
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
The standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept
as short as possible to minimize signal reflections.
Slope Control
The rise and fall slope of the SN65HVD233, SN65HVD234, and SN65HVD235 driver output can be adjusted by
connecting a resistor from the Rs (pin 8) to ground (GND), or to a low-level input voltage as shown in Figure 29.
The slope of the driver output signal is proportional to the pin’s output current. This slope control is implemented with
an external resistor value of 10 kΩ to achieve a ≈ 15 V/µs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/µs slew
rate as displayed in Figure 30. Typical driver output waveforms with slope control are displayed in Figure 31.
10 kΩ
to
100 kΩ
IOPF6
Rs
1
2
3
4
8
7
6
5
D
GND
Vcc
TMS320LF2407
CANH
CANL
LBK
R
Figure 29. Slope Control/Standby Connection to a DSP
25
20
15
10
5
0
0
4.7 6.8 10 15 22 33 47 68 100
Slope Control Resistance − kΩ
Figure 30. HVD233 Driver Output Signal Slope vs Slope Control Resistance Value
19
ꢀ
ꢀ
ꢀ
ꢁꢂ
ꢁꢂ
ꢁꢂ
ꢃ
ꢃ
ꢃ
ꢄꢅ
ꢄꢅ
ꢄꢅ
ꢆꢇ
ꢆꢇ
ꢆꢇ
ꢈ
ꢈ
ꢈ
ꢈ
ꢉ
ꢃ
www.ti.com
SLLS557D − NOVEMBER 2002 REVISED JUNE 2005
Ω
Rs = 0
Ω
Rs = 10 k
Ω
Rs = 100 k
Figure 31. Typical SN65HVD233 250-kbps Output Pulse Waveforms With Slope Control
Standby
If a high−level input (> 0.75 VCC) is applied to Rs (pin 8), the circuit enters a low-current, listen only standby mode
during which the driver is switched off and the receiver remains active. The local controller can reverse this low-power
standby mode when the rising edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
20
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN65HVD233D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD233DG4
SN65HVD233DR
SN65HVD233DRG4
SN65HVD234D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD234DG4
SN65HVD234DR
SN65HVD234DRG4
SN65HVD235D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD235DG4
SN65HVD235DR
SN65HVD235DRG4
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
FMX
FMX
FMX
Reel
Diameter Width
(mm)
Reel
A0 (mm)
6.4
B0 (mm)
5.2
K0 (mm)
2.1
P1
W
Pin1
(mm) (mm) Quadrant
(mm)
SN65HVD233DR
SN65HVD234DR
SN65HVD235DR
D
D
D
8
8
8
330
0
8
8
8
12 PKGORN
T1TR-MS
P
330
330
0
0
6.4
5.2
2.1
12 PKGORN
T1TR-MS
P
6.4
5.2
2.1
12 PKGORN
T1TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65HVD233DR
SN65HVD234DR
SN65HVD235DR
D
D
D
8
8
8
FMX
FMX
FMX
342.9
342.9
342.9
336.6
336.6
336.6
20.6
20.6
20.6
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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