SN65HVD33 [TI]
3.3V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS; 3.3V全双工RS - 485驱动器和接收
| 型号： | SN65HVD33 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS |
| 文件： | 总21页 (文件大小：1438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
3.3V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
Each driver and receiver has separate input and
output pins for full-duplex bus communication
designs. They are designed for balanced
transmission lines and interoperation with ANSI
TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11 and ISO
8482:1993 standard-compliant devices.
FEATURES
•
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
•
•
Bus-Pin ESD Protection Exceeds 15 kV HBM
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 5 Mbps and 25
Mbps
The SN65HVD30, SN65HVD31, SN65HVD32,
SN65HVD36 and SN65HVD37 are fully enabled with
no external enabling pins. The SN65HVD36 and
•
•
Low-Current Standby Mode: < 1 µA
SN65HVD37
implement
receiver
equalization
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
technology for improved performance in long distance
applications.
•
•
•
5V Tolerant Inputs
The SN65HVD33, SN65HVD34, SN65HVD35,
SN65HVD38, and SN65HVD39 have active-high
driver enables and active-low receiver enables. A
very low, less than 1 µA, standby current can be
achieved by disabling both the driver and receiver.
The SN65HVD38 and SN65HVD39 implement
receiver equalization technology for improved
performance in long distance applications.
Bus Idle, Open, and Short Circuit Failsafe
Meets or exceeds the requirements of ANSI
TIA/EIA-485-A and RS-422 Compatible
•
5-V Devices available, SN65HVD50-59
APPLICATIONS
•
•
•
•
Utility Meters
DTE/DCE Interfaces
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
All devices are characterized for operation from -40°C
to +85°C.
The SN65HVD36 and SN65HVD38 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates up to 20 Mbps at cable lengths up to 160
meters.
DESCRIPTION
The SN65HVD3X devices are 3-state differential line
drivers and differential-input line receivers that
operate with 3.3-V power supply.
The SN65HVD37 and SN65HVD39 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates in the range of 1 to 5 Mbps at cable lengths up
to 1000 meters.
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
IMPROVED REPLACEMENT FOR:
Part Number
Replace with
xxx3491
SN65HVD33:
Better ESD protection (15kV vs 2kV or not specified) Higher Signaling
Rate (25Mbps vs 20Mbps) Fractional Unit Load (64 Nodes vs 32)
MAX3491E
MAX3076E
MAX3073E
MAX3070E
SN65HVD33:
SN65HVD33:
SN65HVD34:
SN65HVD35:
Higher Signaling Rate (25Mbps vs 12Mbps) Fractional Unit Load
(64 Nodes vs 32)
Higher Signaling Rate (25Mbps vs 16Mbps) Lower Standby Current
(1 µA vs 10 µA)
Higher Signaling Rate (5Mbps vs 500kbps) Lower Standby Current
(1 µA vs 10 µA)
Higher Signaling Rate (1Mbps vs 250kbps) Lower Standby Current
(1 µA vs 10 µA)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2005, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36,
SN65HVD37
SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38,
SN65HVD39
D PACKAGE (TOP VIEW)
NC
R
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CC
V
1
2
3
4
8
7
6
5
A
B
Z
Y
CC
R
RE
D
DE
GND
D
GND
GND
8
8
NC
2
A
R
7
NC - No internal connection
B
5
3
Y
D
6
Z
AVAILABLE OPTIONS
SIGNALING
RATE
RECEIVER
EQUALIZATION
BASE
PART NUMBER
UNIT LOADS
ENABLES
SOIC MARKING
25 Mbps
5 Mbps
1 Mbps
25 Mbps
5 Mbps
1 Mbps
25 Mbps
5 Mbps
25 Mbps
5 Mbps
1/2
1/8
1/8
1/2
1/8
1/8
1/2
1/8
1/2
1/8
No
No
No
No
SN65HVD30
SN65HVD31
SN65HVD32
SN65HVD33
SN65HVD34
SN65HVD35
SN65HVD36
SN65HVD37
SN65HVD38
SN65HVD39
PREVIEW
PREVIEW
PREVIEW
65HVD33
65HVD34
65HVD35
PREVIEW
PREVIEW
PREVIEW
PREVIEW
No
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Yes
2
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)(2)
UNIT
VCC
Supply voltage range, VCC
–0.3 V to 6 V
–9 V to 14 V
–50 to 50 V
-0.5 V to 7 V
Internally limited
11 mA
Voltage range at any bus terminal (A, B, Y, Z)
Voltage input, transient pulse through 100 Ω. See Figure 12 (A, B, Y, Z)(3)
Input voltage range (D, DE, RE)
VI
IO
Continuous total power dissipation
Output current (receiver output only, R)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) This tests survivability only and the output state of the receiver is not specified.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted
PARAMETER
MIN NOM
3.0
–7(1)
MAX UNIT
VCC
Supply voltage
Voltage at any bus terminal (separately or common mode)
3.6
V
VI or
VIC
12
1/tUI
SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38
25
5
Signaling rate
SN65HVD31, SN65HVD34, SN65HVD37, SN65HVD39
SN65HVD32, SN65HVD35
Mbps
Ω
1
RL
Differential load resistance
High-level input voltage
Low-level input voltage
Differential input voltage
54
2
60
VIH
VIL
VID
D, DE, RE
D, DE, RE
VCC
0.8
12
0
V
–12
–60
–8
Driver
IOH
High-level output current
mA
Receiver
Driver
60
8
IOL
TA
Low-level output current
mA
Receiver
Ambient still-air temperature
–40
85
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
TEST CONDITIONS
Bus terminals and GND
All pins
MIN
TYP(1)
±16
±4
MAX
UNIT
Human body model
Human body model(2)
kV
Charged-device-model(3)
All pins
±1
(1) All typical values at 25°C with 3.3-V supply.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
3
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
–1.5
2.5
TYP(1)
MAX UNIT
VI(K)
Input clamp voltage
II = –18 mA
IO = 0
VCC
RL = 54 Ω, See Figure 1
(RS-485)
RL = 100 Ω, See Figure 1(2)
(RS-422)
1.5
2.0
2.0
2.3
|VOD(SS)
|
Steady-state differential output voltage
Change in magnitude of steady-state
Vtest = –7 V to 12 V,
See Figure 2
1.5
RL = 54 Ω, See Figure 1
∆|VOD(SS)
|
–0.2
0.2
differential output voltage between states and Figure 2
Differential Output Voltage overshoot
and undershoot
RL = 54 Ω, CL = 50 pF,
See Figure 5 and Figure 3
V
VOD(RING)
0.05 |VOD(SS)
|
Peak-to-peak
HVD30, HVD33,
common-mode
HVD36, HVD38
output voltage
VOC(PP)
0.5
See Figure 4
HVD31, HVD34,
HVD37, HVD39,
HVD32, HVD35
0.25
Steady-state common-mode
output voltage
VOC(SS)
1.6
2.3
0.05
90
See Figure 4
Change in steady-state common-mode
output voltage
∆VOC(SS)
–0.05
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
–10
High-impedance state
output current
HVD33, HVD34,
HVD35, HVD38,
HVD39
VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = 12 V
IZ(Z) or IY(Z)
µA
90
Other input
at 0 V
VCC = 5 V or 0 V,
DE = 0 V
–10
VZ or VY = –7 V
VZ or VY = –7 V
VZ or VY = 12 V
–250
–250
0
250
250
100
Other input
at 0 V
IZ(S) or IY(S) Short Circuit output Current
mA
II
Input current
D, DE
µA
pF
Differential output
capacitance
VOD = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
C(OD)
16
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) VCC is 3.3 Vdc ± 5%
4
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
HVD30, HVD33, HVD36, HVD38
Propagation delay time,
low-to-high-level output
4
25
10
38
175
9
18
65
tPLH
tPHL
tr
HVD31, HVD34, HVD37, HVD39
HVD32, HVD35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
4
305
18
HVD30, HVD33, HVD36, HVD38
HVD31, HVD34, HVD37, HVD39
HVD32, HVD35
Propagation delay time,
high-to-low-level output
25
38
175
5
65
120
2.5
20
305
12
HVD30, HVD33, HVD36, HVD38
HVD31, HVD34, HVD37, HVD39
HVD32, HVD35
Differential output signal
rise time
RL = 54 Ω, CL = 50 pF,
See Figure 5
37
185
5
60
120
2.5
20
300
12
HVD30, HVD33, HVD36, HVD38
HVD31, HVD34, HVD37, HVD39
HVD32, HVD35
Differential output signal fall
time
tf
35
180
60
120
300
2
HVD30, HVD33, HVD36, HVD38
HVD31, HVD34, HVD37, HVD39
HVD32, HVD35
tsk(p)
tPZH1
tPHZ
tPZL1
tPLZ
tPZH2
tPZL2
Pulse skew (|tPHL - tPLH|)
4
7
HVD33, HVD38
45
Propagation delay time,
high-impedance-to-high-
level output
HVD34, HVD39
235
490
25
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
See Figure 6
HVD35
HVD33, HVD38
Propagation delay time,
high-level-to-high-
HVD34, HVD39
65
impedance output
HVD35
165
35
HVD33, HVD38
Propagation delay time,
high-impedance-to-low-level HVD34, HVD39
190
490
30
RL = 110 Ω, RE at 0 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
See Figure 7
output
HVD35
HVD33, HVD38
Propagation delay time,
low-level-to-high-impedance HVD34, HVD39
120
290
output
HVD35
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Y, or
D = 0 V and S1 = Z
See Figure 6
Propagation delay time, standby-to-high-level output
Propagation delay time, standby-to-low-level output
4000
4000
RL = 110 Ω, RE at 3 V,
D = 3 V and S1 = Z, or
D = 0 V and S1 = Y
See Figure 7
(1) All typical values are at 25°C and with a 3.3-V supply.
5
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Positive-going differential input
threshold voltage
VIT+
VIT-
IO = –8 mA
IO = 8 mA
–0.02
V
Negative-going differential input
threshold voltage
–0.20
Vhys
VIK
Hysteresis voltage (VIT+ - VIT-
)
50
mV
V
Enable-input clamp voltage
II = –18 mA
–1.5
2.4
VID = 200 mV, IO = –8 mA, See Figure 8
VID = –200 mV, IO = 8 mA, See Figure 8
VO
Output voltage
V
0.4
1
High-impedance-state output
current
IO(Z)
VO = 0 or VCC, RE at VCC
–1
µA
VA or VB = 12 V
0.05
0.06
0.10
0.10
HVD31, HVD32,
HVD34, HVD35,
HVD37, HVD39
VA or VB = 12 V, VCC = 0 V
VA or VB = -7 V
Other input
at 0V
mA
mA
–0.10
–0.10
–0.04
–0.03
0.20
VA or VB = -7 V, VCC = 0 V
VA or VB = 12 V
Bus input
current
IA or IB
0.35
0.40
VA or VB = 12 V, VCC = 0 V
VA or VB = -7 V
0.24
HVD30, HVD33,
HVD36, HVD38
Other input
at 0 V
–0.35
–0.25
–60
–0.18
–0.13
VA or VB = -7 V, VCC = 0 V
VIH = 0.8 V or 2 V
IIH
Input current, RE
µA
pF
CID
Differential input capacitance
HVD30, HVD31,
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
15
6.4
HVD32
D at 0 V or VCC and No Load
mA
HVD36, HVD37
HVD33
7.9
1.8
2.2
3.8
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (Receiver enabled and
driver disabled)
HVD34, HVD35
HVD38, HVD39
mA
µA
HVD33, HVD34,
HVD35, HVD38,
HVD39
RE at VCC, D at VCC, DE at 0 V,
No load (Receiver disabled and
driver disabled)
0.022
1
ICC
Supply current
HVD33
2.1
6.5
3.5
8.0
1.8
6.2
2.5
7.0
RE at 0 V, D at 0 V or VCC, DE at VCC
No load (Receiver enabled and
driver enabled)
,
HVD34, HVD35
HVD38
HVD39
mA
HVD33
RE at VCC, D at 0 V or VCC, DE at VCC
No load (Receiver disabled and
driver enabled)
HVD34, HVD35
HVD38
HVD39
(1) All typical values are at 25°C and with a 3.3-V supply.
6
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
HVD30, HVD33, HVD36, HVD38
Propagation delay time,
low-to-high-level output
26
45
tPLH
tPHL
tsk(p)
HVD31, HVD32, HVD34, HVD35,
HVD37, HVD39
47
29
49
70
45
70
HVD30, HVD33, HVD36, HVD38
Propagation delay time,
high-to-low-level output
HVD31, HVD32, HVD34, HVD35,
HVD37, HVD39
VID = -1.5 V to 1.5 V,
CL = 15 pF,
See Figure 9
HVD30, HVD33, HVD36, HVD37,
HVD38, HVD39
7
Pulse skew (|tPHL - tPLH|)
HVD31, HVD34, HVD32, HVD35
10
ns
5
tr
Output signal rise time
Output signal fall time
tf
6
20
tPHZ
tPZH1
tPZH2
tPLZ
tPZL1
tPZL2
Output disable time from high level
DE at 3 V
DE at 0 V
DE at 3 V
DE at 0 V
CL = 15 pF
See Figure 10
Output enable time to high level
20
Propagation delay time, standby-to-high-level output
Output disable time from low level
4000
20
CL = 15 pF
See Figure 11
Output enable time to low level
20
Propagation delay time, standby-to-low-level output
4000
(1) All typical values are at 25°C and with a 3.3-V supply
RECEIVER EQUALIZATION CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
DEVICE
MIN
TYP(1)
MAX
UNIT
0 m
HVD36, HVD38
HVD33(2)
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
100 m
HVD36, HVD38
HVD33(2)
25 Mbps
150 m
200 m
200 m
250 m
300 m
500 m
HVD36, HVD38
HVD33(2)
HVD36, HVD38
HVD33(2)
HVD36, HVD38
HVD33(2)
Pseudo-random NRZ
Peak-to-peak
tj(pp) eye-pattern
jitter
10 Mbps
code with a bit pattern
length o 216-1, Belden
3105A cable
HVD36, HVD38
HVD33(2)
ns
HVD36, HVD38
HVD34(2)
5 Mbps
3 Mbps
1 Mbps
HVD37, HVD39
HVD33(2)
HVD34(2)
500 m
HVD36, HVD38
HVD37, HVD39
HVD34(2)
1000 m
HVD37, HVD39
(1) All typical values are at VCC = 5 V, and temperature = 25°C.
(2) The HVD33 and the HVD34 do not have receiver equalization but are specified for comparison.
7
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
DEVICE POWER DISSIPATION - PD
TEST CONDITIONS
DEVICE
MIN
TYP
MAX
UNIT
RL = 60 , CL = 50 pF, Input to D a 50% duty
cycle square wave at indicated signaling rate
TA = 85°C
HVD30, HVD36 (25 Mbps)
HVD31, HVD37 (5 Mbps)
HVD32 (1 Mbps)
197
213
193
197
193
248
mW
RL = 60 , CL = 50 pF, DE at VCC, RE at 0 V,
Input to D a 50% duty cycle square wave at
indicated signaling rate TA = 85°C
HVD33, HVD38 (25 Mbps)
HVD34, HVD39 (5 Mbps)
HVD35 (1 Mbps)
8
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
I
Y
DE
I
I
Y
V
OD
R
0 or 3 V
L
Z
I
Z
V
I
V
Z
V
Y
Figure 1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
V
CC
DE
Y
D
V
OD
60 Ω ±1%
0 or 3 V
+
−7 V < V
< 12 V
(test)
Z
_
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test Circuit
V
OD(SS)
V
OD(RING)
0 V Differential
V
OD(RING)
-V
OD(SS)
Figure 3. VOD(RING) Waveform and Definitions
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
theVOD(H) and VOD(L) steady state values.
V
Y
Y
V
CC
27 Ω ± 1%
V
Z
DE
Z
Y
D
V
OC(PP)
∆V
Input
OC(SS)
27 Ω ± 1%
V
OC
Z
V
OC
C
L
= 50 pF ±20%
C
L
Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t <6ns, t <6ns, Z = 50 Ω
r f O
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
9
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Y
»
W
Z
W
»
W
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
3 V
D
S1
Y
3 V
0 V
1.5 V
Z
1.5 V
Y
V
I
S1
D
0 V
V
0.5 V
O
t
Z
PZH(1 & 2)
V
OH
DE
R
= 110 W
L
V
2.3 V
O
C = 50 pF
L
±1%
~ 0 V
Input
Generator
V
I
50 W
±20%
t
PHZ
Generator: PRR = 500kHz, 50% Duty Cycle, t <6 ns, t < 6ns, Z = 50 W
0
r
f
C
Includes Fixture and Instrumentation Capacitance
L
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
V
CC
D
S1
Z
3 V
0 V
R
L
= 110 Ω
3 V
Y
± 1%
Y
V
I
1.5 V
1.5 V
S1
D
V
O
0 V
Z
t
t
PZL(1&2)
PLZ
DE
V
CC
C
L
= 50 pF ±20%
Input
V
I
50 Ω
0.5 V
Generator
C
L
Includes Fixture
V
O
2.3 V
and Instrumentation
Capacitance
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r f o
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
A
I
O
R
V
A
V
ID
B
V
B
V
IC
V
O
I
B
V
A
+ V
B
RE
2
I
I
V
I
Figure 8. Receiver Voltage and Current Definitions
10
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
A
3 V
V
O
R
Input
1.5 V
1.5 V
V
I
V
I
50 Ω
Generator
B
0 V
1.5 V
C = 15 pF
L
t
t
PLH
PHL
±20%
RE
V
OH
0 V
90% 90%
V
O
1.5 V
10%
1.5 V
C
Includes Fixture and Instrumentation Capacitance
L
10%
V
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t <6 ns, Z = 50 Ω
r f o
t
t
r
f
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
V
CC
A
3 V
1.5 V
0 V
V
A
S1
1 kW ±1%
V
R
O
V
1.5V
1.5V
I
B
C
= 15 pF
B
0V
L
RE
±20%
t
t
PHZ
PZH(1 & 2)
V
Input
Generator
OH
50 W
I
1.5 V
0.5V
~0 V
V
C
Includes Fixture and
O
L
Instrumentation Capacitance
Generator: PRR = 500kHz, 50%, Duty Cycle, t <6 ns, t < 6ns, Z = 50 W
r f 0
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
V
CC
A
3 V
0 V
A
S1
1 k W ±1%
V
R
O
V
1.5V
1.5V
I
B
1.5 V
C
= 15 pF
B
0V
L
RE
±20%
t
PZL(1 & 2)
t
PLZ
V
Input
Generator
CC
V
50 W
I
1.5 V
V
0.5V
O
C
Includes Fixture
L
V
and Instrumentation
Capacitance
OL
Generator: PRR = 500 kHz, 50% Duty Cycle, t <6 ns, t < 6ns, Z = 50 W
r f 0
Figure 11. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
A
DE
Y
D
R
B
Z
100 W
±1%
100 W
±1%
RE
Pulse Generator
15 ms duration
1% Duty Cycle
t , t £ 100 ns
0 V or 3 V
+
+
-
-
r
f
Figure 12. Test Circuit, Transient Over Voltage Test
11
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
DEVICE INFORMATION
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,
most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver
or the receiver is re-enabled, the internal circuitry becomes active.
12
A
2
R
11
B
3
RE
Low-Power
Shutdown
4
DE
9
Y
5
D
10
Z
Figure 13. Low-Power Shutdown Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
12
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
DEVICE INFORMATION (continued)
FUNCTION TABLES
SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38,
SN65HVD39 DRIVER
INPUTS
OUTPUTS
D
H
DE
Y
H
L
Z
L
H
L
H
L or open
H
H
Z
H
X
Z
L
Open
SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38,
SN65HVD39 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE
RE
OUTPUT
R
V
ID ≤ –0.2 V
L
L
?
–0.2 V < VID < –0.02 V
–0.02 V ≤ VID
X
L
L
H
Z
H
H
H
H or open
Open Circuit
Idle circuit
L
L
L
Short Circuit, VA=VB
SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36,
SN65HVD37 DRIVER
OUTPUTS
INPUT
D
Y
Z
H
L
H
L
L
L
H
H
Open
SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36,
SN65HVD37 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
OUTPUT
R
V
ID ≤ –0.2 V
L
?
–0.2 V < VID < –0.02 V
–0.02 V ≤ VID
H
H
H
H
Open Circuit
Idle circuit
Short Circuit, VA=VB
13
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
RE Input
D and DE Input
VCC
VCC
130 kW
470 W
470 W
Input
Input
9 V
9 V
125 kW
A Input
B Input
VCC
VCC
R1
R1
22 V
R3
22 V
R3
Input
Input
R2
22 V
R2
22 V
R Output
Y and Z Outputs
VCC
VCC
16 V
5 W
Output
Output
16 V
9 V
R1/R2
R3
SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38
9 kΩ
45 kΩ
180 kΩ
SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 SN65HVD37, 36 kΩ
SN65HVD38, SN65HVD39
14
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
TYPICAL CHARACTERISTICS
HD30, HD33 RMS Supply Current
HD31, HD34 RMS Supply Current
vs
vs
Signaling Rate
Signaling Rate
55
60
55
50
45
40
35
30
T
A
=25°C
R
L
= 54 W
T
A
=25°C
R = 54 W
L
RE = V
C
= 50 pF
RE = V
C = 50 pF
L
CC
L
CC
DE = V
DE = V
CC
CC
50
45
40
35
30
V
= 3.3 V
V
= 3.3 V
CC
CC
0
5
10
15
20
25
0
1
2
3
4
5
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 14.
Figure 15.
HD32, HD35 RMS Supply Current
vs
Signaling Rate
60
55
50
45
40
35
T
A
=25°C
R = 54 W
L
RE = V
C = 50 pF
L
CC
DE = V
CC
V
= 3.3 V
CC
30
0
0.2
0.4
0.6
0.8
1
Signaling Rate - Mbps
Figure 16.
15
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
HVD30, HVD33
Bus Input Current
vs
HVD31, HVD32, HVD34, HVD35
Bus Input Current
vs
Input Voltage
Input Voltage
250
60
40
20
0
T
A
= 25°C
T
A
= 25°C
RE = 0 V
RE = 0 V
200
150
100
50
DE = 0 V
DE = 0 V
V
= 3.3 V
V
= 3.3 V
CC
0
CC
-50
-20
-40
-60
-100
-150
-200
-7
-4
-1
2
5
8
11
14
-7
-4
-1
2
5
8
11
14
V - Bus Input Voltage - V
I
V - Bus Input Voltage - V
I
Figure 17.
Figure 18.
Driver Low-Level Output Current
vs
Driver High-Level Output Current
vs
Low-Level Output Voltage
High-Level Output Voltage
0.01
-0.01
-0.03
-0.05
-0.07
-0.09
-0.11
-0.13
0.14
0.12
0.1
V
CC
= 3.3 V
V
= 3.3 V
CC
DE = V
CC
DE = V
CC
D = 0 V
D = 0 V
0.08
0.06
0.04
0.02
0
-0.02
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
V
- Low-Level Output Voltage - V
V
- High-Level Output Voltage - V
OL
OH
Figure 19.
Figure 20.
16
SN65HVD30-SN65HVD35
SN65HVD36-SN65HVD39
www.ti.com
SLLS665–SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Driver Differential Output Voltage
Driver Output Current
vs
vs
Free-Air Temperature
Supply Voltage
2.2
40
35
30
25
20
15
10
5
V
= 3.3 V
CC
T
A
= 25°C
DE = V
CC
R
= 54 W
L
D = V
CC
D = V
CC
DE = V
2.1
2.0
1.9
1.8
CC
V
= 3.3 V
CC
0
0
0.5
1
1.5
2
2.5
3
3.5
-40
-15
10
35
60
85
V
Supply Voltage - V
T
A
- Free Air Temperature - °C
CC
Figure 21.
Figure 22.
17
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
Drawing
SN65HVD33D
SN65HVD33DR
SN65HVD34D
SN65HVD34DR
SN65HVD35D
SN65HVD35DR
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
D
D
D
D
D
D
14
14
14
14
14
14
50
2500
50
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
50
50
2500
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
SN65HVD33D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD33DG4
SN65HVD33DR
SN65HVD33DRG4
SN65HVD34D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD34DG4
SN65HVD34DR
SN65HVD34DRG4
SN65HVD35D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65HVD35DG4
SN65HVD35DR
SN65HVD35DRG4
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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