SN65HVD485EDGKR [TI]
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| 型号： | SN65HVD485EDGKR |
| 厂家： | 
TEXAS INSTRUMENTS |
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DGK
D
P
www.ti.com
SLLS612 − JUNE 2004
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FEATURES
DESCRIPTION
The SN65HVD485E is a half-duplex transceiver designed
for RS-485 data bus networks. Powered by a 5-V supply,
it is fully compliant with the TIA/EIA-485A standard. This
device is suitable for data transmission up to 10 Mbps over
long twisted-pair cables and is designed to operate with
very low supply current, typically less than 2 mA, exclusive
of the load. When in the inactive shutdown mode, the
supply current drops below 1 mA.
D
D
D
D
D
Bus-Pin ESD Protection Up to 15 kV
1/2 Unit Load—Up to 64 Nodes on a Bus
Bus Open Failsafe Receiver
Available in Small MSOP-8 Package
Meets or Exceeds the Requirements of the
TIA/EIA−485A Standard
D
Industry-Standard SN75176 Footprint
The wide common-mode range and high ESD protection
levels of this device make it suitable for demanding
applications such as, electrical inverters, status/command
signals across telecom racks, cabled chassis
interconnects, and industrial automation networks where
noise tolerance is essential. The SN65HVD485E matches
the industry-standard footprint of the SN75176. Power-on
reset circuits keep the outputs in a high-impedence state
until the supply voltage has stabilized. A thermal shutdown
function protects the device from damage due to system
fault conditions. The SN65HVD485E is characterized for
operation from −40°C to 85°C air temperature.
APPLICATIONS
D
D
D
D
D
D
D
Motor Control
Power Inverters
Industrial Automation
Building Automation Networks
Industrial Process Control
Battery-Powered Applications
Telecommunications Equipment
Improved Replacement for:
PART NUMBER REPLACE WITH
ADM485
HVD485E: Better ESD protection ( 15 kV vs. unspecified)
Faster signaling rate (10 Mbps vs. 5 Mbps)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
SP485E
HVD485E: More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
LMS485E
HVD485E: Higher signaling rate (10 Mbps vs. 2.5 Mbps)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
DS485
HVD485E: Higher signaling rate (10 Mbps vs. 2.5 Mbps)
Better ESD ( 15 kV vs. 2 kV)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
LTC485
HVD485E: Better ESD ( 15 kV vs. 2 kV)
Wider power supply tolerance (10% vs. 5%)
MAX485E
HVD485E: Higher signaling rate (10 Mbps vs. 2.5 Mbps)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
ST485E
HVD485E: Higher signaling rate (10 Mbps vs. 5 Mbps)
Wider power supply tolerance (10% vs. 5%)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢏꢑ ꢕ ꢆꢎ ꢓ ꢒꢔ ꢕꢁ ꢆ ꢊꢒꢊ ꢖꢗ ꢘꢙ ꢚ ꢛꢜ ꢝꢖꢙꢗ ꢖꢞ ꢟꢠ ꢚ ꢚ ꢡꢗꢝ ꢜꢞ ꢙꢘ ꢢꢠꢣ ꢤꢖꢟ ꢜꢝꢖ ꢙꢗ ꢥꢜ ꢝꢡꢦ ꢏꢚ ꢙꢥꢠ ꢟꢝꢞ
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ꢏꢚ ꢙ ꢥꢠꢟ ꢝ ꢖꢙ ꢗ ꢢꢚ ꢙ ꢟ ꢡ ꢞ ꢞ ꢖꢗ ꢫ ꢥꢙ ꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ ꢝꢡ ꢞꢝꢖ ꢗꢫ ꢙꢘ ꢜꢤ ꢤ ꢢꢜ ꢚ ꢜꢛ ꢡꢝꢡ ꢚ ꢞꢦ
Copyright 2004, Texas Instruments Incorporated
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SLLS612 − JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE TYPE
(1)
T
A
(2)
DGK
P
D
SN65HVD485EP
Marked as 65HVD485
SN65HVD485ED
Marked as VP485
SN65HVD485EDGK
Marked as NWJ
−40°C to 85°C
(1)
(2)
The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD485EDR).
The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD485EDGKR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1) (2)
UNITS
Supply voltage range, V
Voltage range at A or B
−0.5 V to 7 V
−9 V to 14 V
CC
Voltage range at any logic pin
Receiver output current
−0.3 V to V + 0.3 V
CC
−24 mA to 24 mA
−50 V to 50 V
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 13)
Storage temperature range
−65°C to 130°C
Junction temperature, T
170°C
J
Continuous total power dissipation
Refer to Package Dissipation Table
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under recommendedoperating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
(3)
DERATING FACTOR
T
<25°C
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
JEDEC BOARD MODEL
POWER RATING
ABOVE T = 25°C
POWER RATING
A
(1)
Low k
507 mW
4.82 mW/°C
7.85 mW/°C
6.53 mW/°C
3.76 mW/°C
5.55 mW/°C
289 mW
217 mW
D
P
(2)
High k
824 mW
471 mW
353 mW
(1)
Low k
686 mW
392 mW
294 mW
(1)
Low k
394 mW
255 mW
169 mW
DGK
(2)
High k
583 mW
333 mW
250 mW
(1)
(2)
(3)
In accordance with the low-k thermal metric definitions of EIA/JESD51-3
In accordance with the high-k thermal metric definitions of EIA/JESDS1-7
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
4.5
−7
TYP
MAX
5.5
UNIT
Supply voltage, V
CC
V
V
V
V
V
Input voltage at any bus terminal (separately or common mode), V
12
I
High-level input voltage (D, DE, or RE inputs), V
IH
2
V
CC
0.8
Low-level input voltage (D, DE, or RE inputs), V
IL
0
Differential input voltage, V
ID
−12
−60
−8
12
60
8
Driver
Output current, I
mA
O
Receiver
Differential load resistance, R
54
60
Ω
L
Signaling rate, 1/t
UI
0
10 Mbps
Operating free−air temperature, T
−40
−40
85
130
°C
°C
A
(2)
Junction temperature, T
J
(1)
(2)
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
See thermal characteristics table for information on maintenance of this specification for the DGK package.
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SUPPLY CURRENT
over recommended operating conditions unless otherwise noted
(1)
TYP
PARAMETER
TEST CONDITIONS
or open or 0V, DE at V , RE at 0 V,
MIN
MAX
UNIT
mA
D at V
CC
CC
Driver and receiver enabled
Driver and receiver disabled
2
No load
I
CC
D at V
or open,
DE at 0 V, RE at V
1
mA
CC
CC
(1)
All typical values are at 25°C and with a 5-V supply.
ELECTROSTATIC DISCHARGE PROTECTION
(1)
PARAMETER
TEST CONDITIONS
Bus terminals and GND
MIN TYP
MAX
UNIT
kV
Human body model
Human body model
15
4
(2)
All pins
All pins
kV
(3)
Charged-device-model
1
kV
(1)
(2)
(3)
All typical values at 25°C
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
(1)
TYP
TEST CONDITIONS
MIN
MAX
UNIT
I
= 0, No load
3
4.3
2.3
O
R
= 54 Ω, See Figure 1
1.5
L
V
OD
Differential output voltage
V
V
= −7 V to 12 V,
TEST
1.5
See Figure 2
∆V
Change in magnitude of differential output voltage
Steady-state common-mode output voltage
See Figure 1 and Figure 2
−0.2
1
0
0.2
3
V
V
OD
V
2.6
OC(SS)
See Figure 3
Change in steady-state common-mode output
voltage
∆V
−0.1
0
0.1
OC(SS)
V
See Figure 3
500
mV
OC(PP)
I
I
I
High-impedance output current
Input current
See receiver input currents
D, DE
OZ
µA
−100
−250
100
250
I
Short-circuit output current
−7 V ≤ V ≤ 12 V, See Figure 7
mA
OS
O
(1)
All typical values are at 25°C and with a 5V-supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
30
UNIT
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
t
t
t
t
t
t
t
t
t
PLH
PHL
r
30
R
= 54 Ω, C = 50 pF,
L
L
25
ns
See Figure 4
Differential output signal fall time
25
f
Pulse skew ( |t
- t
| )
5
PHL PLH
sk(p)
PZH
PHZ
PZL
PLZ
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, low-level-to-high-impedance output
150
100
150
100
R
= 110 Ω,
L
ns
RE at 0 V, See Figure 5
R
= 110 Ω, RE at 0 V
See Figure 6
L
ns
ns
ns
R
= 110 Ω, RE at V
See Figure 5
,
,
L
CC
Propagation delay time, shutdown-to-high-level output
Propagation delay time, shutdown-to-low-level output
2600
2600
t
PZH(SHDN)
PZL(SHDN)
R
= 110 Ω, RE at V
See Figure 6
L
CC
t
3
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
(1)
MIN TYP
PARAMETER
TEST CONDITIONS
= −8 mA
MAX UNIT
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
Negative-going input threshold voltage
I
I
−85
−115
30
−10
mV
mV
mV
O
= 8 mA
−200
4
O
Hysteresis voltage (V
IT+
− V )
IT−
V
= 200 mV, I
OH
= −8 mA, See
= 8 mA, See
ID
V
OH
V
OL
High-level output voltage
Low-level output voltage
4.6
V
Figure 8
V
= −200 mV, I
ID OH
Figure 8
0.15
0.4
V
I
High-impedance-state output current
V
V
V
V
V
V
V
= 0 to V , RE= V
CC CC
−1
1
0.5
0.5
µA
OZ
O
= 12 V, V
= 12 V, V
= −7 V, V
= −7 V, V
= 2 V
= 5 V
= 0
IH
IH
IH
IH
IH
IL
CC
CC
CC
CC
I
I
Bus input current
mA
= 5 V
= 0
−0.4
−0.4
−60
−60
I
I
High-level input current (RE)
Low-level input current (RE)
−30
−30
µA
µA
IH
= 0.8 V
IL
V = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
I
C
diff
Differential input capacitance
7
pF
(1)
All typical values are at 25°C and with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
200
200
PLH
ns
PHL
V
C
= −1.5 V to 1.5 V,
= 15 pF, See Figure 9
ID
L
Pulse skew ( |t
− t
| )
8
sk(p)
PHL PLH
Output signal rise time
Output signal fall time
3
3
r
ns
ns
µs
f
Output enable time to high level
50
PZH
Output enable time to low level
50
PZL
C
= 15 pF, DE at 3 V,
L
See Figure 10 and Figure 11
Output enable time from high level
50
PHZ
Output enable time from low level
50
PLZ
Propagation delay time, shutdown-to-high-level output
Propagation delay time, shutdown-to-low-level output
3500
3500
PZH(SHDN)
PZL(SHDN)
C = 15 pF, DE at 0 V,
L
See Figure 12
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PARAMETER MEASUREMENT INFORMATION
NOTE:Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and
fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. Z = 50 Ω (unless otherwise specified).
O
I
A
B
OA
OB
27 Ω
27 Ω
I
I
V
OD
50 pF
0 V or 3 V
D
I
V
OC
Figure 1. Driver Test Circuit, V
and V
Without Common-Mode Loading
OC
OD
375 Ω
I
I
OA
V
= −7 V to 12 V
TEST
V
OD
60 Ω
375 Ω
0 V or 3 V
OB
V
TEST
Figure 2. Driver Test Circuit, V
With Common-Mode Loading
OD
27 Ω
A
V
A
9 3.25 V
9 1.75 V
D
27 Ω
V
B
Signal
Generator
B
50 Ω
V
V
OC
∆V
OC(PP)
OC(SS)
50 pF
V
OC
Figure 3. Driver V
Test Circuit and Waveforms
OC
3 V
0 V
INPUT
t
1.5 V
1.5 V
V
OD
R
L
= 54 Ω
t
PLH
PHL
C
L
= 50 pF
V
OD(H)
OD(L)
Signal
Generator
90%
10%
50 Ω
0 V
OUTPUT
V
t
r
t
f
Figure 4. Driver Switching Test Circuit and Waveforms
5
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A
B
S1
3 V
0 V
Output
R
D
0 V or 3 V
1.5 V 1.5 V
DE
t
3 V if Testing A Output
0 V if Testing B Output
0.5 V
C
= 50 pF
L
PZH
= 110 Ω
L
DE
V
OH
Output
Signal
Generator
2.5 V
50 Ω
V
Off
0
t
PHZ
Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output
5 V
R
L
= 110 Ω
A
B
S1
3 V
D
Output
0 V or 3 V
1.5 V 1.5 V
DE
t
0 V if Testing A Output
3 V if Testing B Output
0 V
5 V
C
L
= 50 pF
PZL
t
DE
PLZ
Output
Signal
Generator
2.5 V
V
OL
50 Ω
0.5 V
Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output
I
OS
I
O
V
O
V
ID
Voltage
Source
V
O
Figure 7. Driver Short-Circuit Test
Figure 8. Receiver Parameter Definitions
Signal
Generator
50 Ω
Input B
V
ID
1.5 V
0 V
A
B
50%
I
O
Input A
t
R
t
PHL
PLH
V
C
= 15 pF
O
V
OH
Signal
Generator
L
90%
50 Ω
Output
1.5 V
10%
V
OL
t
r
t
f
Figure 9. Receiver Switching Test Circuit and Waveforms
6
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D
V
V
CC
DE
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
0 V
C
L
= 15 pF
RE
t
t
PZH
PHZ
Signal
Generator
V
OH
−0.5 V
50 Ω
V
OH
1.5 V
R
GND
Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High
D
0 V
DE
V
CC
A
54 Ω
B
3 V
0 V
1 kΩ
R
RE
1.5 V
PZL
5 V
C
L
= 15 pF
RE
t
t
PLZ
Signal
Generator
V
CC
50 Ω
1.5 V
R
V
OL
+0.5 V
V
OL
Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low
V
CC
Switch Down for V
= 1.5 V,
(A)
= −1.5 V
Switch Up for V
(A)
A
B
1.5 V or
−1.5 V
R
3 V
1 kΩ
1.5 V
RE
C
L
= 15 pF
0 V
RE
t
t
PZH(SHDN)
PZL(SHDN)
Signal
Generator
50 Ω
5 V
R
V
V
OH
1.5 V
OL
0 V
Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms
7
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V
TEST
100 Ω
0 V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
1.5 ms
15 µs
−V
TEST
Figure 13. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION
PIN ASSIGNMENTS
LOGIC DIAGRAM (POSITIVE LOGIC)
D, P OR DGK PACKAGE
(TOP VIEW)
4
D
R
RE
DE
D
V
B
A
1
2
3
4
8
7
6
5
3
CC
DE
RE
2
6
A
1
GND
R
7
B
FUNCTION TABLE
DRIVER
RECEIVER
OUTPUTS
INPUT
D
ENABLE
DE
DIFFERENTIAL INPUTS
= V – V
ENABLE
RE
OUTPUT
R
V
ID
A
H
L
B
L
A
B
H
L
H
H
V
≤ −0.2 V
L
L
?
ID
−0.2 V < V < −0.01 V
H
Z
L
L
L
ID
X
L
Z
H
Z
−0.01 V ≤ V
H
Z
H
Z
ID
Open
X
H
X
H
Open
Z
Open circuit
X
L
Open
:
NOTE H= high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input
DE Input
V
CC
V
CC
200 kΩ
500 ꢀ
500 ꢀ
Input
Input
200 kΩ
9 V
9 V
A Input
B Input
V
CC
V
CC
16 V
16 V
180 kΩ
36 kΩ
36 kΩ
180 k Ω
Input
Input
36 kΩ
16 V
16 V
36 kΩ
A and B Outputs
R Outputs
V
CC
V
CC
16 V
5 Ω
Output
Output
16 V
9 V
THERMAL CHARACTERISTICS
DGK Package
PARAMETER
TEST CONDITIONS
MIN
TYP
266
MAX
UNIT
(2)
Low-k board, no air flow
(1)
Θ
JA
Junction-to-ambient thermal resistance
°C/W
(3)
High-k board, no air flow
180
108
66
(3)
Θ
Θ
Junction-to-board thermal resistance
Junction-to-case thermal resistance
High-k board, no air flow
JB
°C/W
JC
R
L
= 54 Ω, Input to D is a 10 Mbps
P
Average power dissipation
50% duty cycle square wave
at 5.5 V, T = 130°C
219
mW
(AVG)
V
cc
J
JEDEC High K board model
JEDEC Low K board model
−40
−40
93
75
°C
°C
°C
T
Ambient air temperature
A
T
SD
Thermal shut-down junction temperature
165
(1)
(2)
(3)
See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
9
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SLLS612 − JUNE 2004
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
BUS INPUT CURRENT
vs
vs
DIFFERENTIAL OUTPUT CURRENT
BUS INPUT VOLTAGE
5
80
60
T
V
= 25°C
A
4.5
= 5 V
CC
R
L
= 120Ω
4
40
20
0
3.5
3
V
CC
= 0 V
R
L
= 60Ω
2.5
V
CC
= 5 V
2
1.5
−20
1
−40
−60
0.5
0
−8 −6 −4 −2
0
2
4
6
8
10 12
0
10
20
30
40
50
V − Bus Input Voltage − V
I
I
O
− Differential Output Current − mA
Figure 14
Figure 15
APPLICATION INFORMATION
R
T
R
T
:
NOTE The line should be terminated at both ends with its characteristic impedance (R = Z ).
T
O
Stub lengths off the main line should be kept as short as possible.
Figure 16. Typical Application Circuit
POWER USAGE IN AN RS-485 TRANSCEIVER
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the
transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the
receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard
defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all
receivers can be as high as 32 mA. The HVD485E is rated as a 1/2 unit load device, so up to 64 can be connected on a
bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to
produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at each end, this sums
to 25 mA differential output current whenever the bus is active. Typically the HVD485E can drive more than 25 mA to a
60 Ω load, resulting in a differential output voltage higher than the minimum required by the standard. (See Figure 15.)
Supply current increases with signaling rate primarily due to the totum pole outputs of the driver. When these outputs
change state, there is a moment when both the high-side and low-side output transistors are conducting and this creates
a short spike in the supply current. As the frequency of state changes increases, more power is used.
10
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SLLS612 − JUNE 2004
THERMAL CHARACTERISTICS OF IC PACKAGES
Θ
JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
Θ
D
D
D
Θ
JA is NOT a constant and is a strong function of
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures.
installations.
is often misused when it is used to calculate junction temperatures for other
Θ
JA
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
Θ
JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is
only defined for the high-k test card.
Θ
JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see figure 18).
Ambient Node
ꢁ
Calculated
CA
Surface Node
Calculated/Measured
ꢁ
JC
Junction
Calculated/Measured
ꢁ
JB
PC Board
Figure 17. Thermal Resistance
11
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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