SN65HVS881PWP [TI]
具有诊断功能的 34V、8 通道数字输入串行器 | PWP | 28 | -40 to 125;
| 型号： | SN65HVS881PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有诊断功能的 34V、8 通道数字输入串行器 | PWP | 28 | -40 to 125 驱动 光电二极管 接口集成电路 线路驱动器或接收器 驱动程序和接口 |
| 文件： | 总22页 (文件大小：825K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642–MARCH 2009
INDUSTRIAL 8-DIGITAL-INPUT SERIALIZER WITH DIAGNOSTICS
1
FEATURES
•
•
•
Cascadable in Multiples of Eight Inputs
SPI-Compatible Interface
2
•
Eight Inputs
–
–
–
–
High Input Voltage – up to 34 V
Regulated 5-V Output for External Isolator
Selectable Debounce Filters – 0 ms to 3 ms
Flexible Input Current Limit: 0.2 to 5.2 mA
Field Pins Protected to 15-kV HBM ESD
APPLICATIONS
•
Sensor Inputs for Industrial Automation and
Process Control
High Channel Count Digital Input Modules for
PC and PLC Systems
Decentralized I/O Modules
Motion Control Systems
•
•
Diagnostics:
•
–
–
–
Parity Check
•
•
Undervoltage Indication
Overtemperature Indication
Output Drivers for External Status LEDs
DESCRIPTION
The SN65HVS881 is an eight channel, digital-input serializer for high-channel density digital input modules in
industrial automation. In combination with galvanic isolators the device completes the interface between the high
voltage signals on the field-side and the low-voltage signals on the controller side. Input signals are
current-limited and then validated by internal debounce filters.
With the addition of a few external components, the input switching characteristics can be configured in
accordance with IEC61131-2 for Type 1, 2 and 3 sensor switches.
Upon the application of load and clock signals, input data is latched in parallel into the shift register and
afterwards clocked out serially.
Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial
input of the following device, enabling the design of high-channel count input modules. Multiple devices can be
cascaded through a single serial port, reducing both the isolation channels and controller inputs required.
Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a
single external precision resistor. An integrated voltage regulator provides a 5V output to supply low-power
isolators. An on-chip temperature sensor provides diagnostic information for graceful shutdown and system
safety. An internal parity check for odd parity ensures trustworthy transmission of serial data to the system
controller.
The SN65HVS881 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The
device is characterized for operation at temperatures from –40°C to 125°C
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN65HVS881
SLAS642–MARCH 2009................................................................................................................................................................................................... www.ti.com
DB0
DB1
IP0
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
SIP
Voltage
Regulator
2
VCC
5V out
3
LD
Debounce Select
DB0 : DB1
2
RE0
IP1
4
CLK
CE
Serial Input
5V
8
5
Control Inputs
LD, CE, CLK
3
RE1
IP2
6
SOP
IP7
Field Inputs
IP0 : IP7
8
7
RE2
IP3
8
RE7
IP6
9
LED Outputs
RE0 : RE7
8
RE3
IP4
10
11
12
13
14
RE6
IP5
RE4
RLIM
VCC
RE5
HOT
5VOP
I
REF Adj: RLIM
Serial Output
Field Ground
FUNCTIONAL BLOCK DIAGRAM
Voltage
Regulator
5VOP
HOT
Thermal
Sensor
VCC
5V
Supply
Monitor
GND
RLIM
DB0
DB1
SIP
Adj. Current
Thresholds
Debounce
Select
RE0
IP0
Current
Sense
Debounce
Filter
&
LD
Voltage
Sense
CE
Channel 0
CLK
Parity
Generator
RE7
IP7
Channel 7
SOP
2
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Product Folder Link(s): SN65HVS881
SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642–MARCH 2009
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
PIN NO.
NAME
1, 2
DB0, DB1
Debounce select inputs
Input channel x
3, 5, 7, 9,
11, 18, 20, 22
IPx
4, 6, 8, 10,
12, 17, 19, 21
REx
Return path x (LED drive)
13
14
15
16
23
24
25
26
27
28
RLIM
VCC
Current limiting resistor
Field supply voltage
5VOP
HOT
SOP
CE
5-V output to supply low-power isolators
Active low over-temperature indication
Serial data output
Clock enable input
CLK
LD
Serial clock input
Load pulse input
SIP
Serial data input
GND
Field ground
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ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 36
–0.5 to 36
–0.5 to 6
±8
UNIT
V
VCC
VIPx
VID
IO
Field power input
Field digital inputs
Voltage at any logic input
Output current
IPx
V
DB0, DB1, CLK, SIP, CE, LD
V
HOT, SOP
All pins
mA
±4
Human-Body Model(2)
kV
IPx, VCC
All pins
±15
VESD
Electrostatic discharge
Charged-Device Model(3)
Machine Model(4)
±1
kV
V
All pins
±100
PTOT
TJ
Continuous total power dissipation See Thermal Characteristics Table
Junction temperature
170
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) JEDEC Standard 22, Method A114-A.
(3) JEDEC Standard 22, Method C101
(4) JEDEC Standard 22, Method A115-A
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
θJA Junction-to-air thermal resistance
High-K JEDEC thermal resistance model
35
°C/W
Junction-to-board thermal
resistance
θJB
15
°C/W
Junction-to-case thermal
resistance
θJC
4.27
°C/W
mW
IP0-IP7 = VCC = 34 V
2970
2600
2020
890
ICC and IIP-LIM = worst case with
RLIM = 25 kΩ, ILOAD = 50 mA on 5VOP,
RE0-RE7 = GND, fIP = 100 MHz
IP0-IP7 = VCC = 30 V
IP0-IP7 = VCC = 24 V
IP0-IP7 = VCC = 12 V
PD Device power dissipation
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC
VIPL
VIPH
VIL
Field supply voltage
10
0
34
4
V
V
Field input low-state input voltage
Field input high-state input voltage
Logic low-state input voltage
Logic high-state input voltage
Current limiter resistor
5.5
0
34
V
0.8
5.5
500
1
V
VIH
2.0
17
0
V
RLIM
25
kΩ
Mbps
(1)
fIP
Input data rate (each field input)
VCC ≤ 34 V
VCC ≤ 27 V
VCC ≤ 18 V
–40
–40
–40
85
TA
Free-air temperature, see Thermal Characteristics
105
125
150
°C
°C
TJ
Junction temperature
(1) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω
4
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www.ti.com................................................................................................................................................................................................... SLAS642–MARCH 2009
ELECTRICAL CHARACTERISTICS
Over full-range of recommended operating conditions, unless otherwise noted
PARAMETER
TERMINAL
TEST CONDITIONS
MIN
TYP MAX
UNIT
FIELD INPUTS
Low-level device input threshold
voltage
VTH–(IP)
4.0
4.3
High-level device input threshold
voltage
IP0–IP7
RLIM = 25 kΩ
V
VTH+(IP)
VHYS(IP)
VTH–(IN)
5.2
0.9
8.4
5.5
10
18
Device input hysteresis
Low-level field input threshold
voltage
6
Measured at 18 V < VCC <30 V,
field side of RIN = 1.2 kΩ ± 5%,
High-level field input threshold
voltage
V
V
VTH+(IN)
9.4
1
RIN
RLIM = 25 kΩ, TA ≤ 85 °C
VHYS(IN)
VTH– (VCC)
Field input hysteresis
Low-level VCC-monitor threshold
voltage
15
16.05
High-level VCC-monitor threshold
voltage
VCC
VTH+ (VCC)
16.8
VHYS (VCC)
RIP
VCC-monitor hysteresis
Input resistance
0.75
0.63
3.6
0
IP0–IP7
IP0–IP7
3 V < VIPx < 6 V, RLIM = 25 k
RLIM = 25 kΩ
0.2
1.1
4
kΩ
IIP-LIM
Input current limit
3.15
mA
DB0 = open, DB1 = GND
DB0 = GND, DB1 = open
DB0 = DB1 = open
tDB
Debounce times of input channels
RE on-state current
IP0–IP7
1
ms
3
IRE-on
RE0–RE7
RLIM = 25 kΩ, REx = GND
2.8
3.15
3.5
8.7
mA
FIELD SUPPLY
IP0 to IP7 = VCC, 5VOP = open,
REX = GND, All logic inputs open
ICC(VCC)
Supply current, no load
VCC
mA
5V REGULATED OUTPUT
10V < VCC < 34V, no load
10V < VCC < 34V, IL = 5mA
10V < VCC < 34V, IL = 20mA,
4.5
4.5
5
5
5.5
5.5
VO(5V)
Linear regulator output voltage
V
4.5
4.5
5
5.5
5.5
5VOP
T
A ≤ 105°C
10V < VCC < 34V, IL = 50 mA,
A ≤ 85°C
5
T
ILIM(5V)
Linear regulator output current limit
Linear regulation
115
mA
ΔV5/ΔVCC
5VOP, VCC 10V < VCC < 34V, IL = 5 mA
2
mV/V
LOGIC INPUT AND OUTPUTS
VOL
VOH
Logic low-level output voltage
IOL = 20 µA
SOP, HOT
0.4
V
V
Logic high-level output voltage
IOH = –20 µA
4
DB0, DB1,
SIP,
IIL
Logic input leakage current
–50
50
µA
LD, CE, CLK
Over-temperature indication
(internal)
TOVER
TSHDN
HOT
150
170
°C
°C
Shutdown temperature (internal)
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TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN TYP MAX
UNIT
ns
tW1
CLK pulse duration
LD pulse duration
See Figure 6
See Figure 4
See Figure 7
See Figure 7
See Figure 8
See Figure 5
See Figure 6
4
6
4
2
4
2
tW2
ns
tSU1
tH1
SIP to CLK setup time
SIP to CLK hold time
ns
ns
tSU2
tREC
fCLK
Falling edge to rising edge (CE to CLK) setup time
LD to CLK recovery time
ns
ns
Clock pulse frequency
DC
100
MHz
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
10
UNIT
ns
tPLH1, tPHL1
tPLH2, tPHL2
tr, tf
CLK to SOP
CL = 15 pF, see Figure 6
CL = 15 pF, see Figure 4
CL = 15 pF, see Figure 6
LD to SOP
14
ns
Rise and fall times
5
ns
6
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INPUT CHARACTERISTICS
30
R
= 1.2 kW
IN
25
20
15
10
5
a) I
b) I
c) I
= 2.5 mA (R
= 36.1 kW)
LIM
IP-LIM
IP-LIM
IP-LIM
a)
b)
c)
= 3 mA (R
= 30.1 kW)
= 24.9 kW)
LIM
= 3.6 mA (R
LIM
Off
On
Field Input Thresholds
2.5 3.5
0
0
0.5
1
1.5
2
3
4
I
/mA
IN
Figure 1. Typical Input Characteristic
102
101.5
101
9.6
V 24 = 24 V,
= 24 V,
V
TH+ (IN)
V
IN
9.4
R
R
= 1.2 kW,
IN
= 24.9 kW
LIM
9.2
9
100.5
100
99.5
99
8.8
8.6
V
TH- (IN)
8.4
8.2
8
V 24 = 24 V,
= 1.2 kW,
R
98.5
98
IN
R
= 24.9 kW
LIM
-45 -35 -25 -15 -5
T
5 15 25 35 45 55 65 75 85 95
- Free-Air Temperature - °C
-45 -35 -25 -15 -5
T
5 15 25 35 45 55 65 75 85 95
- Free-Air Temperature - °C
A
A
Figure 2. Typical Current Limiter Variation vs Ambient
Temperature
Figure 3. Typical Limiter Input Threshold Voltage Variation
vs Ambient Temperature
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PARAMETER MEASUREMENT INFORMATION
Waveforms
For the complete serial interface timing, refer to Figure 21.
t
W2
LD
LD
t
REC
t
t
PHL2
PLH2
CLK
SOP
Figure 4. Parallel – Load Mode
Figure 5. Serial – Shift Mode
1/f
Valid
CLK
t
w1
SIP
CLK
SOP
t
t
H1
SU1
t
t
PHL1
PLH1
CLK
t
r
t
f
Figure 6. Serial – Shift Mode
Figure 7. Serial – Shift Mode
CLK
t
SU2
CLK Inhibited
CE
Figure 8. Serial – Shift Clock Inhibit Mode
8
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VOLTAGE REGULATOR PERFORMANCE CHARACTERISTICS
5
6
4
2
I
= 0 mA
I
= 5 mA,
LOAD
LOAD
= 27°C
T
4.995
4.990
4.985
4.980
4.975
4.970
A
0
-2
-4
-6
-8
4.965
4.960
-10
0
5
10
V
15
20
- Input Voltage - V
25
30
35
-45 -35 -25 -15 -5
T
5
15 25 35 45 55 65 75 85 95
- Free-Air Temperature - °C
A
IN
Figure 9. Line Regulation
Figure 10. Output Voltage vs Ambient Temperature
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
R
= 100 W
LOAD
25
0
0
5
10
V
15
20
30
35
- Input Voltage - V
IN
Figure 11. Output Voltage vs Input Voltage
R
IN
IPx
I
IN
V
SN65HVS881
FGND
TH(IP)
V
TH(IN)
Figure 12. On/Off Threshold Voltage Measurements
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DEVICE INFORMATION
Digital Inputs
V-Ref
5V
I
Mirror
LIM
n = 72
I
IN
IPx
I
I
REF
LIM
Limiter
= I
R
LIM
I
INmax LIM
Figure 13. Digital Input Stage
Each digital input operates as a controlled current sink limiting the input current to a maximum value of ILIM. The
current limit is derived from the reference current via ILIM = n × IREF, and IREF is determined by IREF = VREF/RLIM
Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/ILIM
.
.
While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ), it is easy to lower the current limit to
further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate:
90
90
R
=
=
= 36 kΩ
LIM
I
2.5 mA
LIM
Debounce Filter
The HVS881 applies a simple analog/digital filtering technique to remove unintended signal transitions due to
contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration
of the selected debounce time to be latched into the shift register as a valid state.
The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the
different debounce times listed in the following truth table
Table 1. Debounce Times
DB1
Open
Open
DB0
Open
GND
FUNCTION
3 ms delay
1 ms delay
0 ms delay
(filter bypassed)
GND
GND
Open
GND
Reserved
10
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5V
IPx
REF
REx
R
LIM
FGND
Figure 14. Equivalent Input Diagram
Shift Register
The conversion from parallel input- to serial output data is performed by an eight channel parallel-in serial-out
shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7 that are enabled by a low level at
the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register
also provides a clock-enable function.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock
enable (CE) input is held low. Parallel loading is inhibited when /LD is held high. The parallel inputs to the
register are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.
SIP
SOP
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
CLK
CE
Logic
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
LD
PAR
UVO
HOT
PIP 0
PIP 1
PIP 6
PIP 7
Figure 15. Shift Register Logic Structure
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Table 2. Function Table
INPUTS
FUNCTION
LD
L
CLK
X
CE
X
Parallel load
No change
Shift(1)
H
X
H
H
↑
L
(1) Shift = content of each internal register shifts towards serial outputs.
Data at SIP is shifted into first register.
Voltage Regulator
The on-chip linear voltage regulator provides a 5V supply to the internal- and external-circuitry, such as digital
isolators, with an output drive capability of 50 mA and a typical current limit of 115 mA. The regulator accepts
input voltages from 30V down to 10V. Because the regulator output is intended to supply external digital isolator
circuits proper output voltage decoupling is required. For best results connect a 1µF and a 0.1µF ceramic
capacitor as close as possible to the 5VOP-output. For longer traces between the SN65HVS881 and isolators of
the ISO72xx family use additional 0.1µF and 10pF capacitors next to the isolator supply pins. Make sure,
however, that the total load capacitance does not exceed 4.7µF.
For good stability the voltage regulator requires a minimum load current, IL-MIN. Ensure that under any operating
condition the ratio of the minimum load current in mA to the total load capacitance in µF is larger than 1:
I
1 mA
1 µF
L-MIN
>
C
L
Temperature Sensor
An on-chip temperature sensor monitors the device temperature and signals a fault condition if the internal
temperature reaches 150°C. If the internal temperature exceeds this trip point, the HOT output switches to an
active low state. If the internal temperature continues to rise, passing a second trip point at 170°C, all device
outputs are put in a high-impedance state.
A special condition occurs, however, when the chip temperature exceeds the second temperature trip point due
to an output short. Then the output buffer becomes 3-state, thus separating the buffer from the external circuitry.
An internal 100-kΩ pull-down resistor, connecting the HOT pin to ground, is used as a cooling down resistor,
which continues to provide a logic low level to the external circuitry.
Parity Generator
A parity bit is generated when one or more of the following conditions occur:
•
•
•
a change in input status
a change in Undervoltage status
a change in Overtemperature status
Upon the application of a load pulse the input status (IP0–IP7) and the diagnostic bits (HOT, UVO, and PAR) are
loaded parallel into the serializer assuming the following format:
Bit 11
Bit 1
PAR
UVO
HOT
PIP0
PIP1
PIP2
PIP3
PIP4
PIP5
PIP6
PIP7
Figure 16. Sequence of Status Bits in Serializer
12
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APPLICATION INFORMATION
System-Level EMC
The SN65HVS881 is designed to operate reliably in harsh industrial environments. At a system level, the device
is tested according to several international electromagnetic compatibility (EMC) standards. In addition to the
device internal ESD structures, external protection circuitry, as shown in Figure 17, can be used to absorb as
much energy from burst- and surge-transients as possible.
R
1
V
= 24V
V24
SUP
C
S
D
1
C
1
D
S
56 W, 1/3 W MELF Resistor
R1
D1
C1
33 V – 36 V fast Zener Diode, Z2SMB36
10 µF, 60 V Ceramic Capacitor
SN65HVS881
FE
0V
FGND
RIN 1.2 kW, 1/4 W MELF Resistor
R
IN
CIN 22 nF, 60 V Ceramic Capacitor
IPx
IP0 – IP7
CS
DS
D2
4.7 nF, 2 kV Polypropylene Capacitor
C
IN
39V Transient Voltage Suppressor: SM15T39CA
Super Rectifier: BYM10-1000, or
General Purpose rectifier: 1N4007
0V
FE
FGND
D
2
C
S
Figure 17. Typical EMC Protection Circuitry for Supply and Signal Inputs
Input Channel Switching for IEC61131-2 PLC Applications
The input stage of the SN65HVS881 is designed so that with a 24-V supply on VCC and an input resistor RIN
=
1.2 kΩ, the trip point for signaling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching
requirements of IEC61131-2 type-1 and type-3 switches.
Type 1
Type 2
Type 3
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
ON
ON
ON
OFF
OFF
15
OFF
0
0
0
-3
-3
-3
5
10
/ mA
15
5
10
5
10
/ mA
IN
15
20
25
30
I
I
/ mA
I
IN
IN
Figure 18. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a type-2 switch application two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (GND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
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SLAS642–MARCH 2009................................................................................................................................................................................................... www.ti.com
R
IN
R
IN
IP0
IP0
C
C
IN
IN
RE 0
RE0
R
R
IN
IN
IP1
IP1
C
C
IN
IN
RE1
RE1
Figure 19. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
Digital Interface Timing
The digital interface of the SN65HVS881 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard microcontrollers.
SN65HVS881
HOST
SIP
CONTROLLER
ISO7241
IP0
IP7
LD
CE
OUTA
OUTB
OUTC
IND
INA
INB
LOAD
STE
CLK
SOP
INC
SCLK
SOMI
OUTD
Figure 20. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, /LD, the information of the field inputs and the diagnostic bits are latched into
the shift register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A
low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial
output, SOP. Data is clocked at the rising edge of CLK. Thus after eleven consecutive clock cycles all data have
been clocked out of the shift register and the information of the serial input, SIP, appears at the serial output,
SOP.
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SN65HVS881
www.ti.com................................................................................................................................................................................................... SLAS642–MARCH 2009
CLK
CE
SIP
LD
high
PAR - PIP6
PIP7
don’t care
IP7
IP6 IP5 IP4 IP3 IP2 IP1 IP0
HOT UVO PAR SIP
SOP
inhibit
Serial shift
Figure 21. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Cascading for High Channel Count Input Modules
Designing high-channel count modules requires cascading multiple SN65HVS881 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
HOST
CONTROLLER
ISO7241
4 x SN65HVS881
OUTA
OUTB
OUTC
IND
INA
INB
LOAD
STE
INC
SCLK
SOMI
OUTD
SERIALIZER
SERIALIZER
SERIALIZER
SERIALIZER
Figure 22. Cascading Four SN65HVS881 for a 32-Channel Input Module
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Typical Digital Input Module Application
SM15T39CA
24 V
5 V
5 V-ISO
0 V-ISO
(Logic) 24V
1
SM15T39A
Isolated
(Sensors) 24V
4.7 nF
2 kV
2
DC / DC
4.7 nF
2 kV
GND2
GND1
0V
FE
Power
Supply
4.7 nF
2 kV
56 W MELF
Z2SMB36
10mF
60 V
1N4007
1
mF
0.1mF
SN65 HVS 881
5VOP
CHOK
SIP
V24
IP0
1.2 kW
MELF
ISO7242
HOST
CONTROLLER
VCC2
EN2
VCC1
22 nF
S0
VCC
RE0
EN1
INA
LOAD
SCLK
INT
LD
OUTA
OUTB
INC
CLK
CE
INB
1.2 kW
MELF
IP7
OUTC
OUTD
GND1
22 nF
S7
SOMI
DGND
SOP
DB0
DB1
RE7
IND
RLIM
FGND
GND2
24.9 kW
Figure 23. Typical Digital Input Module Application
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Product Folder Link(s): SN65HVS881
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65HVS881PWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
SN65HVS881PWPR
2000
Pack Materials-Page 2
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