SN65HVS883PWP [TI]
34V、8 通道数字输入串行器 | PWP | 28 | -40 to 85;
| 型号： | SN65HVS883PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 34V、8 通道数字输入串行器 | PWP | 28 | -40 to 85 |
| 文件： | 总28页 (文件大小：1346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
SN65HVS883 24V、八通道数字输入串行器
1 特性
施加负载和时钟信号时，输入数据将被并行锁存到移位
寄存器中，然后经过一个后置隔离器随时钟串行移出至
串行 PLC 输入。
1
•
八个传感器输入
–
–
输入电压最高达 34V
可选去抖动滤波器
从 0ms 至 3ms
通过将前面器件的串行输出连接到后面器件的串行输
入，可以将多个 SN65HVS883 级联在一起，从而实现
高通道数输入模块的设计。输入状态通过 3mA 恒流
LED 输出来显示。为设置内部基准电流，需要外接一
个精密电阻。集成的稳压器提供 5V 输出电压，为低功
耗隔离器供电。内部电源电压监视器提供芯片正常
(CHOK) 指示。
–
–
可调节电流限制
从 0.2mA 至 5.2mA
现场输入和电源线路
具有 15kV 人体模型 (HBM) 保护
•
•
•
•
•
用于外部状态 LED 的输出驱动器
支持多路输入级联（输入数为 8 的倍数）
与 SPI 兼容的接口
SN65HVS883 采用散热增强型 28 引脚 PWP
PowerPAD™封装。该器件的额定工作温度范围为
–40°C 至 85°C。
用于外部数字隔离器的 5V 稳压输出
低电源电压指示灯
器件信息(1)
2 应用
器件型号
封装
封装尺寸（标称值）
•
用于工业自动化和过程控制的传感器输入
SN65HVS883
HTSSOP (28)
9.70 mm x 4.40 mm
–
符合 IEC61131-2 标准 1 类、2 类或 3 类的开
关
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
–
符合 EN60947-5-2 标准的接近开关
简化的 I/O 结构
•
•
用于 PC 和可编程逻辑控制器 (PLC) 系统的高通道
数数字输入模块
Voltage
24 V In
5 V Out
分立式 I/O 模块
Regulator
2
Debounce Select
DB0:DB1
Serial Input
5 V
3 说明
3
Control Inputs
LD, CE, CLK
SN65HVS883 是一款用于工业自动化 PC 和 PLC 系
统中高通道数的数字输入模块的 24V、八通道数字输
入串行器。与电流隔离器配合使用时，此器件可将现场
侧的 24V 传感器输出连接到控制侧的低压控制器输
入。输入信号由符合 EN60947-5-2 标准的 2 线和 3 线
接近开关提供
Field Inputs
IP0:IP7
8
8
8
LED Outputs
RE0:RE7
I
Adj: R
LIM
Field Ground
Serial Output
REF
并进行电流限制，然后由内部去抖动滤波器进行验证。
输入开关特性符合 IEC61131-2 标准关于 1 类、2 类和
3 类传感器开关的特性描述。
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASEE6
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
目录
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions...................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 6
6.8 Typical Input Characteristics..................................... 7
9
10 Power Supply Recommendations ..................... 21
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 器件和文档支持 ..................................................... 22
12.1 Third-Party Products Disclaimer ........................... 22
12.2 接收文档更新通知 ................................................. 22
12.3 社区资源................................................................ 22
12.4 商标....................................................................... 22
12.5 静电放电警告......................................................... 22
12.6 Glossary................................................................ 22
13 机械、封装和可订购信息....................................... 22
6.9 Typical Voltage Regulator Performance
Characteristics ........................................................... 8
7
8
Parameter Measurement Information .................. 9
7.1 Waveforms................................................................ 9
7.2 Signal Conventions ................................................... 9
Detailed Description ............................................ 10
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2016 年 9 月
*
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
5 Pin Configuration and Functions
PWP Package
28 Pin (HTSSOP) With Exposed Thermal Pad
Top View
DB0
DB1
IP0
1
28
27
26
25
24
23
FGND
SIP
2
3
LD
RE0
IP1
4
CLK
CE
5
RE1
IP2
6
SOP
IP7
7
22
Thermal
Pad
RE2
IP3
8
21
20
19
18
17
16
15
RE7
IP6
9
RE3
IP4
10
11
12
13
14
RE6
IP5
RE4
RLIM
V24
RE5
CHOK
5VOP
Not to scale
Pin Functions
PIN
DESCRIPTION
PIN NO.
1, 2
NAME
DB0, DB1
Debounce select inputs
Input channel x
3, 5, 7, 9,
11, 18, 20, 22
IPx
4, 6, 8, 10,
12, 17, 19, 21
REx
Return path x (LED drive)
13
14
15
16
23
24
25
26
27
28
RLIM
V24
Current limiting resistor
24 VDC field supply
5VOP
CHOK
SOP
CE
5 V output to supply low-power isolators
Chip okay indicator output
Serial data output
Clock enable input
CLK
LD
Serial clock input
Load pulse input
SIP
Serial data input
FGND
Field ground
Copyright © 2016, Texas Instruments Incorporated
3
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.5
MAX
UNIT
V
V24
VIPx
VID
IO
Field power input
V24
36
36
6
Field digital inputs
IPx
V
Voltage at any logic input
Output current
DB0, DB1, CLK, SIP, CE, LD
CHOK, SOP
V
±8
mA
PTOT
TJ
Continuous total power dissipation
Junction temperature
See Thermal Information table
170
°C
6.2 ESD Ratings
VALUE
±4000
UNIT
All pins
IPx,V24
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
001(1)
±15000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)
Machine Mode(3)
All pins
All pins
±1000
±100
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) JEDEC Standard 22, Method A115-A.
6.3 Recommended Operating Conditions
MIN
10
0
TYP
MAX
34
UNIT
V24
VIPL
VIPH
VIL
Field supply voltage
24
V
V
Field input low-state input voltage(1)
Field input high-state input voltage(1)
Logic low-state input voltage
Logic high-state input voltage
Current limiter resistor
4
10
0
34
V
0.8
5.5
500
1
V
VIH
RLIM
fIP
2
V
17
0
25
kΩ
Mbps
°C
°C
Input data rate(2)
TJ
150
85
TA
–40
(1) Field input voltages correspond to an input resistor of RIN = 1.2 kΩ
(2) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = FGND), and RIN = 0 Ω
6.4 Thermal Information
SN65HVS883
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
28 PINS
35
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
4.27
15
ILOAD = 50 mA, RIN = 0, IPO–IP7 = V24 = 30 V,
PD
Device power dissipation
RE7 = FGND, fCLK = 100 MHz,
2591
mW
IIP-LIM and ICC = worst case with RLIM = 25 kΩ
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
6.5 Electrical Characteristics
all voltages measured against FGND unless otherwise stated, see Figure 12
SYMBOL
VTH–(IP)
VTH+(IP)
VHYS(IP)
VTH–(IN)
VTH+(IN)
VHYS(IN)
PARAMETER
Low-level device input threshold voltage
High-level device input threshold voltage
Device input hysteresis
PIN
TEST CONDITIONS
MIN
TYP
4.3
5.2
0.9
8.4
9.4
1
MAX UNIT
4
V
18 V< V24 < 34 V,
RIN = 0 Ω ,
RLIM = 25 kΩ
5.5
10
V
V
V
V
V
V
V
V
IP0–IP7
Low-level field input threshold voltage
High-level field input threshold voltage
Field input hysteresis
6
18 V < V24 < 34 V,
RIN = 1.2 kΩ ± 5%,
RLIM = 25 kΩ
measured at
field side of RIN
VTH–(V24) Low-level V24-monitor threshold voltage
VTH+(V24) High-level V24-monitor threshold voltage
VHYS(V24) V24-monitor hysteresis
15 16.05
16.8
V24
18
0.75
3 V < VIPx < 6 V,
RIN = 1.2 kΩ ± 5%,
RLIM = 25 kΩ
RIP
Input resistance
1.4
1.83
3.6
2.3
kΩ
IP0–IP7
10 V < VIPx < 34 V,
RLIM = 25 kΩ
IIP-LIM
Input current limit
3.15
4
mA
VOL
VOH
Logic low-level output voltage
Logic high-level output voltage
IOL = 20 μA
0.4
V
V
SOP, CHOK
IOH = –20 μA
4
DB0, DB1, SIP,
LD, CE, CLK
IIL
Logic input leakage current
RE on-state current
–50
50
μA
RLIM = 25 kΩ,
REX = FGND
IRE-on
RE0–RE7
2.8
3.15
3.5
mA
IP0 to IP7 = V24,
5VOP = open,
REX = FGND,
ICC(V24)
Supply current
V24
8.7
mA
V
All logic inputs open
18 V < V24 < 34 V,
no load
4.5
4.5
5
5.5
5.5
VO(5V)
Linear regulator output voltage
5VOP
18 V < V24 < 34 V,
IL = 50 mA
5
ILIM(5V)
Linear regulator output current limit
115
mA
18 V < V24 < 34 V,
IL = 5 mA
ΔV5/ΔV24 Line regulation
5VOP, V24
IP0–IP7
2
mV/V
DB0 = open,
DB1 = FGND
0
tDB
Debounce times of input channels
DB0 = FGND,
DB1 = open
ms
ms
1
3
1
DB0 = DB1 = open
Voltage monitor debounce time after V24 < 15
V (CHOK turns low)
tDB-HL
V24, CHOK
Voltage monitor debounce time after V24 > 18
V (CHOK turns high)
tDB-LH
TSHDN
6
ms
°C
Shutdown temperature
170
Copyright © 2016, Texas Instruments Incorporated
5
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted)
SYMBOL
tW1
PARAMETER
MIN
4
TYP
MAX UNIT
CLK pulse width
See Figure 9
See Figure 7
See Figure 10
See Figure 10
See Figure 11
See Figure 8
See Figure 9
ns
ns
ns
ns
ns
ns
tW2
LD pulse width
6
tSU1
tH1
SIP to CLK setup time
SIP to CLK hold time
4
2
tSU2
tREC
fCLK
Falling edge to rising edge (CE to CLK) setup time
LD to CLK recovery time
4
2
Clock pulse frequency (50% duty cycle)
DC
100
MHz
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
SYMBOL
tPLH1, tPHL1
tPLH2, tPHL2
tr, tf
PARAMETER
CLK to SOP
TEST CONDITIONS
CL = 15 pF, see Figure 9
CL = 15 pF, see Figure 7
CL = 15 pF, see Figure 9
MIN
TYP
MAX
UNIT
ns
10
14
5
LD to SOP
ns
Rise and fall times
ns
6
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
6.8 Typical Input Characteristics
30
25
20
15
10
5
a)
b)
c)
Off
On
Field Input Thresholds
0
0
0.5
1.0
1.5
2.0
I
2.5
(mA)
3.0
3.5
4.0
IN
RIN = 1.2 kΩ
a) IIP-LIM = 2.5 mA (RLIM = 36.1 kΩ)
b) IIP-LIM = 3.0 mA (RLIM = 30.1 kΩ)
c) IIP-LIM = 3.6 mA (RLIM = 24.9 kΩ)
Figure 1. Typical Input Characteristics
102.0
101.5
101.0
100.5
100.0
99.5
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
V
TH+(IN)
99.0
V
TH–(IN)
98.5
98.0
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95
(ºC)
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95
(ºC)
T
A
T
A
V24 = 24 V
VIN = 24 V
RIN = 1.2 kΩ
V24 = 24 V
RIN = 1.2 kΩ
RLIM = 24.9 kΩ
RLIM = 24.9 kΩ
Figure 2. Typical Current Limiter Variation vs Ambient
Temperature
Figure 3. Typical Limiter Threshold Voltage Variation vs
Ambient Temperature
Copyright © 2016, Texas Instruments Incorporated
7
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
6.9 Typical Voltage Regulator Performance Characteristics
6
5.000
4
2
4.995
4.990
4.985
4.980
4.975
4.970
4.965
4.960
0
–2
–4
–6
–8
–10
0
5
10
15
V
20
(V)
25
30
35
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95
T
(°C)
A
IN
ILOAD = 0 mA
ILOAD = 5 mA
TA = 27°C
Figure 5. Output Voltage vs Ambient Temperature
Figure 4. Line Regulation
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
5
10
15
20
25
30
35
V
(V)
IN
RLOAD = 100 Ω
Figure 6. Output Voltage vs Input Voltage
8
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
7 Parameter Measurement Information
7.1 Waveforms
For the complete serial interface timing, refer to Figure 21.
tw2
LD
LD
tREC
tPLH2
tPHL2
CLK
SOP
Figure 7. Parallel – Load Mode
Figure 8. Serial – Shift Mode
valid
1/fCLK
t
w1
SIP
CLK
tSU 1
tH1
t
PHL1
t
PLH1
CLK
SOP
t
r
Figure 9. Serial – Shift Mode
Figure 10. Serial – Shift Mode
CLK
tSU2
CE
CLK inhibited
Figure 11. Serial – Shift Clock Inhibit Mode
7.2 Signal Conventions
R
IN
IPx
I
IN
SN65HVS883
V
V
TH(IN)
TH(IP)
FGND
Copyright © 2016, Texas Instruments Incorporated
Figure 12. On/Off Threshold Voltage Measurements
Copyright © 2016, Texas Instruments Incorporated
9
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
8 Detailed Description
8.1 Overview
The SN65HVS883 is an 8 channel, digital input serializer which operates from a 24 V supply and accepts digital
inputs of up to 34 V on the 8 channels (IP0-IP7). The device provides a serially shifted digital output with reduced
voltage ranges of 0-5 V for applications in industrial and building automation systems. The SN65HVS883 meets
JEDEC standards for ESD protection (refer to ESD Ratings), and is SPI compatible for interfacing with standard
microcontrollers. The serializer operates in 2 fundamental modes: Load Mode and Shift mode. In Load mode,
information from the field inputs is allowed to latch into the shift register. In Shift mode, the information stored in
the parallel shift register can be serially shifted to the serial output (SOP). A detailed description of the functional
modes is available in the Device Functional Modes section.
8.2 Functional Block Diagram
Voltage
Regulator
5VOP
V24
5V
Supply
CHOK
Monitor
FGND
DB0
DB1
Adj. Current
Thresholds
Debounce
Select
RLIM
SIP
RE0
IP0
Current
Sense
Debounce
Filter
&
LD
Voltage
Sense
CE
Channel 0
CLK
RE7
IP7
Channel 7
SOP
Copyright © 2016, Texas Instruments Incorporated
10
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
8.3 Feature Description
8.3.1 Digital Inputs
Each digital input operates as a controlled current sink limiting the input current to a maximum value of ILIM. The
current limit is derived from the reference current via ILIM = n × IREF, and IREF is determined by IREF = VREF/RLIM
Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/ILIM
.
.
Inserting the actual values for n and VREF gives: RLIM = 90 V / ILIM
.
While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ), it is easy to lower the current limit
to further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate:
90 V
90 V
RLIM
=
=
= 36 kΩ
ILIM
2.5 mA
(1)
1.25 V
REF
5 V
I
Mirror
LIM
n = 72
I
IN
IPx
I
I
REF
LIM
Limiter
= I
R
LIM
I
INmax
LIM
Figure 13. Digital Input Stage
8.3.2 Debounce Filter
The HVS883 applies a simple analog/digital filtering technique to remove unintended signal transitions due to
contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration
of the selected debounce time to be latched into the shift register as a valid state.
The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the
different debounce times listed in the following truth table.
Table 1. Debounce Times
DB1
Open
Open
DB0
Open
FGND
FUNCTION
3 ms delay
1 ms delay
0 ms delay
(Filter bypassed)
FGND
FGND
Open
FGND
Reserved
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ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
5 V
IPx
REF
REx
R
LIM
FGND
Figure 14. Equivalent Input Diagram
8.3.3 Shift Register
The conversion from parallel input to serial output data is performed by an eight-channel, parallel-in serial-out
shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7, that are enabled by a low level at
the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register
also provides a clock-enable function.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock
enable (CE) input is held low for all registers in the shift register except the last register which is latched by a
high-to-low transition. Parallel loading is inhibited when LD is held high. The parallel inputs to the register are
enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.
SIP
SOP
D
D
D
D
D
D
D
D
D
Q
S
Q
S
Q
S
Q
S
Q
S
Q
S
Q
S
Q
Q
S
CLK
CE
Logic
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
CP
R
LD
PIP 0
PIP 1
PIP 2
PIP 3
PIP 4
PIP 5
PIP 6
PIP 7
Figure 15. Shift Register Logic Structure
12
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SN65HVS883
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ZHCSFI0 –SEPTEMBER 2016
Table 2. Function Table
INPUTS
FUNCTION
LD
L
CLK
CE
X
X
X
↑
Parallel load
No change
Shift(1)
H
H
L
H
H
↓
L
Shift(2)
(1) Shift = content of each internal register, except the last register, shifts towards serial output.
(2) Shift = content of the last register shifts towards serial output.
8.3.4 Voltage Regulator
The on-chip linear voltage regulator provides a 5 V supply to the internal- and external circuitry, such as digital
isolators, with an output drive capability of 50 mA and a typical current limit of 115 mA. The regulator accepts
input voltages from 34 V down to 10 V. Because the regulator output is intended to supply external digital isolator
circuits proper output voltage decoupling is required. For best results connect a 1 μF and a 0.1 μF ceramic
capacitor as close as possible to the 5VOP-output. For longer traces between the SN65HVS883 and isolators of
the ISO72xx family use additional 0.1 μF and 10 pF capacitors next to the isolator supply pins. Make sure,
however, that the total load capacitance does not exceed 4.7 μF.
For good stability the voltage regulator requires a minimum load current, IL-MIN. Ensure that under any operating
condition the ratio of the minimum load current in mA to the total load capacitance in μF is larger than 1:
I
1 mA
1 µF
L-MIN
>
C
L
(2)
8.3.5 Supply Voltage Monitor
The integrated supply voltage monitor senses the supply voltage of the SN65HVS883 at the V24-pin. If this
voltage drops below 15 V but stays within the regulator’s operating range, i.e., 15 V > V24 > 10 V, the output
CHOK goes low 1 ms later. When the supply voltage returns to 24 V, the CHOK output turns logic high after
6 ms. Should the supply voltage drop below 10 V, the device ceases operation. Upon the supply returning to
above 18 V, the CHOK output turns high again after 6 ms.
18 V
18 V
15 V
15 V
10 V
V24 < 10 V
V24
15 V > V24 > 10 V
1 ms
debounce
time starts
1 ms
debounce
time starts
t
t
DB-LH
t
DB-LH
DB-HL
Circuit ceases
operation
CHOK
Figure 16. CHOK Output Timing as a Function of Supply Voltage Drop at V24
Copyright © 2016, Texas Instruments Incorporated
13
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ZHCSFI0 –SEPTEMBER 2016
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8.4 Device Functional Modes
The 2 functional modes of operation are Load mode and Shift mode.
Load mode enables information from the field inputs to latch into the shift register. To enter load mode, the LD
pin must be held low, and the device remains in load mode regardless of the CLK, CE, or serial (SIP) input
levels. A high level at the LD pin switches the device into Shift mode.
When the device is in Shift mode, a low level at the CE pin causes the data stored in all registers of the parallel
shift register except for the last register, to be serially shifted toward the serial output (SOP) on the rising edge of
CLK. The final register in the shift register will be shifted toward the serial output (SOP) on the falling edge of
CLK. A high level at the CE pin inhibits the serial shifting, which is demonstrated in Figure 21. After 8
consecutive CLK cycles, the serial output (SOP) remains at the level of the serial input (SIP) which is internally
pulled to logic high. A logic high at the CE pin is required to signify the end of the serial data output. For of a
daisy chained configuration, the serial output (SOP) of the SN65HVS883 can be connected to the serial input
(SIP) of a following device, and additional clock cycles are required to shift the additional data out of the chain.
The number of consecutive clock cycles will equal 8 times the number of devices in the chain. See Figure 22 for
an example of a cascaded chain of 4x SN65HVS883.
14
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
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ZHCSFI0 –SEPTEMBER 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 System-Level EMC
The SN65HVS883 must operate reliably in harsh industrial environments. At a system level, the device is tested
according to several international electromagnetic compatibility (EMC) standards.
In addition to the device internal ESD structures, external protection circuitry, such as the one in Figure 17, can
be used to absorb as much energy from burst- and surge-transients as possible.
C
C
R
D
RP
S
V
SUP
= 24 V
V24
D
D
Z
C
TS
C
C
C
C
HV
C
B
SN65HVS883
R
IN
INx
IP0 – IP7
FGND
C
IN
0 V
C
HV
FE
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Typical EMC Protection Circuitry for Supply and Signal Inputs
Table 3. Components
DESIGNATOR
DESCRIPTION
DTS
39 V Transient Voltage Suppressor: SM15T39CA
Super Rectifier: BYM10-1000,
or General Purpose rectifier: 1N4007
DRP
DZ
RS
33 V – 36 V fast Zener Diode, Z2SMB36
56 Ω, 1/3 W MELF Resistor
RIN
CIN
CHV
CC
1.2 kΩ, 1/4 W MELF Resistor
22 nF, 60 V Ceramic Capacitor
4.7 nF, 2 kV Ceramic Capacitor
n x 220 nF, 60 V Ceramic Capacitors
1 µF - 10 µF, 60 V Ceramic Capacitor
CB
Copyright © 2016, Texas Instruments Incorporated
15
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
9.1.2 Input Channel Switching Characteristics
The input stage of the SN65HVS883 is so designed, that for an input resistor RIN = 1.2 kΩ the trip point for
signalling an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching requirements of IEC61131-
2 Type 1 and Type 3 switches.
Type 1
Type 2
Type 3
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
ON
ON
ON
OFF
10
OFF
15
OFF
0
–3-
0
–3
0
–3
5
15
5
10
20
(mA)
25
30
5
10
(mA)
15
0
0
0
I
(mA)
I
IN
I
IN
IN
Figure 18. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a Type 2 switch application, two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (FGND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
R
R
IN
IN
IN0
IN0
IP0
IP0
C
C
IN
IN
RE0
RE0
R
R
IN
IN
IN1
IP1
IP1
C
C
IN
IN
RE1
RE1
Figure 19. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
16
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SN65HVS883
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ZHCSFI0 –SEPTEMBER 2016
9.1.3 Digital Interface Timing
The digital interface of the SN65HVS883 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard micro controllers.
SN65HVS883
HOST
SIP
ISO7241
CONTROLLER
IP0
IP7
LD
CE
OUTA
OUTB
OUTC
IND
INA
INB
LOAD
STE
CLK
SOP
INC
SCLK
SOMI
OUTD
Figure 20. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift
register. Taking LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at
the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data
is clocked into the shift register at the rising edge of CLK and out of the shift register on the falling edge of CLK.
Thus after eight consecutive clock cycles all field input data have been clocked out of the shift register and the
information of the serial input, SIP, appears at the serial output, SOP.
The CE signal should only be transitioned low while the CLK signal is low which ensures that a rising edge of
CLK occurs before a falling edge of CLK. This shifts the data into and through the shift register up until the final
register before the first bit that was loaded into the final register is shifted out the serial output, SOP. If a falling
edge of CLK is seen first following the transition of CE to low, the final register outputs the first bit, IP0, on the
serial output, SOP, before shifting the rest of the bits through the shift register. The previous value of the second
to last register prior to the LD event will then be shifted into the final register on the next rising CLK edge and
output on the serial output, SOP, before the next valid bit, IP1, is output on the serial output, SOP. This appears
as an erroneous bit in the serial data. Also, depending on how many falling CLK edges were seen before the CE
signal is transitioned back high, the final bit, IP7, may not get shifted out of the shift register.
CLK
CE
SIP
high
LD
PIP0-PIP6
PIP7
SOP
IP7
Inhibit
IP6
IP5
IP4
IP3
IP2
IP1
IP0
SIP
don’t care
Serial shift
Figure 21. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Copyright © 2016, Texas Instruments Incorporated
17
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
9.1.4 Cascading for High Channel Count Input Modules
Designing high-channel count modules require cascading multiple SN65HVS883 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
HOST
ISO7241
CONTROLLER
4 X SN65HVS883
OUTA
OUTB
OUTC
IND
INA
INB
LOAD
STE
INC
SCLK
SOMI
OUTD
SERIALIZER
SERIALIZER
SERIALIZER
SERIALIZER
Figure 22. Cascading Four SN65HVS883 for a 32-Channel Input Module
NOTE
When daisy-chaining multiple devices, the maximum operating rate (CLK pulse width) may
need to be restricted in order to maintain minimum set-up/hold timing relationships
between the serial data (SIP/SOP) and the CLK line.
9.2 Typical Application
SM15T39CA
24 V
5 V
5 V-ISO
(Logic) 24 V1
SM15T39A
4.7 nF
2 kV
Isolated
DC / DC
(Sensors) 24 V2
4.7 nF
2 kV
220 nF
100 V
220 nF
100 V
Power
Supply
GND2
GND1
0 V
0 V-ISO
4.7 nF
2 kV
56 Ω
MELF
FE
220 nF
100 V
BYM10-1000
Z2SMB36
2.2 mF
60 V
1 mF
0.1 mF
SN65HVS883
V24
5VOP
CE
1.2 kW
MELF
220 nF
60 V
ISO7242
VCC2
HOST
IP0
VCC1
CONTROLLER
22 nF
100 V
S0
RE0
SIP
EN2
EN1
INA
VCC
LD
OUTA
OUTB
INC
LOAD
SCLK
INT
CLK
CHOK
SOP
DB0
DB1
INB
1.2 kW
MELF
IP7
OUTC
OUTD
GND1
22 nF
100 V
S7
RE7
IND
MISO
DGND
RLIM
FGND
GND2
24.9 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Typical Digital Input Module Application
18
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
Typical Application (continued)
9.2.1 Design Requirements
The simplified schematic in Figure 23 demonstrates a typical application of the SN65HVS883 for sensing the
state of digital switches with 24-V high logic levels. In this application, a 5-V host controller must receive the state
of 8 switches as a serial input, while remaining isolated from the high voltage power supply.
9.2.2 Detailed Design Procedure
9.2.2.1 Input Stage
Selection of the current limiting resistor RLIM sets the input current limit ILIM for the device. Digital Inputs includes
necessary equations for choosing the limiting resistor.
The On/Off voltage thresholds at the device pin VTH(IP+) and VTH(IP-) are fixed to 5.2 V and 4.3 V respectively,
however the On/Off voltage thresholds of the field input VTH(IN+) and VTH(IN-) are determined by the value of the
series resistor RIN placed between the field input and the device. The threshold voltage VTH(IN+) is determined
with the following equation:
VTH(IN+) = IIN ´RIN + VTH(IP+)
(3)
Substituting Equation 1 and solving for RIN produces an equation for RIN given a desired on-threshold.
(VTH(IN+) -5.2V)´RLIM
RIN =
90V
(4)
(5)
The following equation can be used to calculate the off-threshold voltage given a value for RIN
90V´RIN
VTH(IN-)
=
+ VTH(IP-)
RLIM
Figure 24 contains an example input characteristic:
30
25
20
15
10
ON = 8.2V
OFF = 7.3V
5
0
0
0.5
1
1.5
(mA)
2
2.5
3
I
IN
Figure 24. SN65HVS883 Example Input Characteristic
Copyright © 2016, Texas Instruments Incorporated
19
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
Typical Application (continued)
9.2.2.2 Setting Debounce Time
The logic signals at the DB0 and DB1 pins determine the denounce times for the device according to the table in
section 6.5. The DB0 and DB1 pins are internally pulled high. Connecting the pins to GND in different
configurations allows for selection of 0, 1, or 3 ms debounce times. In noisy environments, it is recommended
that unused DB pins should be connected externally to a 5 V supply.
9.2.2.3 Example: High-Voltage Sensing Application
For the high-voltage sensing application in Figure 23, inputs from each switch (S0-S7) are connected to the 8
parallel inputs (IP0-IP7) of the SN65HVS883 through 1.2 kΩ MELF resistors. Small capacitors (22 nF) are tied to
ground at each input to provide noise protection for the signals. A resistor is added between the RLIM pin and
GND to provide a device current limit according to the equation ILIM = 90 V / RLIM. In this example, with a 24.9 kΩ
resistor, the current limit for the device is set to 3.6 mA. LEDs are placed between pins RE0-RE7 to allow for
external status observation of the parallel inputs. Finally the SN65HVS883 is connected through a digital isolation
device to the host controller to provide galvanic isolation to the external interfaces and to allow for
communication between the 5 V SN65HVS883 logic and the 5-V host controller. The host controller manages
mode switching and clocking of the SN65HVS883 through the digital isolation device.
9.2.3 Application Curve
The application traces acquired in Figure 25 demonstrates the typical behavior of the SN65HVD883 when in shift
mode (Load Pulse Input pulled high and Clock Enable Input pulled low). Channel 1 shows the SIP input, Channel
2 shows the CLK input, and Channel 3 shows the SOP output.
500 ns/div
Figure 25. SN65HVS883 Serial Input and Output Timing
20
Copyright © 2016, Texas Instruments Incorporated
SN65HVS883
www.ti.com.cn
ZHCSFI0 –SEPTEMBER 2016
10 Power Supply Recommendations
The SN65HVS883 operates within a recommended supply voltage range from 4.5 V to 5.5 V. A 0.1 µF or larger
capacitor should be placed between VCC and ground to improve power supply noise immunity. A current limiting
resistor can be used to reduce overall power consumption as described in Digital Inputs. The high voltage
parallel field inputs can accept voltages ranging from 0 V to 34 V, however all other inputs must remain between
0 V to 5 V. Refer to the Recommended Operating Conditions table for more detailed voltage suggestions. High
voltage field inputs should be buffered as shown in Figure 23 to improve input noise immunity.
11 Layout
11.1 Layout Guidelines
1. Place series MELF resistors between the field inputs and the device input pins.
2. Place small ~22 nF capacitors close to the field input pins to reduce noise.
3. Place a supply buffering 0.1-µF capacitor around as close to the VCC pin as possible.
11.2 Layout Example
1
R
2
C
R
R
R
C
C
C
High
{b65Iëꢀ883
Voltage
Parallel
Inputs
Isolator
MCU
R
R
R
R
C
C
C
C
R
C
C
3
Isolated
DC-DC
Via to ground
Via to VCC 5V
Via to VCC 24V
版权 © 2016, Texas Instruments Incorporated
21
SN65HVS883
ZHCSFI0 –SEPTEMBER 2016
www.ti.com.cn
12 器件和文档支持
12.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
29-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65HVS883PWP
SN65HVS883PWPR
NRND
HTSSOP
HTSSOP
PWP
PWP
28
28
50
RoHS & Green
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
HVS883
HVS883
ACTIVE
2000 RoHS & Green
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
PWP 28
4.4 x 9.7, 0.65 mm pitch
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/B
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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