SN65HVS885_15 [TI]
34-V Digital-Input Serializer;
| 型号： | SN65HVS885_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 34-V Digital-Input Serializer |
| 文件： | 总21页 (文件大小：828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Typical Size
6.4 mm X 9.7 mm
SN65HVS885
www.ti.com ............................................................................................................................................................................................... SLAS638–JANUARY 2009
34 V, Digital-Input Serializer for 5V Systems
1
FEATURES
2
•
Eight Digital Sensor Inputs
•
•
SPI-Compatible Interface
–
–
High Input Voltage up to 34 V
Over-Temperature Indicator
Selectable Debounce Filters From 0 ms to
3 ms
APPLICATIONS
•
•
•
•
Industrial PCs
Digital I/O Cards
High Channel Count Digital Input Modules
Decentralized I/O Modules
–
–
Flexible Input Current-Limited – 0.2 mA to
5.2 mA
Field Inputs Protected to 15-kV ESD
•
•
•
Single 5V Supply
Output Drivers for External Status LEDs
Cascadable for More Inputs in Multiples of
Eight
DESCRIPTION
The SN65HVS885 is an eight channel, digital-input serializer for high-channel density digital input modules in
industrial and building automation. Operating from a 5V supply the device accepts field input voltages of up to
34V. In combination with galvanic isolators the device completes the interface between the high voltage signals
on the field-side and the low-voltage signals on the controller side. Inputs signals are current limited and then
validated by internal debounce filters.
With the addition of few external components, the input switching characteristic can be configured in accordance
with IEC61131-2 for Type 1, 2 and 3 sensor switches.
Upon the application of load and clock signals, input data is latched in parallel into the shift register and
afterwards clocked out serially.
Cascading of multiple devices is possible by connecting the serial output of the leading device with the serial
input of the following device, enabling the design of high-channel count input modules. Multiple devices can be
cascaded through a single serial port, reducing both the isolation channels and controller inputs required.
Input status can be visually indicated via constant current LED outputs. The current limit on the inputs is set by a
single, external, precision resistor. An on-chip temperature sensor provides diagnostic information for graceful
shutdown and system safety.
The SN65HVS885 is available in a 28-pin PWP PowerPAD™ package, allowing for efficient heat dissipation. The
device is specified for operation at temperatures from –40°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
SN65HVS885
SLAS638–JANUARY 2009............................................................................................................................................................................................... www.ti.com
DB0
DB1
IP0
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
SIP
2
Debounce Select
DB 0:1
2
Serial Input
3
LD
RE0
IP1
4
CLK
CE
5
Field Inputs
IP 0:7
8
3
Control Inp[uts
LD, CE, CLK
RE1
IP2
6
SOP
IP7
7
8
GND
RE2
IP3
8
RE7
IP6
VCC
9
LED Outputs
RE 0:7
8
RE3
IP4
10
11
12
13
14
RE6
IP5
IREF Adjust:
RLIM
RE4
RLIM
NC
RE5
HOT
VCC
Serial Output
FUNCTIONAL BLOCK DIAGRAM
Vcc
HOT
DB0
DB1
Adj. Current
Thresholds
Thermal
Protection
Debounce
Select
RLIM
SIP
RE0
IP0
Current
Sense
Debounce
Filter
&
LD
Voltage
Sense
CE
Channel 0
CLK
GND
RE7
IP7
Channel 7
SOP
2
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TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
PIN NO.
NAME
1, 2
DB0, DB1
Debounce select inputs
Input Channel x
3, 5, 7, 9,
11, 18, 20, 22
IPx
4, 6, 8, 10,
12, 17, 19, 21
REx
Return Path x (LED drive)
13
14
15
16
23
24
25
26
27
28
RLIM
NC
Current Limiting Resistor
Not Connected
VCC
HOT
SOP
CE
5 V Device Supply
Over-Temperature Flag
Serial Data Output
Clock Enable Input
Serial Clock Input
Load Pulse Input
Serial Data Input
CLK
LD
SIP
GND
Device Ground
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
UNIT
V
VCC
VIPx
VID
IO
Device power input
Field digital inputs
Voltage at any logic input
Output current
VCC
–0.5 to 6
IPx
–0.3 to 36
V
DB0, DB1, CLK, SIP, CE, LD
–0.5 to 6
V
HOT, SOP
All pins
IPx
±8
mA
±4
Human-Body Model(2)
kV
±15
VESD
Electrostatic discharge
Charged-Device Model(3) All pins
Machine Model(4)
All pins
±1
kV
V
±100
See Thermal Characteristics table
170
PTOT
TJ
Continuous total power dissipation
Junction temperature
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) JEDEC Standard 22, Method A114-A.
(3) JEDEC Standard 22, Method C101
(4) JEDEC Standard 22, Method A115-A
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
High-K thermal resistance
MIN
TYP
35
MAX
UNIT
°C/W
°C/W
°C/W
θJA
θJB
θJC
Junction-to-air thermal resistance
Junction-to-board thermal resistance
Junction-to-case thermal resistance
15
4.27
VCC = 5 V, RIN = 0Ω,
RLIM = 25 kΩ,
RE0 – RE7 = GND,
fCLK = 100 MHz
IP0-IP7 = 34V
IP0-IP7 = 30V
IP0-IP7 = 24V
IP0-IP7 = 12V
PD
Device power dissipation
1100
mW
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
0
TYP
MAX
UNIT
VCC
VIPL
VIPH
VIL
Device supply voltage
Field input low-state input voltage
Field input high-state input voltage
Logic low-state input voltage
Logic high-state input voltage
Current limiter resistor
Input data rate
5
5.5
4
V
V
5.5
0
34
V
0.8
5.5
500
1
V
VIH
2.0
17
0
V
RLIM
25
kΩ
Mbps
°C
°C
(1)
fIP
TA
TJ
Device
–40
125
150
(1) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and RIN = 0 Ω
4
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ELECTRICAL CHARACTERISTICS
over full-range of recommended operating conditions (unless otherwise noted)
all voltages measured against device ground, see Figure 9
PARAMETER
TERMINAL
TEST CONDITIONS
MIN TYP MAX
UNIT
FIELD INPUTS
VTH–(IP)
VTH+(IP)
VHYS(IP)
VTH–(IN)
VTH+(IN)
VHYS(IN)
Low-level device input threshold voltage
High-level device input threshold voltage
Device input hysteresis
4.0
6
4.3
5.2
0.9
8.4
9.4
1
V
V
V
V
V
V
IP0–IP7
RLIM = 25 kΩ
5.5
10
Low-level field input threshold voltage
High-level field input threshold voltage
Field input hysteresis
4.5 V < VCC < 5.5 V,
RIN = 1.2 kΩ ± 5%,
RLIM = 25 kΩ, TA ≤ 125°C
measured at
field side of RIN
3 V < VIPx < 6 V,
RLIM = 25 kΩ
RIP
Input resistance
Input current limit
IP0–IP7
IP0–IP7
0.2 0.63
1.1
4
kΩ
IIP-LIM
RLIM = 25 kΩ
3.15
3.6
mA
DB0 = open, DB1 = GND
DB0 = GND, DB1 = open
DB0 = DB1 = open
0
tDB
Debounce times of input channels
RE on-state current
IP0–IP7
1
3
ms
IRE-on
RE0–RE7
RLIM = 25 kΩ, REX = GND
2.8 3.15
3.5
10
mA
DEVICE SUPPLY
IP0 to IP7 = 24V, REX = GND,
All logic inputs open
ICC(VCC)
Supply current
VCC
6.5
mA
LOGIC INPUTS AND OUTPUTS
VOL
VOH
Logic low-level output voltage
IOL = 20 µA
0.4
50
V
V
SOP, HOT
Logic high-level output voltage
IOH = –20 µA
4
DB0, DB1, SIP,
LD, CE, CLK
IIL
Logic input leakage current
–50
µA
TOVER
TSHDN
Over-temperature indication
Shutdown temperature
150
170
°C
°C
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
4
TYP MAX UNIT
tW1
CLK pulse width
See Figure 6
ns
ns
ns
ns
ns
ns
tW2
LD pulse width
See Figure 4
See Figure 7
See Figure 7
6
tSU1
tH1
SIP to CLK setup time
SIP to CLK hold time
4
2
tSU2
tREC
fCLK
Falling edge to rising edge (CE to CLK) setup time See Figure 8
4
LD to CLK recovery time
Clock pulse frequency
See Figure 5
See Figure 6
2
DC
100
MHz
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
ns
tPLH1, tPHL1
tPLH2, tPHL2
tr, tf
CLK to SOP
CL = 15 pF, see Figure 6
CL = 15 pF, see Figure 4
CL = 15 pF, see Figure 6
10
14
6
LD to SOP
ns
Rise and fall times
ns
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INPUT CHARACTERISTICS
30
RIN = 1.2kW
25
a) IIP-LIM = 2.5mA (RLIM = 36.1kW)
c)
a)
b)
b) IIP-LIM = 3.0mA (RLIM = 30.1kW)
c) IIP-LIM = 3.6mA (RLIM = 24.9 kW)
20
15
10
Off
On
5
Field Input Thresholds
0
0
4.0
0.5
1.0
1.5
2.0
/ mA
2.5
3.0
3.5
I
IN
Figure 1. Typical Input Characteristics
102.0
101.5
101.0
100.5
100.0
99.5
VCC = 5 V,
VIN = 24 V,
RIN = 1.2 kW,
RLIM = 24.9 kW
99.0
98.5
98.0
-45 -35 -25 -15 -5
5 15 25 35 45 55 65 75 85 95
TA - Ambient Temperature - °C
Figure 2. Typical Current Limiter Variation vs Ambient Temperature
9.6
9.4
VTH+(IN)
9.2
VCC = 5 V,
9.0
RIN = 1.2 kW,
8.8
RLIM = 24.9 kW
8.6
8.4
VTH–(IN)
8.2
8.0
-45 -35 -25 -15 -5
5
15 25 35 45 55 65 75 85 95
TA - Ambient Temperature - °C
Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature
6
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PARAMETER MEASUREMENT INFORMATION
Waveforms
For the complete serial interface timing, refer to Figure 17.
tW2
LD
LD
tREC
tLPH2
tPLH2
CLK
SOP
Figure 4. Parallel – Load Mode
Figure 5. Serial – Shift Mode
1/fCLK
valid
tW1
SIP
CLK
SOP
tH1
tSU1
tPLH1
tPHL1
CLK
tr
tf
Figure 6. Serial – Shift Mode
Figure 7. Serial – Shift Mode
CLK
tSU2
CLK
inhibited
CE
Figure 8. Serial – Shift Clock Inhibit Mode
Signal Conventions
R
IN
IPx
I
IN
V
V
TH(IN)
TH(IP)
SN65HVS885
GND
Figure 9. On/Off Threshold Voltage Measurements
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DEVICE INFORMATION
Digital Inputs
1.25 V
REF
5 V
I
Mirror
LIM
n = 72
I
IN
IPx
I
I
REF
LIM
Limiter
= I
R
LIM
I
INmax
LIM
Figure 10. Digital Input Stage
Each digital input operates as a controlled current sink limiting the input current to a maximum value of ILIM. The
current limit is derived from the reference current via ILIM = n × IREF, and IREF is determined by IREF = VREF/RLIM
Thus, changing the current limit requires the change of RLIM to a different value via: RLIM = n × VREF/ILIM
.
.
Inserting the actual values for n and VREF gives: RLIM = 90 V / ILIM
.
While the device is specified for a current limit of 3.6 mA, (via RLIM = 25 kΩ), it is easy to lower the current limit
to further reduce the power consumption. For example, for a current limit of 2.5 mA simply calculate:
90 V
ILIM
90 V
RLIM
=
=
= 36 kΩ
2.5 mA
Debounce Filter
The HVS885 applies a simple analog/digital filtering technique to remove unintended signal transitions due to
contact bounce or other mechanical effects. Any new input (either low or high) must be present for the duration
of the selected debounce time to be latched into the shift register as a valid state.
The logic signal levels at the control inputs, DB0 and DB1 of the internal Debounce-Select logic determine the
different debounce times listed in the following truth table.
Table 1. Debounce Times
DB1
Open
Open
DB0
Open
GND
FUNCTION
3 ms delay
1 ms delay
0 ms delay
(Filter bypassed)
GND
GND
Open
GND
Reserved
8
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5 V
IPx
REF
REx
R
LIM
GND
Figure 11. Equivalent Input Diagram
Shift Register
The conversion from parallel input to serial output data is performed by an eight-channel, parallel-in serial-out
shift register. Parallel-in access is provided by the internal inputs, PIP0–PIP7, that are enabled by a low level at
the load input (LD). When clocked, the latched input data shift towards the serial output (SOP). The shift register
also provides a clock-enable function.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while LD is held high and the clock
enable (CE) input is held low. Parallel loading is inhibited when LD is held high. The parallel inputs to the register
are enabled while LD is low independently of the levels of the CLK, CE, or serial (SIP) inputs.
SIP
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
SOP
CLK
CE
Logic
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
LD
PIP
0
PIP 1
PIP 2
PIP 3
PIP 4
PIP
5
PIP
6
PIP
7
Figure 12. Shift Register Logic Structure
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Table 2. Function Table
INPUTS
FUNCTION
LD
L
CLK
X
CE
X
Parallel load
No change
Shift(1)
H
X
H
H
↑
L
(1) Shift = content of each internal register shifts towards serial outputs.
Data at SIP is shifted into first register.
Temperature Sensor
An on-chip temperature sensor monitors the device temperature and signals a fault condition if the temperature
exceeds a first trip point at 150°C by pulling the HOT output low. If the junction temperature continues to rise,
passing a second trip point at 170 °C, all device outputs assume high impedance state.
A special condition occurs when the chip temperature exceeds the second temperature trip point due to an
output short; the HOT output buffer becomes high impedance, thus separating the buffer from the external
circuitry. An internal 100-kΩ pulldown resistor, connecting the HOT-pin to ground, is used as a "cooling down"
resistor, which continues to provide a logic low level to the external circuitry.
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APPLICATION INFORMATION
System-Level EMC
The SN65HVS885 is designed to operate reliably in harsh industrial environments. At a system level, the device
is tested according to several international electromagnetic compatibility (EMC) standards.
In addition to the device internal ESD structures, external protection circuitry shown in Figure 13, can be used to
absorb as much energy from burst- and surge-transients as possible.
R
IN
INx
IP0 – IP7
V
5 V
CC
1.2 kW, 1/4 W MELF Resistor
220 nF, 60 V Ceramic Capacitor
4.7 nF, 2 kV Ceramic Capacitor
RIN
CIN
CS
C
1mF
IN
SN65HVS885
0 V
FE
GND
C
S
Figure 13. Typical EMC Protection Circuitry for Supply and Signal Inputs
Input Channel Switching Characteristics
The input stage of the HVS885 is so designed, that for an input resistor RIN = 1.2 kΩ the trip point for signaling
an ON-condition is at 9.4 V at 3.6 mA. This trip point satisfies the switching requirements of IEC61131-2 Type 1
and Type 3 switches.
Type 1
Type 2
Type 3
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
ON
ON
ON
OFF
10
OFF
15
OFF
0
–3-
0
–3
0
–3
5
15
5
10
20
(mA)
25
30
5
10
(mA)
15
0
0
0
I
(mA)
I
IN
I
IN
IN
Figure 14. Switching Characteristics for IEC61131-2 Type 1, 2, and 3 Proximity Switches
For a Type 2 switch application, two inputs are connected in parallel. The current limiters then add to a total
maximum current of 7.2 mA. While the return-path (RE-pin), of one input might be used to drive an indicator
LED, the RE-pin of the other input channel should be connected to ground (GND).
Paralleling input channels reduces the number of available input channels from an octal Type 1 or Type 3 input
to a quad Type 2 input device. Note, that in this configuration output data of an input channel is represented by
two shift register bits.
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R
R
IN
IN
IN0
IN0
IP0
IP0
C
C
IN
IN
RE0
RE0
R
R
IN
IN
IN1
IP1
IP1
C
C
IN
IN
RE1
RE1
Figure 15. Paralleling Two Type 1 or Type 3 Inputs Into One Type 2 Input
Digital Interface Timing
The digital interface of the SN65HVS885 is SPI compatible and interfaces, isolated or non-isolated, to a wide
variety of standard micro controllers.
SN65HVS885
HOST
SIP
ISO7241
CONTROLLER
IP0
IP7
LD
CE
OUTA
OUTB
OUTC
IND
INA
INB
LOAD
STE
CLK
SOP
INC
SCLK
OUTD
SOMI
Figure 16. Simple Isolation of the Shift Register Interface
Upon a low-level at the load input, LD, the information of the field inputs, IP0 to IP7 is latched into the shift
register. Taking /LD high again blocks the parallel inputs of the shift register from the field inputs. A low-level at
the clock-enable input, CE, enables the clock signal, CLK, to serially shift the data to the serial output, SOP. Data
is clocked at the rising edge of CLK. Thus after eight consecutive clock cycles all field input data have been
clocked out of the shift register and the information of the serial input, SIP, appears at the serial output, SOP.
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CLK
CE
SIP
LD
high
PIP0–PIP6
PIP7
don’t care
IP7
IP6 IP5 IP4 IP3 IP2 IP1 IP0 SIP
SOP
inhibit
Serial shift
Figure 17. Interface Timing for Parallel-Load and Serial-Shift Operation of the Shift Register
Cascading for High Channel Count Input Modules
Designing high-channel count modules require cascading multiple SN65HVS885 devices. Simply connect the
serial output (SOP) of a leading device with the serial input (SIP) of a following device without changing the
processor interface.
HOST
CONTROLLER
ISO7241
4 x SN65HVS885
OUTA
OUTB
OUTC
IND
INA
INB
LOAD
STE
INC
SCLK
SOMI
OUTD
SERIALIZER
SERIALIZER
SERIALIZER
SERIALIZER
Figure 18. Cascading Four SN65HVS885 for a 32-Channel Input Module
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Typical Digital Input Module Application
Isolated DC-DC
SM15T39A
3V-ISO
0V-ISO
24V
0V
5VO
3VIN
4.7nF
2kV
Power
Supply
0VO
0VIN
4.7nF
2kV
FE
0.1 mF
SN65HVS885
NC
VCC
HOT
SIP
1.2k
ISO7242
MELF
HOST
CONTROLLER
IP0
RE0
VCC2
VCC1
22nF
S0
VCC
EN2
EN1
INA
LOAD
SCLK
INT
LD
OUTA
OUTB
INC
CLK
CE
INB
1.2k
MELF
IP7
OUTC
OUTD
GND1
22nF
S7
SOMI
DGND
SOP
DB0
DB1
RE7
RLIM
GND
IND
GND2
24.9k
Figure 19. Typical Digital Input Module Application
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2009
PACKAGING INFORMATION
Orderable Device
SN65HVS885PWP
SN65HVS885PWPR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
HTSSOP
PWP
28
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVS885PWPR
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN65HVS885PWPR
2000
Pack Materials-Page 2
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