SN65LBC173DRG4 [TI]
Quadruple Low-Power Differential Line Receiver 16-SOIC -40 to 85;
| 型号： | SN65LBC173DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quadruple Low-Power Differential Line Receiver 16-SOIC -40 to 85 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢋ ꢌꢍꢎꢏ ꢌꢐꢄ ꢑ ꢄ ꢒ ꢓꢔꢐꢒ ꢓ ꢑꢏ ꢎꢕ ꢖꢖ ꢑꢏ ꢑꢁꢗ ꢕꢍ ꢄ ꢄ ꢕꢁꢑ ꢏꢑꢆ ꢑꢕ ꢘ ꢑ ꢏꢀ
SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
D
Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B,
EIA/TIA-423-B, RS-485, and ITU
Recommendations V.10 and V.11.
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1B
1A
CC
D
D
D
D
D
D
Designed to Operate With Pulse Durations
as Short as 20 ns
4B
4A
4Y
G
1Y
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
G
2Y
Input Sensitivity . . . 200 mV
3Y
3A
3B
2A
2B
Low-Power Consumption . . . 20 mA Max
Open-Circuit Fail-Safe Design
GND
Pin Compatible With SN75173 and
AM26LS32
description
The SN65LBC173 and SN75LBC173 are monolithic quadruple differential line receivers with 3-state outputs.
Both are designed to meet the requirements of the ANSI standards EIA/TIA-422-B, EIA/TIA-423-B, RS-485,
and ITU Recommendations V.10 and V.11. The devices are optimized for balanced multipoint bus transmission
at data rates up to and exceeding 10 million bits per second. The four receivers share two ORed enable inputs,
one active when high, the other active when low.
Each receiver features high input impedance, input hysteresis for increased noise immunity, and input
sensitivity of 200 mV over a common-mode input voltage range of 12 V to −7 V. Fail-safe design ensures that
if the inputs are open circuited, the output is always high. Both devices are designed using the Texas Instruments
proprietary LinBiCMOS technology that provides low power consumption, high switching speeds, and
robustness.
These devices offer optimum performance when used with the SN75LBC172 or SN75LBC174 quadruple line
drivers. The SN65LBC173 and SN75LBC173 are available in the 16-pin DIP (N) and SOIC (D) packages.
The SN65LBC173 is characterized over the industrial temperature range of −40°C to 85°C. The SN75LBC173
is characterized for operation over the commercial temperature range of 0°C to 70°C.
FUNCTION TABLE
(each receiver)
ENABLES
DIFFERENTIAL INPUTS
A−B
OUTPUT
Y
G
G
H
X
X
L
H
H
V
ID
≥ 0.2 V
H
X
X
L
?
?
−0.2 V < V < 0.2 V
ID
H
X
X
L
L
L
V
ID
≤ −0.2 V
X
L
H
Z
H
X
X
L
H
H
Open Circuit
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
ꢐꢏ ꢒ ꢎꢌ ꢆ ꢗꢕ ꢒ ꢁ ꢎ ꢍꢗꢍ ꢙꢚ ꢛ ꢜꢝ ꢞ ꢟꢠ ꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠ ꢙꢜꢚ ꢨꢟ ꢠꢤ ꢩ
ꢐꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢗꢤꢫ ꢟꢡ ꢕꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢐꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ
Copyright 2000, Texas Instruments Incorporated
1
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ꢐ
ꢋ
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ꢆ
ꢑ
ꢕ
ꢘ
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ꢏ
ꢀ
SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
†
logic symbol
logic diagram (positive logic)
4
4
G
≥ 1
G
G
12
12
G
2
2
1A
3
5
1A
1B
2A
2B
3A
3B
4A
4B
3
5
1Y
1
1
1Y
2Y
3Y
4Y
1B
6
7
2Y
3Y
4Y
6
2A
10
9
7
11
13
2B
14
15
10
3A
9
11
3B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
14
4A
4B
13
15
schematics of inputs and outputs
EQUIVALENT OF A AND B INPUTS
TYPICAL OF ALL OUTPUTS
TYPICAL OF G AND G INPUTS
V
CC
V
CC
V
CC
100 kΩ
(A Only)
3 kΩ
Receiver
Input
Output
Input
18 kΩ
Y Output
100 kΩ
(B Only)
12 kΩ
1 kΩ
2
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SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
CC
Input voltage, V (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
I
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
ID
Voltage range at Y, G, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
+ 0.5 V
CC
Operating free-air temperature range, T : SN65LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
A
SN75LBC173 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
N
1100 mW
1150 mW
8.7 mW/°C
9.2 mW/°C
708 mW
736 mW
578 mW
598 mW
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
−7
5
Common-mode input voltage, V
IC
V
Differential input voltage, V
6
V
ID
High-level input voltage, V
IH
2
V
G inputs
Low-level input voltage, V
IL
0.8
−8
8
V
High-level output current, I
mA
mA
OH
Low-level output current, I
OL
SN65LBC173
SN75LBC173
−40
0
85
70
Operating free-air temperature, T
°C
A
3
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SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
I
I
= −8 mA
= 8 mA
0.2
IT+
IT−
hys
IK
O
−0.2
V
O
Hysteresis voltage (V
IT+
− V
IT−
)
45
−0.9
4.5
mV
V
Enable input clamp voltage
High-level output voltage
Low-level output voltage
I = −18 mA
−1.5
I
V
V
V
V
V
V
V
V
V
V
= 200 mV,
I
I
= −8 mA
= 8 mA
3.5
V
OH
OL
ID
ID
O
OH
= −200 mV,
0.3
0.5
20
V
OL
I
High-impedance-state output current
= 0 V to V
= 12 V,
= 12 V,
= −7 V,
= −7 V,
= 5 V
µA
OZ
CC
V
V
V
V
= 5 V, Other inputs at 0 V
= 0 V, Other inputs at 0 V
= 5 V, Other inputs at 0 V
= 0 V, Other inputs at 0 V
0.7
0.8
1
IH
IH
IH
IH
IH
IL
CC
CC
CC
CC
1
I
I
Bus input current
A or B inputs
mA
−0.5
−0.4
−0.8
−0.8
20
I
I
I
High-level input current
Low-level input current
Short-circuit output current
µA
µA
IH
= 0 V
−20
IL
= 0
−80 −120
mA
OS
O
Outputs enabled,
Outputs disabled
I
O
= 0,
V
ID
= 5 V
11
20
I
Supply current
mA
CC
0.9
1.4
†
All typical values are at V
= 5 V and T = 25°C.
A
CC
switching characteristics, V
= 5 V, C = 15 pF, T = 25°C
L A
CC
PARAMETER
TEST CONDITIONS
MIN
11
TYP
22
22
17
18
35
25
0.5
5
MAX
30
30
30
30
45
40
6
UNIT
ns
t
t
t
t
t
t
t
t
Propagation delay time, high- to low-level output
PHL
PLH
PZH
PZL
PHZ
PLZ
sk(p)
t
V
ID
= −1.5 V to 1.5 V, See Figure 1
Propagation delay time, low- to high-level output
Output enable time to high level
11
ns
See Figure 2
See Figure 3
See Figure 2
See Figure 3
See Figure 2
See Figure 1
ns
Output enable time to low level
ns
Output disable time from high level
Output disable time from low level
ns
ns
Pulse skew (|t
− t
PHL PLH
|)
ns
Transition time
10
ns
4
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ꢋ ꢌꢍꢎꢏ ꢌꢐꢄ ꢑ ꢄ ꢒ ꢓꢔꢐꢒ ꢓ ꢑꢏ ꢎꢕ ꢖꢖ ꢑꢏ ꢑꢁꢗ ꢕꢍ ꢄ ꢄ ꢕꢁꢑ ꢏꢑꢆ ꢑ ꢕꢘ ꢑ ꢏꢀ
SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
1.5 V
Generator
(see Note A)
Input
t
0 V
0 V
50 Ω
Output
= 15 pF
−1.5 V
C
t
L
PLH
PHL
(see Note B)
V
OH
OL
90%
10%
Output
1.3 V
1.3 V
V
t
t
t
t
2 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 1. t and t Test Circuit and Voltage Waveforms
pd
t
V
CC
2 kΩ
Input
Output
1.5 V
S1
3 V
0 V
1.3 V
1.3 V
C
= 15 pF
L
(see Note B)
t
t
PHZ
0.5 V
PZH
5 kΩ
See Note C
V
OH
Output
S1 Open
1.3 V
S1 Closed
2 V
≈ 1.4 V
0 V
Generator
(see Note A)
VOLTAGE WAVEFORMS
50 Ω
(see Note D)
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
C
O
B.
includes probe and jig capacitance.
L
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 2. t
and t
Test Circuit and Voltage Waveforms
PHZ
PZH
5
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SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
2 kΩ
Output
1.5 V
3 V
0 V
Input
t
C
= 15 pF
1.3 V
1.3 V
L
(see Note B)
5 kΩ
See Note C
t
PZL
PLZ
S2 Closed
≈ 1.4 V
S2 Open
2 V
Output
1.3 V
Generator
V
OL
(see Note A)
S2
0.5 V
VOLTAGE WAVEFORMS
50 Ω
(see Note D)
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
C
O
B.
includes probe and jig capacitance.
L
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
Figure 3. t
and t
Test Circuit and Voltage Waveforms
PZL
PLZ
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
5.5
5
4.5
4
V
T
A
= 5 V
= 25°C
CC
V
CC
= 5.25 V
4.5
4
3.5
3
V
CC
= 5 V
3.5
3
V
CC
= 4.75 V
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
V
T
A
= 0.2 V
ID
= 25°C
0.5
0
0
−4 −8 −12 −16 −20 −24 −28 −32 −36 −40
0
10 20 30 40 50 60 70 80 90 100
I
− High-Level Output Current − mA
V
ID
− Differential Input Voltage − mV
OH
Figure 4
Figure 5
6
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SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
FREQUENCY
LOW-LEVEL OUTPUT CURRENT
14
12
10
8
660
600
540
480
420
360
300
240
180
120
60
T
V
= 25°C
A
T
V
V
= 25°C
A
= 5 V
CC
= 5 V
= 200 mV
CC
ID
6
4
2
0
0
10k
100k
1M
10M
100M
0
3
6
9
12 15 18 21 24 27 30
f − Frequency − Hz
I
− Low-Level Output Current − mA
OL
Figure 6
Figure 7
BUS
INPUT CURRENT
vs
INPUT VOLTAGE
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
(COMPLEMENTARY INPUT AT 0 V)
1
0.8
24.5
24
T
V
= 25°C
V
C
= 5 V
= 15 pF
= 1.5 V
A
CC
L
= 5 V
CC
V
IO
0.6
0.4
t
PHL
0.2
23.5
23
0
−0.2
−0.4
−0.6
−0.8
−1
t
PLH
22.5
22
The shaded region of this graph represents
more than 1 unit load per RS-485.
−8 −6 −4 −2
0
2
4
6
8
10 12
−40
−20
0
20
40
60
80
100
V − Input Voltage − V
I
T
A
− Free-Air Temperature − °C
Figure 8
Figure 9
7
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ꢋ
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ꢄ
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ꢓꢔ
ꢐ
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ꢖꢑ
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ꢆ
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SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−ā8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄ ꢅꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢍ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢌ
ꢐ
ꢄ
ꢑ
ꢄ
ꢒ
ꢓꢔ
ꢐ
ꢒ
ꢓ
ꢑ
ꢏ
ꢎ
ꢕ
ꢖꢖ
ꢑ
ꢏ
ꢑ
ꢁ
ꢗ
ꢕ
ꢄ
ꢄ
ꢕ
ꢁ
ꢑ
ꢏ
ꢑ
ꢆ
ꢑ
ꢕꢘ
ꢑ
ꢏ
ꢀ
SLLS170E − OCTOBER 1993 − REVISED AUGUST 2000
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23.37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21.59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°−ā15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN65LBC173D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LBC173DG4
SN65LBC173DR
SN65LBC173DRG4
SN65LBC173N
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
N
N
D
D
D
D
N
N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65LBC173NE4
SN75LBC173D
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LBC173DG4
SN75LBC173DR
SN75LBC173DRG4
SN75LBC173N
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75LBC173NE4
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN75LBC173 :
Military: SN55LBC173
•
NOTE: Qualified Version Definitions:
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65LBC173DR
SN65LBC173DR
SN75LBC173DR
SN75LBC173DR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
16
16
16
16
2500
2500
2500
2500
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
6.5
6.5
6.5
6.5
10.3
10.3
10.3
10.3
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LBC173DR
SN65LBC173DR
SN75LBC173DR
SN75LBC173DR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
16
16
16
16
2500
2500
2500
2500
333.2
346.0
346.0
333.2
345.9
346.0
346.0
345.9
28.6
33.0
33.0
28.6
Pack Materials-Page 2
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