SN65LBC179DG4 [TI]
LOW-POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS; ？低功耗差动线路驱动器和接收器对
| 型号： | SN65LBC179DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS |
| 文件： | 总19页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢄꢌ ꢍꢎꢏ ꢌꢍ ꢐꢑ ꢒꢓ ꢔꢔ ꢐꢑ ꢐꢁꢕ ꢓꢖ ꢄ ꢄ ꢓꢁꢐ ꢒꢑꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐ ꢑ ꢏꢖ ꢓꢑ ꢀ
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
D OR P PACKAGE
(TOP VIEW)
D
Designed for High-Speed Multipoint Data
Transmission Over Long Cables
D
Operates With Pulse Widths as Low
as 30 ns
V
A
B
Z
Y
1
2
3
4
8
7
6
5
CC
R
D
Low Supply Current . . . 5 mA Max
D
D
Meets or Exceeds the Standard
Requirements of ANSI RS-485 and
ISO 8482:1987(E)
GND
Function Tables
D
D
Common-Mode Voltage Range of −7 V
to 12 V
DRIVER
INPUT
D
OUTPUTS
Positive- and Negative-Output Current
Limiting
Y
Z
H
L
H
L
L
H
D
Driver Thermal Shutdown Protection
Pin Compatible With the SN75179B
D
RECEIVER
DIFFERENTIAL INPUTS OUTPUT
description
A−B
≥ 0.2 V
R
H
?
L
H
The SN65LBC179, SN65LBC179Q,
and
V
ID
−0.2 V < V < 0.2 V
SN75LBC179 differential driver and receiver pairs
are monolithic integrated circuits designed for
bidirectional data communication over long
cables that take on the characteristics of
transmission lines. They are balanced, or
differential, voltage mode devices that meet or
exceed the requirements of industry standards
ANSI RS-485 and ISO 8482:1987(E). Both
devices are designed using TI’s proprietary
LinBiCMOS with the low power consumption of
CMOS and the precision and robustness of
bipolar transistors in the same circuit.
ID
≤ − 0.2 V
V
ID
Open circuit
H = high level,
? = indeterminate
L = low level,
†
logic symbol
8
7
2
A
B
R
6
5
3
Z
Y
D
The SN65LBC179, SN65LBC179Q,
and
SN75LBC179 combine a differential line driver
and differential line receiver and operate from a
single 5-V supply. The driver differential outputs
and the receiver differential inputs are connected
to separate terminals for full-duplex operation and
are designed to present minimum loading to the
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
8
2
A
B
bus when powered off (V
= 0). These parts
R
D
7
CC
feature a wide common-mode voltage range
making them suitable for point-to-point or
multipoint data bus applications. The devices also
provide positive- and negative-current limiting
and thermal shutdown for protection from line fault
conditions. The line driver shuts down at a junction
temperature of approximately 172°C.
5
6
3
Y
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
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Copyright 1994 − 2006, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ ꢋ
ꢄ ꢌꢍꢎꢏ ꢌꢍꢐꢑ ꢒ ꢓ ꢔꢔ ꢐꢑ ꢐꢁ ꢕꢓ ꢖ ꢄ ꢄꢓ ꢁ ꢐ ꢒꢑ ꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐꢑ ꢏꢖꢓ ꢑꢀ
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
description (continued)
The SN65LBC179, SN65LBC179Q, and SN75LBC179 are available in the 8-pin dual-in-line and small-outline
packages. The SN75LBC179 is characterized for operation over the commercial temperature range of 0°C to
70°C. The SN65LBC179 is characterized over the industrial temperature range of −40°C to 85°C. The
SN65LBC179Q is characterized over the extended industrial or automotive temperature range of −40°C to
125°C.
schematics of inputs and outputs
EQUIVALENT OF DRIVER INPUT
RECEIVER A INPUT
RECEIVER B INPUT
V
CC
V
CC
V
CC
100 kΩ
NOM
22 kΩ
3 kΩ
NOM
3 kΩ
NOM
18 kΩ
NOM
18 kΩ
NOM
Input
Input
Input
12 kΩ
12 kΩ
100 kΩ
NOM
1.1 kΩ
NOM
1.1 kΩ
NOM
DRIVER OUTPUT
TYPICAL OF RECEIVER OUTPUT
V
V
CC
CC
R Output
Output
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢌ ꢍꢎꢏ ꢌꢍ ꢐꢑ ꢒꢓ ꢔꢔ ꢐꢑ ꢐꢁꢕ ꢓꢖ ꢄ ꢄ ꢓꢁꢐ ꢒꢑꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐ ꢑ ꢏꢖ ꢓꢑ ꢀ
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
†
absolute maximum ratings
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
CC
Voltage range at A, B, Y, or Z (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V
Voltage range at D or R (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.5 V
CC
Receiver output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
O
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. The maximum operating junction temperature is internally limited. Uses the dissipation rating table to operate below this
temperature.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
4.75
2
5
5.25
V
V
V
V
V
High-level input voltage, V
IH
D
D
Low-level input voltage, V
IL
0.8
6
‡
−6
Differential input voltage, V
ID
Voltage at any bus terminal (separately or common-mode), V , V , or V
IC
A, B, Y, or Z
−7
12
O
I
Y or Z
R
−60
−8
60
High-level output current, I
mA
OH
Y or Z
R
Low-level output current, I
Junction temperature, T
mA
OL
8
140
85
°C
J
SN65LBC179
SN65LBC179Q
SN75LBC179
−40
−40
0
Operating free-air temperature, T
125
70
°C
A
‡
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for differential
input voltage, voltage at any bus terminal (separately or common mode), operating temperature, input threshold voltage, and common-mode
output voltage.
DISSIPATION RATING TABLE
THERMAL
MODEL
T
< 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
ABOVE T = 25°C
POWER RATING POWER RATING
POWER RATING
A
†
Low K
526 mW
5.0 mW/°C
8.4 mW/°C
8.0 mW/°C
301 mW
504 mW
480 mW
226 mW
378 mW
360 mW
D
P
‡
High K
882 mW
840 mW
†
‡
In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.
In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.
3
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ ꢋ
ꢄ ꢌꢍꢎꢏ ꢌꢍꢐꢑ ꢒ ꢓ ꢔꢔ ꢐꢑ ꢐꢁ ꢕꢓ ꢖ ꢄ ꢄꢓ ꢁ ꢐ ꢒꢑ ꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐꢑ ꢏꢖꢓ ꢑꢀ
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
DRIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
IK
I = −18 mA
−1.5
V
I
SN65LBC179,
SN65LBC179Q
1.1
1.5
1.1
1.5
2.2
2.2
2.2
2.2
5
5
R
= 54 Ω,
L
See Figure 1
SN75LBC179
|V
OD
|
Differential output voltage (see Note 3)
V
SN65LBC179,
SN65LBC179Q
5
R
= 60 Ω,
L
See Figure 2
SN75LBC179
5
Change in magnitude of differential output voltage
(see Note 4)
∆|V
|
|
See Figures 1 and 2
0.2
3
V
V
V
OD
V
OC
Common-mode output voltage
1
2.5
R
= 54 Ω,
See Figure 1
Change in magnitude of common-mode output
voltage (see Note 4)
L
∆|V
0.2
OC
I
I
I
I
Output current with power off
High-level input current
Low-level input current
V
= 0,
V = −7 V to 12 V
O
100
−100
−100
250
µA
µA
µA
mA
O
CC
V = 2.4 V
I
IH
IL
V = 0.4 V
I
Short-circuit output current
−7 V ≤ V ≤ 12 V
O
OS
SN65LBC179,
SN75LBC179
4.2
4.2
5
7
mA
mA
I
Supply current
No load
CC
SN65LBC179Q
†
All typical values are at V
CC
= 5 V and T = 25°C.
A
NOTES: 3. The minimum V
specification of the SN65179 may not fully comply with ANSI RS-485 at operating temperatures below 0°C.
OD
System designers should take the possibly lower output signal into account in determining the maximum signal transmission
distance.
4. ∆|V
OD
| and ∆|V
OC
| are the changes in the steady-state magnitude of V
changed from a high level to a low level.
and V
, respectively, that occur when the input is
OC
OD
switching characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 54 Ω, See Figure 3
MIN
7
MAX
18
UNIT
ns
t
t
Differential-output delay time
Differential transition time
d(OD)
R
L
5
20
ns
t(OD)
4
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ꢀꢁꢂ ꢃ ꢄ ꢅꢆꢇ ꢂ ꢈ ꢉ ꢀꢁꢊ ꢃ ꢄ ꢅꢆꢇ ꢂ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢂꢈ ꢋ
ꢄꢌ ꢍꢎꢏ ꢌꢍ ꢐꢑ ꢒꢓ ꢔꢔ ꢐꢑ ꢐꢁꢕ ꢓꢖ ꢄ ꢄ ꢓꢁꢐ ꢒꢑꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐ ꢑ ꢏꢖ ꢓꢑ ꢀ
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
−0.2
3.5
TYP
MAX
UNIT
V
V
IT+
V
IT−
V
hys
V
OH
V
OL
Positive-going input threshold voltage
Negative-going input threshold voltage
I
I
= −8 mA
= 8 mA
0.2
O
V
O
Hysteresis voltage (V
IT+
− V
)
45
4.5
0.3
mV
V
IT−
High-level output voltage
Low-level output voltage
V
V
= 200 mV,
I
I
= −8 mA
= 8 mA
ID
OH
= −200 mV,
0.5
1
V
ID
OL
SN65LBC179,
V = 12 V,
I
0.7
0.7
mA
mA
mA
mA
mA
mA
mA
mA
SN75LBC179
Other inputs at 0 V,
V
= 5 V
SN65LBC179Q
1.2
CC
SN65LBC179,
SN75LBC179
V = 12 V,
I
0.8
1
Other inputs at 0 V,
V
= 0 V
SN65LBC179Q
0.8
1.2
−0.8
−1.0
−0.8
−1.0
CC
I
I
Bus input current
SN65LBC179,
SN75LBC179
V = −7 V,
I
−0.5
−0.5
−0.5
−0.5
Other inputs at 0 V,
V
= 5 V
SN65LBC179Q
CC
SN65LBC179,
SN75LBC179
V = −7 V,
I
Other inputs at 0 V,
V
= 0 V
CC
SN65LBC179Q
switching characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
MIN
15
TYP
MAX
30
30
6
UNIT
ns
t
t
t
t
Propagation delay time, high- to low-level output
Propagation delay time, low- to high-level output
PHL
PLH
sk(p)
t
V
ID
= −1.5 V to 1.5 V, See Figure 4
15
ns
Pulse skew ( t
− t
)
3
3
ns
PHL PLH
See Figure 4
Transition time
5
ns
PARAMETER MEASUREMENT INFORMATION
Y
R
2
L
D
V
OD
0 V or 3 V
R
2
L
V
OC
Z
Figure 1. Differential and Common-Mode Output Voltage Test Circuit
5
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ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ ꢋ
ꢄ ꢌꢍꢎꢏ ꢌꢍꢐꢑ ꢒ ꢓ ꢔꢔ ꢐꢑ ꢐꢁ ꢕꢓ ꢖ ꢄ ꢄꢓ ꢁ ꢐ ꢒꢑ ꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐꢑ ꢏꢖꢓ ꢑꢀ
ꢘ
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
PARAMETER MEASUREMENT INFORMATION
V
test
R1
375 Ω
Y
Z
D
R
= 60 Ω
V
OD
L
0 V or 3 V
R2
375 Ω
−7 V < V
test
< 12 V
V
test
Figure 2. Differential Output Voltage Test Circuit
3 V
Input
1.5 V
1.5 V
0 V
t
t
d(ODH)
d(ODL)
C
= 50 pF
Output
L
≈ 2.5 V
(see Note B)
R
= 54 Ω
Generator
(see Note A)
L
50%
50%
Output
50 Ω
≈ − 2.5 V
t
t
t(OD)
t(OD)
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
TEST CIRCUIT
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 3. Driver Test Circuits and Differential Output Delay and Transition Time Voltage Waveforms
3 V
Input
1.5 V
1.5 V
A
B
0 V
Generator
(see Note A)
Output
t
t
PHL
50 Ω
PLH
1.5 V
V
OH
C
= 15 pF
90%
1.3 V
10%
90%
L
(see Note B)
1.3 V
10%
Output
V
OL
t
t
t
t
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
VOLTAGE WAVEFORMS
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 4. Receiver Test Circuit and Propagation Delay and Transition Time Voltage Waveforms
6
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SLLS173F − JANUARY 1994 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5
4.5
4
5
4.5
4
V
T
= 5 V
V
T
= 5 V
= 25°C
CC
CC
= 25°C
A
A
3.5
3.5
3
3
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0
0.5
0
0
10 20 30 40 50 60 70 80 90 100
0
20
40
60
80
100
120
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OH
OL
Figure 5
Figure 6
DRIVER
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
4
3
2.5
2
V
T
A
= 5 V
V
= 5 V
CC
= 25°C
CC
Load = 54 Ω
= 2 V
3.5
V
IH
3
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
10 20 30 40 50 60 70 80 90 100
− 50
− 25
0
25
50
75
100
125
I
O
− Output Current − mA
T
A
− Free-Air Temperature − °C
Figure 7
Figure 8
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ ꢋ
ꢄ ꢌꢍꢎꢏ ꢌꢍꢐꢑ ꢒ ꢓ ꢔꢔ ꢐꢑ ꢐꢁ ꢕꢓ ꢖ ꢄ ꢄꢓ ꢁ ꢐ ꢒꢑ ꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐꢑ ꢏꢖꢓ ꢑꢀ
ꢘ
ꢘ
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
DRIVER
RECEIVER
DIFFERENTIAL DELAY TIME
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
6
5
4
20
15
10
V
ID
= 200 mV
V
= 5 V
CC
Load = 54 Ω
t
d(ODL)
t
d(ODH)
3
2
5
0
1
0
− 50
− 25
0
25
50
75
100
125
0
−10
− 20
− 30
− 40
− 50
I
− High-Level Output Current − mA
T
A
− Free-Air Temperature − °C
OH
Figure 9
Figure 10
RECEIVER
RECEIVER
OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
1
6
V
= 5 V
= 25°C
= − 200 mV
CC
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
T
A
V
ID
5
V
IC
= 12 V
4
3
2
V
IC
= 0 V
V
IC
= −7 V
1
0
0
5
10
15
20
25
30
35
40
− 80 − 60 − 40 − 20
0
20
40
60
80
I
− Low-Level Output Current − mA
OL
V
ID
− Differential Input Voltage − mV
Figure 11
Figure 12
8
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ꢀꢁꢂ ꢃ ꢄ ꢅꢆꢇ ꢂ ꢈ ꢉ ꢀꢁꢊ ꢃ ꢄ ꢅꢆꢇ ꢂ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢂꢈ ꢋ
ꢄꢌ ꢍꢎꢏ ꢌꢍ ꢐꢑ ꢒꢓ ꢔꢔ ꢐꢑ ꢐꢁꢕ ꢓꢖ ꢄ ꢄ ꢓꢁꢐ ꢒꢑꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐ ꢑ ꢏꢖ ꢓꢑ ꢀ
ꢘ
ꢘ
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
TYPICAL CHARACTERISTICS
RECEIVER
INPUT CURRENT
vs
AVERAGE SUPPLY CURRENT
vs
INPUT VOLTAGE
FREQUENCY
(COMPLEMENTARY INPUT AT 0 V)
60
55
50
45
40
35
30
25
1
0.8
Receiver Load = 50 pF
Driver Load = Receiver Inputs
T
V
= 25°C
A
= 5 V
CC
0.6
0.4
0.2
0
− 0.2
− 0.4
− 0.6
− 0.8
− 1
20
15
10
5
The shaded region of this graph represents
more than 1 unit load per RS-485.
0
10 K
100 K
1 M
10 M
100 M
− 8 − 6 − 4 − 2
0
2
4
6
8
10 12
V − Input Voltage − V
I
f − Frequency − Hz
Figure 13
Figure 14
RECEIVER
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
24.5
24
V
C
= 5 V
= 15 pF
= 1.5 V
CC
L
V
IO
t
PHL
23.5
23
t
PLH
22.5
22
− 40 − 20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
Figure 15
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢂ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢆ ꢇ ꢂ ꢈ ꢋ
ꢄ ꢌꢍꢎꢏ ꢌꢍꢐꢑ ꢒ ꢓ ꢔꢔ ꢐꢑ ꢐꢁ ꢕꢓ ꢖ ꢄ ꢄꢓ ꢁ ꢐ ꢒꢑ ꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐꢑ ꢏꢖꢓ ꢑꢀ
ꢘ
ꢘ
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
THERMAL CHARACTERISTICS − D PACKAGE
TEST CONDITIONS
PARAMETER
MIN
TYP
199.4
119
MAX
UNIT
Low-K board, no air flow
†
Junction−to−ambient thermal reisistance, θ
JA
High-K board, no air flow
°C/W
Junction−to−board thermal reisistance, θ
JB
High-K board, no air flow
67
Junction−to−case thermal reisistance, θ
46.6
JC
R
= 54 Ω, input to D is 10 Mbps 50% duty
L
cycle square wave, V
°C.
= 5.25 V, T = 130
Average power dissipation, P
(AVG)
330
mW
CC
J
Thermal shutdown junction temperature, T
SD
165
°C
†
See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄ ꢅꢆꢇ ꢂ ꢈ ꢉ ꢀꢁꢊ ꢃ ꢄ ꢅꢆꢇ ꢂ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢂꢈ ꢋ
ꢄꢌ ꢍꢎꢏ ꢌꢍ ꢐꢑ ꢒꢓ ꢔꢔ ꢐꢑ ꢐꢁꢕ ꢓꢖ ꢄ ꢄ ꢓꢁꢐ ꢒꢑꢓ ꢗꢐ ꢑ ꢖꢁꢒ ꢑꢐꢆ ꢐꢓꢗ ꢐ ꢑ ꢏꢖ ꢓꢑ ꢀ
ꢘ
ꢘ
SLLS173F − JANUARY 1994 − REVISED APRIL 2006
THERMAL CHARACTERISTICS OF IC PACKAGES
Θ
JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
Θ
D
D
D
Θ
JA is NOT a constant and is a strong function of
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures.
installations.
is often misused when it is used to calculate junction temperatures for other
Θ
JA
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board givesbest case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
Θ
JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is only
defined for the high-k test card.
Θ
JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 16).
Ambient Node
q
Calculated
CA
Surface Node
Calculated/Measured
q
JC
Junction
Calculated/Measured
q
JB
PC Board
Figure 16. Thermal Resistance
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2010
PACKAGING INFORMATION
Orderable Device
SN65LBC179D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LBC179DG4
SN65LBC179DR
SN65LBC179DRG4
SN65LBC179P
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
P
P
D
D
D
D
D
D
D
D
P
P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN65LBC179PE4
SN65LBC179QD
SN65LBC179QDG4
SN65LBC179QDR
SN65LBC179QDRG4
SN75LBC179D
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LBC179DG4
SN75LBC179DR
SN75LBC179DRG4
SN75LBC179P
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75LBC179PE4
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2010
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LBC179DR
SN75LBC179DR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Mar-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LBC179DR
SN75LBC179DR
SOIC
SOIC
D
D
8
8
2500
2500
340.5
340.5
338.1
338.1
20.6
20.6
Pack Materials-Page 2
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