SN65LBC180AD [TI]
LOW POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS; 低功耗差分线路驱动器和接收器对
| 型号： | SN65LBC180AD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW POWER DIFFERENTIAL LINE DRIVER AND RECEIVER PAIRS |
| 文件： | 总19页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄ ꢅꢆꢇ ꢈ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ
ꢄꢍ ꢎꢏꢐ ꢍꢎ ꢑꢒ ꢓꢔ ꢕꢕ ꢑꢒ ꢑꢁꢖ ꢔꢊ ꢄ ꢄ ꢔꢁꢑ ꢓꢒꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑ ꢒ ꢐꢊ ꢔꢒ ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
SN65LBC180AD (Marked as BL180A)
D
High-Speed Low-Power LinBICMOS
Circuitry Designed for Signaling Rates of
up to 30 Mbps
SN65LBC180AN (Marked as 65LBC180A)
SN75LBC180AD (Marked as LB180A)
SN75LBC180AN (Marked as 75LBC180A)
(TOP VIEW)
†
D
D
D
D
Bus-Pin ESD Protection Exceeds 12 kV
HBM
NC
R
V
V
A
B
Z
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
CC
Very Low Disabled Supply-Current
Requirements . . . 700 µA Maximum
Designed for High-Speed Multipoint Data
Transmission Over Long Cables
RE
DE
D
Common-Mode Voltage Range of
−7 V to 12 V
GND
GND
8
NC
D
Low Supply Current . . . 15 mA Max
NC−No internal connection
D
Compatible With ANSI Standard
TIA/EIA-485-A and ISO 8482:1987(E)
Function Tables
D
D
Positive and Negative Output Current
Limiting
DRIVER
INPUT
ENABLE
OUTPUTS
Driver Thermal Shutdown Protection
D
H
L
X
Open
DE
H
H
Y
H
L
Z
L
H
Z
L
description
L
Z
The SN65LBC180A and SN75LBC180A
H
H
differential driver and receiver pairs are monolithic
integrated circuits designed for bidirectional data
communication over long cables that take on the
characteristics of transmission lines. They are
balanced, or differential, voltage mode devices
that are compatible with ANSI standard
TIA/EIA-485-A and ISO 8482:1987(E). The A
version offers improved switching performance
over its predecessors without sacrificing
significantly more power.
RECEIVER
DIFFERENTIAL INPUTS
A−B
ENABLE
OUTPUT
RE
L
L
L
H
L
R
H
?
L
Z
H
V
≥ 0.2 V
ID
≤ − 0.2 V
X
ID
−0.2 V < V < 0.2 V
V
ID
Open circuit
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off)
These devices combine a differential line driver and differential input line receiver and operate from a single 5-V
power supply. The driver differential outputs and the receiver differential inputs are connected to separate
terminals for full-duplex operation and are designed to present minimum loading to the bus when powered off
(V
= 0). These parts feature wide positive and negative common-mode voltage ranges, making them suitable
CC
for point-to-point or multipoint data bus applications. The devices also provide positive and negative current
limiting for protection from line fault conditions. The SN65LBC180A is characterized for operation from −40°C
to 85°C, and the SN75LBC180A is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit duration, and much higher signaling rates may be achieved
without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device.
LinBiCMOS is a trademark of Texas Instruments.
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Copyright 2002, Texas Instruments Incorporated
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1
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SLLS378C − MAY 2000 − REVISED JUNE 2002
†
logic symbol
logic diagram (positive logic)
4
DE
4
9
9
DE
D
EN1
Y
Z
1
1
Y
Z
5
5
10
D
10
3
2
3
2
12
11
RE
RE
R
EN2
2
A
B
12
11
A
B
R
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
AVAILABLE OPTIONS
PACKAGE
PLASTIC
DUAL-IN-LINE
(N)
†
T
A
SMALL OUTLINE
(D)
0°C to 70°C
SN75LBC180AD
SN65LBC180AD
SN75LBC180AN
SN65LBC180AN
−40°C to 85°C
†
The D package is available taped and reeled. Add an R suffix to the part
number (i.e., SN65LBC180ADR).
2
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SLLS378C − MAY 2000 − REVISED JUNE 2002
schematics of inputs and outputs
D, DE, and RE Inputs
V
CC
100 kΩ
1 kΩ
Input
8 V
A Input
B Input
V
CC
V
CC
16 V
100 kΩ
4 kΩ
4 kΩ
16 V
18 kΩ
18 kΩ
Input
Input
100 kΩ
4 kΩ
16 V
16 V
4 kΩ
Y AND Z Outputs
V
CC
R Output
V
CC
16 V
40 Ω
Output
Output
8 V
16 V
3
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ꢄ ꢍꢎꢏꢐ ꢍꢎꢑꢒ ꢓꢔ ꢕ ꢕꢑ ꢒꢑ ꢁꢖ ꢔ ꢊꢄ ꢄꢔ ꢁ ꢑ ꢓꢒ ꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑꢒ ꢐꢊꢔ ꢒꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
†
absolute maximum ratings
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
CC
Input voltage range, V (A, B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V
I
Voltage range at D, R, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.5 V
CC
Continuous total power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Electrostatic discharge:Bus terminals and GND, Class 3, A: (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . 12 kV
Bus terminals and GND, Class 3, B: (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . 400 V
All terminals, Class 3, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
All terminals, Class 3, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND except for differential input or output voltages.
2. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.
3. Tested in accordance with MIL−STD−883C, Method 3015.7
DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T = 85°C
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
D
N
950 mW
7.6 mW/°C
9.2 mW/°C
608 mW
736 mW
494 mW
598 mW
1150 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
Supply voltage, V
CC
4.75
2
5
5.25
V
V
V
V
V
High-level input voltage, V
IH
D, DE, and RE
D, DE, and RE
V
CC
0.8
Low-level input voltage, V
IL
0
§
−12
Differential input voltage, V (see Note 4)
ID
12
12
Voltage at any bus terminal (separately or common mode), V , V , or V
IC
A, B, Y, or Z
−7
−60
−8
O
I
Y or Z
High-level output current, I
mA
mA
°C
OH
R
Y or Z
60
8
Low-level output current, I
OL
R
SN65LBC180A
SN75LBC180A
−40
0
85
70
Operating free-air temperature, T
A
§
The algebraic convention where the least positive (more negative) limit is designated minimum, is used in this data sheet.
NOTE 4: Differential input/output bus voltage is measured at the noninverting terminal with respect to the inverting terminal.
4
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ꢄꢍ ꢎꢏꢐ ꢍꢎ ꢑꢒ ꢓꢔ ꢕꢕ ꢑꢒ ꢑꢁꢖ ꢔꢊ ꢄ ꢄ ꢔꢁꢑ ꢓꢒꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑ ꢒ ꢐꢊ ꢔꢒ ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
Input clamp voltage
I = −18 mA
−1.5
1
−0.8
1.5
1.5
1.5
1.5
V
IK
I
SN65LBC180A
3
3
3
3
R
= 54 Ω,,
L
See Figure 1
SN75LBC180A
SN65LBC180A
SN75LBC180A
1.1
1
Differential output voltage
magnitude
| V
OD
|
V
R
= 60 Ω,,
L
See Figure 2
1.1
Change in magnitude of
differential output voltage
(see Note 5)
∆| V
|
See Figures 1 and 2
−0.2
1.8
0.2
2.8
V
V
V
OD
Steady-state common-mode
output voltage
V
2.4
OC(SS)
See Figure 1
Change in steady-state
common-mode output voltage
(see Note 5)
∆ V
OC
−0.1
0.1
10
I
I
I
I
Output current with power off
High-level input current
Low-level input current
V
= 0,
V = −7 V to 12 V
O
−10
−100
−100
−250
µA
µA
µA
mA
O
CC
V = 2 V
IH
IL
I
V = 0.8 V
I
Short-circuit output current
−7 V ≤ V ≤ 12 V
70
250
9
OS
O
Receiver disabled and
driver enabled
5.5
Receiver disabled and
driver disabled
V = 0 or V
I
,
CC
0.5
8.5
1
I
Supply current
mA
CC
No load
Receiver enabled and driver
enabled
15
†
All typical values are at V
= 5 V and T = 25°C.
A
OC
CC
NOTE 5: ∆|V
| and ∆|V
| are the changes in the steady-state magnitude of V
and V , respectively, that occur when the input is changed
OC
OD
OD
from a high level to a low level.
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
2
TYP
6
MAX
12
12
1
UNIT
ns
t
t
t
t
t
t
t
t
t
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
PLH
PHL
sk(p)
r
2
6
ns
R
= 54 Ω, C = 50 pF,
L
See Figure 3
L
Pulse skew (| t
− t
PLH PHL
|)
0.3
7.5
7.5
12
12
12
12
ns
Differential output signal rise time
4
4
11
ns
Differential output signal fall time
11
ns
f
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
R
R
R
R
= 110 Ω, See Figure 4
= 110 Ω, See Figure 5
= 110 Ω, See Figure 4
= 110 Ω, See Figure 5
22
22
22
22
ns
PZH
PZL
PHZ
PLZ
L
L
L
L
ns
ns
ns
5
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SLLS378C − MAY 2000 − REVISED JUNE 2002
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Positive-going input threshold
voltage
V
V
I
I
= −8 mA
= 8 mA
0.2
V
IT+
O
Negative-going input threshold
voltage
−0.2
V
IT−
O
V
V
V
V
Hysteresis voltage (V
IT+
− V
)
50
−0.8
4.9
mV
V
hys
IT−
Enable-input clamp voltage
High-level output voltage
Low-level output voltage
I = −18 mA
−1.5
4
IK
I
V
= 200 mV,
I
I
= −8 mA
= 8 mA
V
OH
OL
ID
ID
OH
V
= −200 mV,
0.1
0.8
1
V
OL
High-impedance-state output
current
I
V
O
= 0 V to V
CC
−1
µA
OZ
I
I
High-level enable-input current
Low-level enable-input current
V
V
= 2.4 V
= 0.4 V
−100
−100
µA
µA
IH
IH
IL
IL
V = 12 V,
I
0.4
0.5
1
1
V
= 5 V
CC
V = 12 V,
I
V
= 0 V
CC
V = −7 V,
I
Bus input current
Other input at 0 V
mA
mA
I
I
−0.8
−0.8
−0.4
−0.3
V
= 5 V
CC
V = −7 V,
I
V
= 0 V
CC
Receiver enabled and driver disabled
Receiver disabled and driver disabled
Receiver enabled and driver enabled
4.5
0.5
8.5
7.5
1
V = 0 or V
I
,
CC
I
Supply current
CC
No load
15
†
All typical values are at V
= 5 V and T = 25°C.
A
CC
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
7
TYP
13
MAX
20
UNIT
ns
t
t
t
t
t
t
t
t
t
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
PLH
PHL
sk(p)
r
V
ID
= −1.5 V to 1.5 V, See Figure 7
7
13
20
ns
Pulse skew ( t
− t
)
0.5
2.1
2.1
30
1.5
3.3
3.3
45
ns
PHL PLH
Output signal rise time
Output signal fall time
ns
See Figure 7
ns
f
Output enable time to high level
Output enable time to low level
Output disable time from high level
Output disable time from low level
ns
PZH
PZL
PHZ
PLZ
30
45
ns
C
= 10 pF,
See Figure 8
L
20
40
ns
20
40
ns
6
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SLLS378C − MAY 2000 − REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
V
test
R1
375 Ω
27 Ω
Y
Z
V
OD
0 or 3 V
D
R
= 60 Ω
V
OC
V
OD
L
0 V or 3 V
27 Ω
Figure 1. Driver V
and V
OC
OD
R2
375 Ω
−7 V < V
test
< 12 V
V
test
Figure 2. Driver V
OD
3 V
0 V
Input
1.5 V
1.5 V
C
= 50 pF
L
(see Note B)
R
= 54 Ω
L
t
t
PLH
PHL
≈ 1.5 V
10%
Generator
(see Note A)
V
O
50 Ω
90%
50%
Output
3 V
≈ − 1.5 V
t
r
t
f
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3 V
S1
Input
1.5 V 1.5 V
3 V
0 V
0.5 V
t
PZH
R
= 110 Ω
C
= 50 pF
L
L
V
OH
(see Note B)
Generator
(see Note A)
Output
50 Ω
2.3 V
V
off
≈ 0 V
t
PHZ
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
7
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ꢄ ꢍꢎꢏꢐ ꢍꢎꢑꢒ ꢓꢔ ꢕ ꢕꢑ ꢒꢑ ꢁꢖ ꢔ ꢊꢄ ꢄꢔ ꢁ ꢑ ꢓꢒ ꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑꢒ ꢐꢊꢔ ꢒꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
5 V
3 V
0 V
Input
1.5 V
1.5 V
R
= 110 Ω
L
S1
Output
0 V
t
PZL
t
PLZ
C
= 50 pF
L
5 V
0.5 V
Generator
(see Note A)
(see Note B)
50 Ω
2.3 V
Output
V
OL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
I
O
V
ID
V
O
Figure 6. Receiver V
and V
OL
OH
3 V
0 V
Input
1.5 V
1.5 V
Input
Generator
(see Note A)
Output
50 Ω
t
1.5 V
0 V
t
PHL
PLH
C
= 10 pF
(see Note B)
L
V
OH
90%
Output
1.3 V
1.3 V
10%
V
OL
t
t
r
f
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
8
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ꢄꢍ ꢎꢏꢐ ꢍꢎ ꢑꢒ ꢓꢔ ꢕꢕ ꢑꢒ ꢑꢁꢖ ꢔꢊ ꢄ ꢄ ꢔꢁꢑ ꢓꢒꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑ ꢒ ꢐꢊ ꢔꢒ ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
S1
1.5 V
S2
2 kΩ
−1.5 V
5 V
C
= 10 pF
5 kΩ
L
(see Note B)
Input
Generator
(see Note A)
50 Ω
S3
TEST CIRCUIT
3 V
S1 to 1.5 V
S2 Open
3 V
S1 to −1.5 V
S2 Closed
S3 Open
Input
Input
1.5 V
1.5 V
S3 Closed
0 V
0 V
t
PZH
t
PZL
V
OH
≈ 4.5 V
1.5 V
Output
Output
Input
1.5 V
0 V
V
OL
3 V
3 V
S1 to 1.5 V
S2 Closed
S3 Closed
S1 to −1.5 V
S2 Closed
S3 Closed
1.5 V
1.5 V
Input
0 V
0 V
t
PHZ
t
PLZ
≈ 1.3 V
V
OH
0.5 V
Output
0.5 V
Output
V
OL
≈ 1.3 V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ 6 ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 8. Receiver Output Enable and Disable Times
9
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ꢄ ꢍꢎꢏꢐ ꢍꢎꢑꢒ ꢓꢔ ꢕ ꢕꢑ ꢒꢑ ꢁꢖ ꢔ ꢊꢄ ꢄꢔ ꢁ ꢑ ꢓꢒ ꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑꢒ ꢐꢊꢔ ꢒꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
Receiver Output
Driver Input
120 Ω
120 Ω
Driver Input
Receiver Output
Figure 9. Typical Waveform of Nonreturn-to-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at
100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable
TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition
of a logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length
perform quite well even though they do not meet the standard by definition.
10
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ꢄꢍ ꢎꢏꢐ ꢍꢎ ꢑꢒ ꢓꢔ ꢕꢕ ꢑꢒ ꢑꢁꢖ ꢔꢊ ꢄ ꢄ ꢔꢁꢑ ꢓꢒꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑ ꢒ ꢐꢊ ꢔꢒ ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
LOGIC INPUT CURRENT
vs
AVERAGE SUPPLY CURRENT
vs
INPUT VOLTAGE
FREQUENCY
40
35
−30
−25
−20
V
T
A
= 5 V
= 25°C
CC
Driver
R
C
= 54 Ω
= 50 pF
L
L
30
25
V
T
= 5 V
CC
= 25°C
20
15
A
−15
−10
50% Duty Cycle
10
Receiver
C
= 10 pF
0.5
−5
0
L
5
0
0.05
1
2
5
10
20
30
0
1
2
3
4
5
f − Frequency − MHz
V − Input Voltage − V
I
Figure 10
Figure 11
BUS INPUT CURRENT
vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
INPUT VOLTAGE
LOW-LEVEL OUTPUT CURRENT
800
2
V
T
= 5 V
CC
= 25°C
V
T
A
= 5 V
= 25°C
CC
A
1.75
600
400
1.50
1.25
200
1
0
0.75
0.50
−200
−400
−600
0.25
0
0
10
20
30
40
50
60
70
80
−8 −6 −4 −2
0
2
4
6
8
10 12
V − Input Voltage − V
I
I
− Low-Level Output Current − mA
OL
Figure 12
Figure 13
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊ
ꢄ ꢍꢎꢏꢐ ꢍꢎꢑꢒ ꢓꢔ ꢕ ꢕꢑ ꢒꢑ ꢁꢖ ꢔ ꢊꢄ ꢄꢔ ꢁ ꢑ ꢓꢒ ꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑꢒ ꢐꢊꢔ ꢒꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
PROPAGATION DELAY TIME
vs
vs
HIGH-LEVEL OUTPUT CURRENT
CASE TEMPERATURE
5
4.5
4
14
13
T
= 25°C
A
Receiver
V
CC
= 5.25 V
12
V
CC
= 5 V
Driver Tested Per Figure 3
Receiver Tested Per Figure 7
Square Wave Input at 50%
Duty Cycle
3.5
3
11
10
2.5
V
CC
= 5 V
9
8
2
V
CC
= 4.75 V
1.5
1
7
Driver
0.5
0
6
5
0
−10 −20 −30 −40 −50 −60 −70 −80
−50
0
50
100
I
− High-Level Output Current − mA
Case Temperature − C
°
OH
Figure 15
Figure 14
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄ ꢅꢆꢇ ꢈ ꢉ ꢊꢋ ꢀꢁ ꢌꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ
ꢄꢍ ꢎꢏꢐ ꢍꢎ ꢑꢒ ꢓꢔ ꢕꢕ ꢑꢒ ꢑꢁꢖ ꢔꢊ ꢄ ꢄ ꢔꢁꢑ ꢓꢒꢔ ꢗꢑ ꢒ ꢊꢁꢓ ꢒꢑꢆ ꢑꢔꢗ ꢑ ꢒ ꢐꢊ ꢔꢒ ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
APPLICATION INFORMATION
SN65LBC180A
SN75LBC180A
SN65LBC180A
SN75LBC180A
R
T
R
T
Up to 32
Unit Loads
NOTE A: The line should be terminated at both ends in its characteristic impedance (R = Z ). Stub lengths off the main line should be kept
T
O
as short as possible. One SN65LBC180A typically represents less than one unit load.
Figure 16. Typical Application Circuit
13
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ꢄ
ꢍ
ꢎ
ꢏꢐ
ꢍ
ꢎ
ꢑ
ꢒ
ꢓꢔ
ꢕ
ꢕꢑ
ꢒꢑ
ꢁ
ꢖ
ꢔ
ꢊꢄ
ꢄꢔ
ꢁ
ꢑ
ꢓꢒ
ꢔ
ꢗ
ꢑ
ꢒ
ꢊ
ꢁ
ꢓ
ꢒꢑ
ꢆ
ꢑꢔ
ꢗ
ꢑ
ꢒ
ꢐ
ꢊ
ꢔ
ꢒ
ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−ā8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
14
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ꢒ
ꢄ
ꢍ
ꢎꢏꢐ
ꢍ
ꢎ
ꢑ
ꢒ
ꢓ
ꢔ
ꢕꢕ
ꢑꢒ
ꢑꢁ
ꢖ
ꢔꢊ
ꢄ
ꢄ
ꢔ
ꢁ
ꢑ
ꢓꢒ
ꢔ
ꢗ
ꢑ
ꢊꢁ
ꢓ
ꢒ
ꢑ
ꢆ
ꢑꢔ
ꢗ
ꢑ
ꢒ
ꢐ
ꢊ
ꢔ
ꢒ
ꢀ
SLLS378C − MAY 2000 − REVISED JUNE 2002
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.035 (0,89) MAX
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°−ā15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN65LBC180AD
SN65LBC180ADR
SN65LBC180AN
SN75LBC180AD
SN75LBC180ADR
SN75LBC180AN
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
50
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SOIC
PDIP
SOIC
SOIC
PDIP
D
N
D
D
N
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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