SN65LVCP23DRG4 [TI]
2x2 LVPECL CROSSPOINT SWITCH; LVPECL 2×2交叉点开关
| 型号： | SN65LVCP23DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2x2 LVPECL CROSSPOINT SWITCH |
| 文件： | 总19页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVCP23
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
2x2 LVPECL CROSSPOINT SWITCH
FEATURES
DESCRIPTION
•
High Speed 2x2 LVPECL Crosspoint Switch
The SN65LVCP23 is a 2x2 LVPECL crosspoint
switch. The dual channels incorporate wide
common-mode (0 V to 4 V) receivers, allowing for
the receipt of LVDS, LVPECL, and CML signals. The
dual outputs are LVPECL drivers to provide
high-speed operation. The SN65LVCP23 provides a
single device supporting 2:2 buffering (repeating),
1:2 splitting, 2:1 multiplexing, 2x2 switching, and
LVDS/CML to LVPECL level translation on each
channel. The flexible operation of the SN65LVCP23
provides a single device to support the redundant
serial bus transmission needs (working and
protection switching cards) of fault-tolerant switch
systems found in optical networking, wireless
infrastructure, and data communications systems. TI
offers an additional gigabit repeater/translator in the
SN65LVDS101.
•
LVDS Crosspoint Switch Available in
SN65LVCP22
•
•
•
•
50 ps (Typ), of Peak-to-Peak Jitter With
PRBS = 223– 1 Pattern
Output (Channel-to-Channel) Skew Is 10 ps
(Typ), 50 ps (Max)
Configurable as 2:1 Mux, 1:2 Demux,
Repeater or 1:2 Signal Splitter
Inputs Accept LVDS, LVPECL, and CML
Signals
•
•
•
•
Fast Switch Time of 1.7 ns (Typ)
Fast Propagation Delay of 0.75 ns (Typ)
16 Lead SOIC and TSSOP Packages
Operating Temperature: –40°C to 85°C
The SN65LVCP23 uses a fully differential data path
to ensure low-noise generation, fast switching times,
low pulse width distortion, and low jitter. Output
channel-to-channel skew is less than 10 ps (typ) and
50 ps (max) to ensure accurate alignment of outputs
in all applications. Both SOIC and TSSOP package
options are available.
APPLICATIONS
•
Gigabit Ethernet Redundant Transmission
Paths
Gigabit Interface Converters (GBICs)
Fibre Channel Redundant Transmission
Paths
HDTV Video Routing
Base Stations
Protection Switching for Serial Backplanes
Network Switches/Routers
Optical Networking Line Cards/Switches
Clock Distribution
•
•
OUTPUTS OPERATING SIMULTANEOUSLY
•
•
•
•
•
•
1.3 Gbps
23
2
-1 PRBS
OUTPUT 1
V
=
3.3 V
CC
|V | = 200 mV, V
ID IC
= 1.2 V
Vertical Scale = 400 mV/div
OUTPUT 2
650 MHz
Horizontal Scale = 200 ps
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
SN65LVCP23
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE DESIGNATOR
PART NUMBER(1)
SYMBOLIZATION
LVCP23
SOIC
SN65LVCP23D
TSSOP
SN65LVCP23PW
LVCP23
(1) Add the suffix R for taped and reeled carrier
PACKAGE DISSIPATION RATINGS
CIRCUIT
PACKAGE
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
BOARD MODEL
POWER RATING
SOIC (D)
High-K(2)
High-K(2)
1361 mW
13.9 mW/°C
10.7 mW/°C
544 mW
TSSOP (PW)
1074 mW
430 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
UNITS
°C/W
°C/W
°C/W
°C/W
mW
D
15.7
22.1
26.1
17.3
165
θJB
θJC
PD
Junction-to-board thermal resistance
PW
D
Junction-to-case thermal resistance
Device power dissipation
PW
Typical
Maximum
VCC = 3.3 V, TA = 25°C, 2 Gbps
VCC = 3.6 V, TA = 85°C, 2 Gbps
234
mW
FUNCTIONAL BLOCK DIAGRAM
OUT 0
OUT 1
EN 0
EN 1
SEL 1
SEL 0
0
1
0
1
IN 0
IN 1
2
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
CIRCUIT FUNCTION TABLE
INPUTS(1)
OUTPUTS(1)
LOGIC DIAGRAM
IN 0
IN 1
X
SEL 0
X
L
SEL1
X
L
EN 0
L
EN 1
L
OUT 0
L
OUT 1
L
X
>100 mV
<-100 mV
<-100 mV
>100 mV
>100 mV
<-100 mV
>100 mV
<-100 mV
X
H
H
H
H
L
L
H
L
L
EN 0
X
L
L
L
L
IN 0
IN 1
OUT 0
X
L
L
H
H
H
H
L
L
L
X
L
L
H
L
H
H
L
OUT 1
EN 1
X
L
L
X
L
L
L
L
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
L
L
X
L
L
L
EN 0
<-100 mV <-100 mV
<-100 mV >100 mV
>100 mV <-100 mV
L
H
H
H
H
H
H
L
L
L
IN 0
IN 1
OUT 0
L
L
H
L
L
H
H
L
OUT 1
EN 1
>100 mV
>100 mV
>100 mV
<-100 mV
>100 mV
<-100 mV
<-100 mV
>100 mV
>100 mV
<-100 mV
>100 mV
<-100 mV
L
H
H
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
EN 0
L
L
IN 0
IN 1
OUT 0
H
H
H
H
L
L
L
H
L
H
H
L
OUT 1
EN 1
L
L
H
H
H
H
H
H
L
H
L
L
L
L
L
EN 0
<-100 mV <-100 mV
<-100 mV >100 mV
>100 mV <-100 mV
L
H
H
H
H
H
H
L
L
IN 0
IN 1
OUT 0
L
H
L
L
L
H
H
H
L
OUT 1
EN 1
>100 mV
>100 mV
<-100 mV
>100 mV
L
H
L
X
X
L
L
L
L
(1) H = High level, L = Low level, Z = High impedance, X = Don't care
3
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUTS
V
CC
IN +
IN -
400 Ω
SEL, EN
300 kΩ
7 V
7 V
7 V
OUTPUTS
V
V
CC
V
CC
R
CC
R
R
OUT +
V
CC
7 V
OUT -
7 V
4
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
–0.5 V to 4 V
–0.5 V to 4 V
–0.7 V to 4.3 V
–0.5 V to 4 V
50 mA
Supply voltage range,(2) VCC
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1)
Receiver input voltage (IN+, IN–)
LVPECL driver output voltage (OUT+, OUT–)
Continuous
Output current
Surge
100 mA
Storage temperature range
–65°C to 125°C
235°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Continuous power dissipation
See Dissipation Rating Table
±5 kV
Human body model(3)
Charged-device mode(4)
All pins
All pins
Electrostatic discharge
±500 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC
Supply voltage
3
0
3.3
3.6
4
V
V
Receiver input voltage
Junction temperature
Operating free-air temperature(1)
125
85
3
°C
°C
V
TA
|VID
–40
0.1
|
Magnitude of differential input voltage
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
5
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INPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input clamp voltage
2
VCC
V
GND
0.8
±20
±10
–1.5
V
µA
µA
V
VIN = 3.6 V or 2.0 V, VCC = 3.6 V
VIN = 0.0 V or 0.8 V, VCC = 3.6 V
ICL = –18 mA
±3
±1
IIL
VCL
–0.8
LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1)
VOH
VOL
|VOD
CO
Output high voltage
VCC – 1.3
VCC – 2.2
600
VCC – 0.85
VCC – 1.65
1000
V
RL = 50 Ω to VTT
VTT = VCC – 2.0 V, See Figure 2
,
Output low voltage
|
Differential output voltage
Differential output capacitance
800
3
mV
pF
VI = 0.4 sin(4E6πt) + 0.5 V
RECEIVER DC SPECIFICATIONS (IN0, IN1)
VTH
Positive-going differential input voltage threshold See Figure 1 and Table 1
100
mV
mV
mV
V
Negative-going differential input voltage
See Figure 1 and Table 1
threshold
VTL
–100
0.05
VID(HYS) Differential input voltage hysteresis
25
VID = 100 mV,
VCC = 3.0 V to 3.6 V
VCMR
Common-mode voltage range
3.95
VIN = 4 V, VCC = 3.6 V or 0.0 V
VIN = 0 V, VCC = 3.6 V or 0.0 V
VI = 0.4 sin (4E6πt) + 0.5 V
±1
±1
1
±10
±10
IIN
Input current
µA
pF
CIN
Differential input capacitance
SUPPLY CURRENT
ICCD
DC supply current
No load
50
65
mA
(1) All typical values are at 25°C and with a 3.3-V supply.
6
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
tSET
Input to SEL setup time
Input to SEL hold time
Figure 5
Figure 5
Figure 5
Figure 4
Figure 4
1
0.5
0.5
1.7
2
ns
ns
ns
ns
ns
ps
ps
tHOLD
1.1
tSWITCH SEL to switched output
2.5
2.5
2.5
tPHKL
tPKLH
tLHT
Disable time, high-level-to-known LOW
Enable time, known LOW-to-high-level output
Differential output signal rise time (20% – 80%)(1) Figure 3
2
80 110 220
80 110 220
tHLT
Differential output signal fall time (20% – 80%)(1)
Figure 3
VID = 200 mV, 50% duty cycle, VCM = 1.2 V,
650 MHz
15
30
ps
VID = 200 mV, PRBS = 223–1 data pattern
and K28.5 (0011111010),
tJIT
Added peak-to-peak jitter
50 100
ps
VCM = 1.2 V at 1.3 Gbps
VID = 200 mV, 50% duty cycle,
VCM = 1.2 V, 650 MHz
tJrms
Added random jitter (rms)
0.3
0.5 psRMS
tPLHD
tPHLD
tskew
tCCS
Propagation delay time, low-to-high-level output(1) VCC = 3.3 V, TA = 25°C, See Figure 3
Propagation delay time, high-to-low-level output(1) VCC = 3.3 V, TA = 25°C, See Figure 3
400 750 1100
400 750 1100
20 100
ps
ps
Pulse skew (|tPLHD– tPHLD|)(2)
Figure 3
Figure 3
ps
Output channel-to-channel skew, splitter mode
Maximum operating frequency(3)
10
50
ps
fMAX
1
GHz
(1) Input: VIC = 1.2 V, VID = 200 mV, 50% duty cycle, 1 MHz, tr/tf = 500 ps
(2) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
(3) Signal generator conditions: 50% duty cycle, tr or tf ≤ 100 ps (10% to 90%), transmitter output criteria: duty cycle = 45% to 55% VOD
≥
300 mV.
PIN ASSIGNMENTS
D or PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SEL1
SEL0
IN0+
IN0-
VCC
IN1+
IN1-
EN0
EN1
OUT0+
OUT0-
GND
OUT1+
OUT1-
GND
VCC
7
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SLLS554E–NOVEMBER 2002–REVISED MAY 2006
PARAMETER MEASUREMENT INFORMATION
I
IN+
OUT +
IN+
IN-
V
ID
V
OD
V
IN+
V
OY
V
IC
OUT -
IN+ +IN-
2
V
OUT+
+V
2
OUT-
V
OZ
I
IN-
V
IN-
Figure 1. Voltage and Current Definitions
Y
Driver
Device
Receiver
Device
V
OD
Z
50 Ω
50 Ω
V
TT
= V -2 V
CC
Figure 2. Typical Termination for LVPECL Output Driver
OUT+
IN+
50 Ω
1 pF
V
ID
V
OD
V
OUT+
IN-
V
OUT-
TT
V
IN+
50 Ω
V
IN-
V
OUT-
V
TT
V
1.4 V
1 V
IN+
V
IN-
0.4 V
0 V
V
ID
-0.4 V
t
t
PLHD
PHLD
+V
OD
80%
0 V
Vdiff = (OUT+) - (OUT-)
20%
-V
OD
t
t
LHT
HLT
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
8
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PARAMETER MEASUREMENT INFORMATION (continued)
OUT+
1 V or 1.4 V
1.2 V
50 Ω
1 pF
V
OUT+
V
TT
OUT-
EN
V
OUT-
50 Ω
V
TT
3 V
EN
1.5 V
0 V
+V
OD
0 V
-V
OD
Vdiff = (OUT+) - (OUT-)
t
t
PHKL
PKLH
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns, CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
Table 1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
OUTPUT(1)
VIA
VIB
VID
VIC
1.25 V
1.15 V
4.0 V
3.9 V
0.1 V
0.0 V
1.7 V
0.7 V
4.0 V
3.0 V
1.0 V
0.0 V
1.15 V
1.25 V
3.9 V
4. 0 V
0.0 V
0.1 V
0.7 V
1.7 V
3.0 V
4.0 V
0.0 V
1.0 V
100 mV
1.2 V
1.2 V
3.95 V
3.95 V
0.05 V
0.05 V
1.2 V
1.2 V
3.5 V
3.5 V
0.5 V
0.5 V
H
L
–100 mV
100 mV
H
L
–100 mV
100 mV
H
L
–100 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
1000 mV
–1000 mV
H
L
H
L
H
L
(1) H = high level, L = low level
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IN0
IN1
SEL
t
t
HOLD
SET
OUT
EN
IN0
IN1
t
SWITCH
IN0
IN1
SEL
t
t
HOLD
SET
IN1
IN0
OUT
EN
t
SWITCH
NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 5. Input to Select for Both Rising and Falling Edge Setup and Hold Times
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
PEAK-TO-PEAK JITTER
vs
FREQUENCY
FREQUENCY
900
30
100
80
V
V
= 3 − 3.6 V,
CC
= 1.2 V,
V
T
A
= 3.3 V,
CC
= 25°C,
IC
25
|V | = 300 mV
ID
V
= 400 mV,
IC
825
750
Input = 1 MHz
Input = Clock
20
15
10
60
40
t
PLH
800 mV
500 mV
V
T
A
= 3.3 V,
CC
= 25°C,
t
PHL
675
600
V
= 1.2 V,
IC
20
0
5
0
|V | = 200 mV
ID
Output = Loaded
300 mV
0
500
1000
1500
2000
2500
0
100 200 300 400 500 600 700
−60 −40 −20
0
20 40 60 80 100
f − Frequency − MHz
T
A
− Free-Air Temperature − °C
f − Frequency − MHz
Figure 6.
Figure 7.
Figure 8.
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
vs
DATA RATE
FREQUENCY
DATA RATE
30
25
20
15
60
60
50
40
30
20
V
= 3.3 V,
= 25°C,
= 1.2 V
CC
V
= 3.3 V,
CC
= 25°C,
V
= 3.3 V,
CC
= 25°C,
T
A
T
A
T
A
V
50
40
800 mV
IC
V
= 1.2 V,
IC
Input = Clock
V
= 400 mV,
IC
23-
Input = PRBS 2
1
23
800 mV
Input = PRBS 2 −1
300 mV
500 mV
30
800 mV
500 mV
10
20
10
300 mV
500 mV
5
0
10
0
300 mV
0
0
200 400 600 800 1000 1200 1400
0
200 400 600 800 1000 1200 1400
0
100 200 300 400 500 600 700
f − Frequency − MHz
Data Rate − Mbps
Data Rate − Mbps
Figure 9.
Figure 10.
Figure 11.
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
FREQUENCY
DATA RATE
70
60
50
40
30
20
10
30
V
T
V
= 3.3 V,
CC
= 25°C,
300 mV
A
25
20
15
10
5
= 3.3 V,
IC
Input = Clock
500 mV
800 mV
500 mV
V
= 3.3 V,
CC
= 25°C,
T
A
V
= 3.3 V,
IC
800 mV
23
Input = PRBS 2 −1
500 mV
0
0
0
200 400 600 800 1000 1200 1400
0
100 200 300 400 500 600 700
Data Rate − Mbps
f − Frequency − MHz
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
PEAK-TO-PEAK JITTER
vs
vs
FREQUENCY
DATA RATE
900
820
740
660
580
500
50
40
30
20
10
0
230
200
170
140
V
T
V
= 3.3 V,
V
T
V
= 3.3 V,
= 25°C,
= 1.2 V,
CC
= 25°C,
CC
A
A
= 1.2 V,
IC
|V | = 200 mV
IC
|V | = 200 mV
ID
Input = PRBS 2 −1
ID
23
110
80
Added Random Jitter
50
20
0
250 500 750 1000 1250 1500 1750 2000
0
500 1000 1500 2000 2500 3000 3500
f − Frequency − MHz
Data Rate − Mbps
Figure 14.
Figure 15.
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
50 Ω
3.3 V or 5 V
3.3 V
SN65LVCP23
A
B
ECL
50 Ω
50 Ω
50 Ω
V
TT
= V -2 V
CC
V
TT
Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
50 Ω
50 Ω
SN65LVCP23
3.3 V
3.3 V
A
B
CML
50 Ω
3.3 V
Figure 17. Current-Mode Logic (CML)
3.3 V
3.3 V
SN65LVCP23
50 Ω
A
ECL
B
50 Ω
1.1 kΩ
3.3 V
1.5 kΩ
V
TT
= V -2 V
CC
V
TT
Figure 18. Single-Ended (LVPECL)
50 Ω
3.3 V or 5 V
LVDS
3.3 V
SN65LVCP23
A
B
100 Ω
50 Ω
Figure 19. Low-Voltage Differential Signaling (LVDS)
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2006
PACKAGING INFORMATION
Orderable Device
SN65LVCP23D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVCP23DG4
SN65LVCP23DR
SOIC
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVCP23DRG4
SN65LVCP23PW
SN65LVCP23PWG4
SN65LVCP23PWR
SN65LVCP23PWRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
SN65LVCP23DR
D
16
16
SITE 60
SITE 60
6.5
10.3
5.4
2.1
1.6
8
8
16
12
Q1
Q1
SN65LVCP23PWR
PW
330
12
6.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LVCP23DR
D
16
16
SITE 60
SITE 60
346.0
346.0
346.0
346.0
33.0
29.0
SN65LVCP23PWR
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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