SN65LVCP23_14 [TI]
2x2 LVPECL CROSSPOINT SWITCH;
| 型号： | SN65LVCP23_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2x2 LVPECL CROSSPOINT SWITCH |
| 文件： | 总17页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
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FEATURES
DESCRIPTION
D
High Speed 2x2 LVPECL Crosspoint Switch
The SN65LVCP23 is a 2x2 LVPECL crosspoint switch.
The dual channels incorporate wide common-mode (0 V
to 4 V) receivers, allowing for the receipt of LVDS,
LVPECL, and CML signals. The dual outputs are LVPECL
drivers to provide high-speed operation. The
SN65LVCP23 provides a single device supporting 2:2
buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2
switching, and LVDS/CML to LVPECL level translation on
each channel. The flexible operation of the SN65LVCP23
provides a single device to support the redundant serial
bus transmission needs (working and protection switching
cards) of fault-tolerant switch systems found in optical
networking, wireless infrastructure, and data commu-
nications systems. TI offers an additional gigibit repeater/
translator in the SN65LVDS101.
D
LVDS Crosspoint Switch Available in
SN65LVCP22
D
D
D
D
50 ps (Typ), of Peak-to-Peak Jitter
23
With PRBS = 2 –1 Pattern
Output (Channel-to-Channel) Skew Is 10 ps
(Typ), 50 ps (Max)
Configurable as 2:1 Mux, 1:2 Demux,
Repeater or 1:2 Signal Splitter
Inputs Accept LVDS, LVPECL, and CML
Signals
D
D
D
D
Fast Switch Time of 1.7 ns (Typ)
Fast Propagation Delay of 0.75 ns (Typ)
16 lead SOIC and TSSOP Packages
Operating Temperature: −40°C to 85°C
The SN65LVCP23 uses a fully differential data path to
ensure low-noise generation, fast switching times, low
pulse width distortion, and low jitter. Output
channel-to-channel skew is less than 10 ps (typ) and 50 ps
(max) to ensure accurate alignment of outputs in all
applications. Both SOIC and TSSOP package options are
available.
APPLICATIONS
D
Gigabit Ethernet Redundant Transmission
Paths
OUTPUTS OPERATING SIMULTANEOUSLY
D
Gigabit Interface Converters (GBICs)
1.3 Gbps
−1 PRBS
23
2
D
Fibre Channel Redundant Transmission
Paths
OUTPUT 1
V
=
=
3.3 V
1.2 V
CC
|V | = 200 mV, V
D
D
D
D
D
D
HDTV Video Routing
ID
IC
Vertical Scale = 400 mV/div
Base Stations
OUTPUT 2
Protection Switching for Serial Backplanes
Network Switches/Routers
Optical Networking Line Cards/Switches
Clock Distribution
650 MHz
Horizontal Scale = 200 ps
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢇꢌ ꢍ ꢒꢓ ꢆ ꢏꢎ ꢍ ꢁ ꢒ ꢔꢏꢔ ꢕꢖ ꢗꢘ ꢙ ꢚꢛ ꢜꢕꢘꢖ ꢕꢝ ꢞꢟ ꢙ ꢙ ꢠꢖꢜ ꢛꢝ ꢘꢗ ꢡꢟꢢ ꢣꢕꢞ ꢛꢜꢕ ꢘꢖ ꢤꢛ ꢜꢠꢥ ꢇꢙ ꢘꢤꢟ ꢞꢜꢝ
ꢞ ꢘꢖ ꢗꢘꢙ ꢚ ꢜꢘ ꢝ ꢡꢠ ꢞ ꢕ ꢗꢕ ꢞ ꢛ ꢜꢕ ꢘꢖꢝ ꢡ ꢠꢙ ꢜꢦꢠ ꢜꢠ ꢙ ꢚꢝ ꢘꢗ ꢏꢠꢊ ꢛꢝ ꢎꢖꢝ ꢜꢙ ꢟꢚ ꢠꢖꢜ ꢝ ꢝꢜ ꢛꢖꢤ ꢛꢙ ꢤ ꢧ ꢛꢙ ꢙ ꢛ ꢖꢜꢨꢥ
ꢇꢙ ꢘ ꢤꢟꢞ ꢜ ꢕꢘ ꢖ ꢡꢙ ꢘ ꢞ ꢠ ꢝ ꢝ ꢕꢖ ꢩ ꢤꢘ ꢠ ꢝ ꢖꢘꢜ ꢖꢠ ꢞꢠ ꢝꢝ ꢛꢙ ꢕꢣ ꢨ ꢕꢖꢞ ꢣꢟꢤ ꢠ ꢜꢠ ꢝꢜꢕ ꢖꢩ ꢘꢗ ꢛꢣ ꢣ ꢡꢛ ꢙ ꢛꢚ ꢠꢜꢠ ꢙ ꢝꢥ
Copyright 2002−2003, Texas Instruments Incorporated
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PART NUMBER
PACKAGE DESIGNATOR
SYMBOLIZATION
LVCP23
SOIC
SN65LVCP23D
TSSOP
SN65LVCP23PW
LVCP23
(1)
Add the suffix R for taped and reeled carrier
PACKAGE DISSIPATION RATINGS
(1)
CIRCUIT
T
A
≤ 25°C
DERATING FACTOR
T = 85°C
A
POWER RATING
PACKAGE
BOARD MODEL POWER RATING
ABOVE T = 25°C
A
(2)
SOIC (D)
High-K
1361 mW
1074 mW
13.9 mW/°C
10.7 mW/°C
544 mW
(2)
High-K
TSSOP (PW)
430 mW
(1)
(2)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
15.7
22.1
26.1
17.3
165
UNITS
°C/W
°C/W
°C/W
°C/W
mW
D
θ
θ
Junction-to-board thermal resistance
Junction-to-case thermal resistance
Device power dissipation
JB
PW
D
JC
PW
Typical
Maximum
V
V
= 3.3−V, T = 25°C, 2 Gbps
A
CC
P
D
= 3.6−V, T = 85°C, 2 Gbps
234
mW
CC
A
FUNCTION TABLE
SEL0
SEL1
OUT0
IN0
OUT1
IN0
FUNCTION
1:2 Splitter
Repeater
Switch
0
0
1
1
0
1
0
1
IN0
IN1
IN1
IN0
IN1
IN1
1:2 Splitter
FUNCTIONAL BLOCK DIAGRAM
OUT 0
OUT 1
EN 0
EN 1
SEL 1
SEL 0
0
1
0
1
IN 0
IN 1
2
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUTS
V
CC
IN +
IN −
400 Ω
300 kΩ
7 V
SEL, EN
7 V
7 V
OUTPUTS
V
V
CC
V
CC
R
CC
R
R
OUT +
V
CC
7 V
OUT −
7 V
3
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNITS
(2)
Supply voltage range, V
CC
−0.5 V to 4 V
−0.5 V to 4 V
−0.7 V to 4.3 V
−0.5 V to 4 V
50 mA
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1)
Receiver Input voltage (IN+, IN−)
LVPECL driver output voltage (OUT+, OUT−)
Continuous
Output current
Surge
100 mA
Storage temperature range
−65°C to 125°C
235°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Continuous power dissipation
See Dissipation Rating Table
5 kV
(3)
Human body model
All pins
All pins
Electrostatic discharge
(4)
Charged-device mode
500 V
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(2)
(3)
(4)
Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, V
CC
3
0
3.3
3.6
4
V
V
Receiver input voltage
Junction temperature
125
85
3
°C
°C
V
(1)
Operating free-air temperature, T
−40
0.1
A
Magnitude of differential input voltage |V
|
ID
(1)
Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
4
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
INPUT ELECTRICAL CHARACTERISTICS
over recommended operatingconditions unless otherwise noted
(1)
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
V
V
High-level input voltage
Low-level input voltage
2
V
CC
0.8
V
V
IH
GND
IL
V
= 3.6 V or 2.0 V,
IN
I
High-level input current
3
1
20
10
µA
IH
IL
Vcc = 3.6 V
V
= 0.0 V or 0.8 V,
IN
Vcc = 3.6 V
I
Low-level input current
Input clamp voltage
µA
V
I
= −18 mA
−0.8
−1.5
V
CL
CL
LVPECL OUTPUT SPECIFICATIONS (OUT0, OUT1)
V
V
Output high voltage
V
V
− 1.3
− 2.2
600
V
V
− 0.85
− 1.65
1000
OH
CC
CC
R
V
= 50 Ω to V
L
TT;
V
Output low voltage
= V
− 2.0 V,
OL
CC
CC
TT
CC
See Figure 2
V
C
Differentialoutput voltage
Differential output capacitance
800
3
mV
pF
OD
V = 0.4 sin(4E6πt) + 0.5 V
I
O
RECEIVER DC SPECIFICATIONS (IN0, IN1)
V
V
Positive-going differential input voltage threshold See Figure 1 and Table 1
Negative-going differential input voltage threshold See Figure 1 and Table 1
Differential input voltage hysteresis
100
mV
mV
mV
TH
−100
0.05
TL
V
25
ID(HYS)
V
ID
= 100 mV,
V
CMR
Common-mode voltage range
3.95
V
V
CC
= 3.0 V to 3.6 V
V
= 4 V, V
= 3.6 V or 0.0
= 3.6V or 0.0
1
1
1
10
10
IN
IN
CC
I
Input current
µA
IN
V
= 0V, V
CC
C
Differential input capacitance
V = 0.4 sin (4E6πt) + 0.5 V
I
pF
IN
SUPPLY CURRENT
I
DC supply current
No load
50
65
mA
CCD
(1)
All typical values are at 25°C and with a 3.3 V supply.
5
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SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
1
TYP
0.5
0.5
1.7
2
MAX
UNIT
t
t
Input to SEL setup time
Figure 5
Figure 5
Figure 5
Figure 4
Figure 4
Figure 3
Figure 3
ns
ns
ns
ns
ns
ps
ps
SET
Input to SEL hold time
1.1
HOLD
t
SEL to switched output
2.5
2.5
SWITCH
t
Disable time, high-level-to-known LOW
Enable time, known LOW-to-high-level output
Differential output signal rise time (20%−80%)
PHKL
PKLH
LHT
t
t
t
2
2.5
(1)
(1)
80
80
110
110
220
220
Differential output signal fall time (20%−80%)
HLT
V
= 200 mV, 50% duty cycle, V = 1.2 V,
CM
ID
650 MHz
15
30
ps
23
= 200 mV, PRBS = 2 −1 data pattern
t
Added peak−to-peak jitter
V
JIT
ID
and K28.5 (0011111010),
50
100
ps
V
CM
= 1.2 V at 1.3 Gbps
V
= 200 mV, 50% duty cycle, V
= 1.2 V,
CM
ID
t
Added random jitter (rms)
0.3
0.5 ps
RMS
Jrms
650 MHz
(1)
(1)
t
t
t
t
f
Propagation delay time, low-to-high-level output
V
V
= 3.3 V,
T = 25°C, See Figure 3
A
400
400
750
750
20
1100
1100
100
50
ps
ps
PLHD
PHLD
skew
CCS
MAX
CC
Propagation delay time, high-to-low-level output
= 3.3 V, T = 25°C, See Figure 3
CC
A
(2)
Pulse skew (|t
− t
|)
Figure 3
Figure 3
ps
PLHD PHLD
Output channel-to-channel skew, splitter mode.
(3)
10
ps
Maximum operating frequency
1
GHz
(1)
(2)
(3)
Input: V = 1.2 V, V = 200 mV, 50% duty cycle, 1 MHz, t /t = 500 ps
IC
ID
r f
t
is the magnitude of the time difference between the t
and t
of any output of a single device.
transmitter output criteria: duty cycle = 45% to 55% V
OD
skew
PLHD
PHLD
Signal generator conditions: 50% duty cycle, t or t ꢀ 100 ps
ꢁ
3
0
0
m
V
.
r
f
(10% to 90%),
PIN ASSIGNMENTS
D or PW PACKAGE
(TOP VIEW)
1
16
15
14
13
12
11
10
9
SEL1
SEL0
IN0+
IN0−
VCC
IN1+
IN1−
VCC
EN0
EN1
2
3
4
5
6
7
8
OUT0+
OUT0−
GND
OUT1+
OUT1−
GND
6
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PARAMETER MEASUREMENT INFORMATION
I
IN+
OUT +
OUT −
IN+
IN−
V
ID
V
OD
V
IN+
V
OY
V
IC
IN+ +IN−
2
V
+V
OUT+ OUT−
2
V
OZ
I
IN−
V
IN−
Figure 1. Voltage and Current Definitions
Y
Driver
Device
Receiver
Device
V
OD
Z
50 Ω
50 Ω
V
TT
= V
CC
−2 V
Figure 2. Typical Termination for LVPECL Output Driver
OUT+
IN+
50 Ω
1 pF
V
ID
V
OD
V
OUT+
IN−
V
OUT−
TT
V
IN+
50 Ω
V
IN−
V
OUT−
V
TT
V
1.4 V
1 V
IN+
V
IN−
0.4 V
0 V
V
ID
−0.4 V
t
t
PLHD
PHLD
+V
−V
OD
80%
0 V
Vdiff = (OUT+) − (OUT−)
20%
OD
t
t
LHT
HLT
:
NOTE All input pulses are supplied by a generator having the following characteristics: t or t ≤ 0.25 ns, pulse-repetition rate (PRR) = 0.5 Mpps,
r
f
pulse width = 500 10 ns; C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 3. Timing Test Circuit and Waveforms
7
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OUT+
OUT−
1 V or 1.4 V
1.2 V
50 Ω
1 pF
V
OUT+
V
TT
EN
V
50 Ω
TT
OUT−
V
3 V
EN
1.5 V
0 V
+V
−V
OD
0 V
OD
Vdiff = (OUT+) − (OUT−)
t
t
PKLH
PHKL
:
NOTE All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse
r
f
width = 500 10 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 4. Enable and Disable Time Circuit and Definitions
Table 1. Receiver Input Voltage Threshold Test
RESULTING DIFFERENTIAL RESULTING COMMON-
APPLIED VOLTAGES
OUTPUT
INPUT VOLTAGE
MODE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V
1.15 V
4.0 V
3.9 V
0.1 V
0.0 V
1.7 V
0.7 V
4.0 V
3.0 V
1.0 V
0.0 V
1.15 V
1.25 V
3.9 V
4. 0 V
0.0 V
0.1 V
0.7 V
1.7 V
3.0 V
4.0 V
0.0 V
1.0 V
100 mV
−100 mV
100 mV
1.2 V
1.2 V
3.95 V
3.95 V
0.05 V
0.05 V
1.2 V
1.2 V
3.5 V
3.5 V
0.5 V
0.5 V
H
L
H
L
−100 mV
100 mV
H
L
−100 mV
1000 mV
−1000 mV
1000 mV
−1000 mV
1000 mV
−1000 mV
H
L
H
L
H
L
H = high level, L = low level
8
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IN0
IN1
SEL
t
t
HOLD
SET
OUT
EN
IN0
IN1
t
SWITCH
IN0
IN1
SEL
t
t
HOLD
SET
IN1
IN0
OUT
EN
t
SWITCH
:
NOTE
t
and t times specify that data must be in a stable state before and after mux control switches.
HOLD
SET
Figure 5. Input to Select for Both Rising and Falling Edge Setup and Hold Times
9
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TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
PEAK-TO-PEAK JITTER
vs
FREQUENCY
FREQUENCY
900
825
30
25
100
80
V
V
= 3 − 3.6 V,
= 1.2 V,
Cc
IC
V
T
V
= 3.3 V,
CC
= 25°C,
A
IC
|V | = 300 mV
ID
= 400 mV,
Input = 1 MHz
Input = Clock
20
15
10
60
40
750
t
PLH
800 mV
500 mV
V
T
V
= 3.3 V,
= 1.2 V,
IC
t
CC
PHL
= 25°C,
675
600
A
20
0
5
0
|V | = 200 mV
Output = Loaded
ID
300 mV
−60 −40 −20
0
20 40 60 80 100
0
100 200 300 400 500 600 700
0
500
1000
1500
2000
2500
T
A
− Free-Air Temperature − °C
f − Frequency − MHz
f − Frequency − MHz
Figure 6
Figure 7
Figure 8
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
vs
vs
vs
DATA RATE
FREQUENCY
DATA RATE
60
30
25
20
15
60
V
= 3.3 V,
CC
V = 3.3 V,
CC
T = 25°C,
V = 1.2 V,
IC
Input = Clock
V
= 3.3 V,
CC
T
= 25°C,
A
T
= 25°C,
A
A
V
= 1.2 V
Input = PRBS 2
50
40
800 mV
50
40
30
20
IC
V
= 400 mV,
IC
23-
1
23
800 mV
Input = PRBS 2 −1
300 mV
500 mV
30
800 mV
500 mV
10
20
10
300 mV
500 mV
5
0
10
0
300 mV
0
0
200 400 600 800 1000 1200 1400
0
200 400 600 800 1000 1200 1400
0
100 200 300 400 500 600 700
Data Rate − Mbps
f − Frequency − MHz
Data Rate − Mbps
Figure 9
Figure 10
Figure 11
PEAK-TO-PEAK JITTER
PEAK-TO-PEAK JITTER
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
vs
FREQUENCY
DATA RATE
FREQUENCY
30
70
900
820
740
660
580
500
50
40
30
20
10
0
V
T
V
= 3.3 V,
= 25°C,
= 3.3 V,
Input = Clock
V
T
= 3.3 V,
CC
A
IC
CC
= 25°C,
60
50
40
30
20
10
0
300 mV
A
25
20
15
10
5
V
= 1.2 V,
IC
|V | = 200 mV
ID
500 mV
800 mV
500 mV
Added Random Jitter
V
T
V
= 3.3 V,
= 3.3 V,
CC
= 25°C,
A
IC
800 mV
23
500 mV
Input = PRBS 2 −1
0
0
100 200 300 400 500 600 700
0
200 400 600 800 1000 1200 1400
0
250 500 750 1000 1250 1500 1750 2000
Data Rate − Mbps
f − Frequency − MHz
f − Frequency − MHz
Figure 12
Figure 13
Figure 14
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PEAK-TO-PEAK JITTER
vs
DATA RATE
230
200
170
140
V
= 3.3 V,
= 1.2 V,
|V | = 200 mV
23
Input = PRBS 2 −1
CC
= 25°C,
T
A
V
IC
ID
110
80
50
20
0
500 1000 1500 2000 2500 3000 3500
Data Rate − Mbps
Figure 15
11
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www.ti.com
SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, ETC.)
50 Ω
3.3 V or 5 V
ECL
3.3 V
SN65LVCP23
A
B
50 Ω
50 Ω
50 Ω
V
TT
= V −2 V
CC
V
TT
Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
3.3 V
50 Ω
50 Ω
50 Ω
SN65LVCP23
3.3 V
3.3 V
A
B
CML
50 Ω
3.3 V
Figure 17. Current-Mode Logic (CML)
3.3 V
3.3 V
SN65LVCP23
50 Ω
A
B
ECL
50 Ω
1.1 kΩ
3.3 V
1.5 kΩ
V
TT
= V −2 V
CC
V
TT
Figure 18. Single-Ended (LVPECL)
50 Ω
3.3 V or 5 V
LVDS
3.3 V
SN65LVCP23
A
B
100 Ω
50 Ω
Figure 19. Low-Voltage Differential Signaling (LVDS)
12
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SLLS554C − NOVEMBER 2002 − REVISED SEPTEMBER 2004
IN0 +
IN0 −
IN1 +
OUT0 +
OUT0 −
OUT1 +
OUT1 −
IN1 −
Figure 20. 2 x 2 Crosspoint
OUT0 +
OUT0 −
IN +
IN −
(1 or 2)
OUT1 +
OUT1 −
Figure 21. 1:2 Spitter
OUT0 +
IN0 +
IN0 −
IN1 +
OUT0 −
OUT1 +
OUT1 −
IN1 −
Figure 22. Dual Repeater
IN0 +
IN0 −
IN1 +
OUT +
MUX
(1 or 2)
OUT −
IN1 −
Figure 23. 2:1 MUX
13
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN65LVCP23D
SN65LVCP23DR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVCP23PW
SN65LVCP23PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
90
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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