SN65LVCP404RGZRG4 [TI]
Gigabit 4x4 CROSSPOINT SWITCH; 千兆4×4交叉点开关
| 型号： | SN65LVCP404RGZRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Gigabit 4x4 CROSSPOINT SWITCH |
| 文件： | 总21页 (文件大小：1345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVCP404
www.ti.com
SLLS700–MARCH 2007
Gigabit 4x4 CROSSPOINT SWITCH
FEATURES
DESCRIPTION
•
Up to 4.25 Gbps Operation
The SN65LVCP404 is a 4x4 non-blocking crosspoint
switch in a flow-through pin-out allowing for ease in
PCB layout. VML signaling is used to achieve a
high-speed data throughput while using low power.
Each of the output drivers includes a 4:1 multiplexer
to allow any input to be routed to any output. Internal
signal paths are fully differential to achieve the high
signaling speeds while maintaining low signal skews.
The SN65LVCP404 incorporates 100-Ω termination
resistors for those applications where board space is
•
Non-blocking Architecture Allows Each
Output to be Connected to Any Input
•
•
•
•
•
•
30 ps of Deterministic Jitter
Selectable Transmit Pre-Emphasis Per Lane
Selectable Receive Equalization
Available Packaging 48 Pin QFN
Propagation Delay Times: 500 ps Typical
a
premium. Built-in transmit pre-emphasis and
Inputs Electrically Compatible With
CML Signal Levels
receive equalization for superior signal integrity
performance.
•
•
•
•
Operates From a Single 3.3-V Supply
Ability to 3-STATE ouputs
The SN65LVCP404 is characterized for operation
from -40°C to 85°C.
Low Power: 560 mW
Integrated Termination Resistors
APPLICATIONS
1
2
3
4
5
6
7
8
36
35
34
33
P22
P21
2Y
S20
S21
1A
•
•
•
•
•
Clock Buffering/Clock MUXing
Wireless Base Stations
High-Speed Network Routing
Telecom/Datacom
XAUI 802.3ae Protocol Backplane
Redundancy
2Z
1B
32
31
30
29
28
27
GND
3Y
GND
2A
3Z
2B
VCC
4Y
VCC
3A
9
4Z
10
11
12
3B
26
GND
EQ
25 4DE
VBB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN65LVCP404
www.ti.com
SLLS700–MARCH 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
LOGIC DIAGRAM
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
High Speed I/O
Differential Inputs (with 50-Ω
termination to Vbb)
xA=P; xB=N
xA
xB
3, 6, 9, 16
4, 7, 10, 17
Line Side Differential Inputs CML compatible
Switch Side Differential Outputs. VML
xY
xZ
41, 34, 31, 28
40, 33, 30, 27
Differential Output xY=P; xZ=N
Control Signals
Data Enable; Active Low; LVTTL; When not enabled the ouput
is in 3-STATE mode for power savings
xDE
45, 38, 37, 25
Input
1, 2, 13, 14, 19,
20, 47, 48
S10 - S41
P11-P42
EQ
Input; S1x = Channel 1 bit one
Input; P1x- Channel 1 bit one
Switching Selection; LVTTL
43, 44, 35, 36, 23,
24, 21, 22
Output Preemphasis Control; LVTTL
Input; Selection for receive
equalization setting
EQ = 1 (default) is for the 5 dB setting, EQ = 0 is for the 12 dB
setting
11
Power
Supply
VCC
GND
8, 18, 29, 39, 46 Power
5, 15, 26, 32, 42
Power Supply 3.3v ±5%
The ground center pad of the package must be connected to
GND plane.
Power Pad
VBB
12
Input
Receiver input biasing voltage
2
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SLLS700–MARCH 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
IN+
R
T(SE)
= 50 W
Gain
Stage
+ EQ
VCC
RBBDC
VBB
R
T(SE)
= 50 W
IN−
LineEndTermination
ESD Self−Biasing Network
Figure 1. Equivalent Input Circuit Design
49.9 W
49.9 W
OUT+
OUT−
V
OCM
1 pF
Figure 2. Common-Mode Output Voltage Test Circuit
Table 1. CROSSPOINT LOGIC TABLES
OUTPUT CHANNEL 1
OUTPUT CHANNEL 2
OUTPUT CHANNEL 3
OUTPUT CHANNEL 4
CONTROL
PINS
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
CONTROL
PINS
INPUT
SELECTED
S10
0
S11
0
1Y/1Z
1A/1B
2A/2B
3A/3B
4A/4B
S20
0
S21
0
2Y/2Z
1A/1B
2A/2B
3A/3B
4A/4B
S30
S31
3Y/3Z
S40
0
S41
0
4Y/4Z
1A/1B
2A/2B
3A/3B
4A/4B
0
0
1A/1B
0
1
0
1
0
1
1
1
0
1
2A/2B
0
1
1
0
1
0
3A/3B
1
0
1
1
1
1
4A/4B
1
1
AVAILABLE OPTIONS
PACKAGED DEVICE(1)
RGZ (48 pin)
TA
DESCRIPTION
-40°C to 85°C
Serial multiplexer
SN65LVCP404
(1) The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP404RGZR).
3
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SLLS700–MARCH 2007
PACKAGE THERMAL CHARACTERISTICS
PACKAGE THERMAL CHARACTERISTICS(1)
NOM
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θJA (junction-to-ambient)
33
20
θJB (junction-to-board)
4-layer JEDEC Board (JESD51-7) using eight GND-vias θ-0.2 on the
θJC (junction-to-case)
23.6
0.6
center pad as shown in the section: Recommended PCB footprint
with boundary and environment conditions of JEDEC Board
(JESD51-2)
PSI-jt (junction-to-top pseudo)
PSI-jb (junction-to-board pseudo)
θJP (junction-to-pad)
19.4
5.4
(1) See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
Supply voltage range(2)
Voltage range
–0.5 V to 6 V
–0.5 V to (VCC + 0.5 V)
–0.5 V to 4 V
3 kV
Control inputs, all outputs
Receiver inputs
All pins
Human Body Model(3)
Charged-Device Model(4)
ESD
All pins
500 V
See Package Thermal Characteristics
Table
TJ
Maximum junction temperature
Moisture sensitivity level
2
Reflow temperature package soldering, 4 seconds
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
4
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SLLS700–MARCH 2007
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
4.25
3.465
20
UNIT
Gbps
V
dR
Operating data rate
VCC
VCC(N)
TJ
Supply voltage
3.135
3.3
Supply voltage noise amplitude
Junction temperature
10 Hz to 2.125 GHz
mV
°C
125
85
TA
Operating free-air temperature(1)
-40
°C
DIFFERENTIAL INPUTS
dR(in) ≤ 4.25 Gbps
100
100
100
1750
1560
1000
mVPP
mVPP
mVPP
Receiver peak-to-peak differential input
VID
1.25 Gbps < dR(in) ≤ 4.25 Gbps
dR(in) > 4.25 Gbps
voltage(2)
Receiver common-mode
input voltage
Note: for best jitter performance ac
coupling is recommended.
|V
*
|
ID
VICM
1.5
1.6
V
V
CC
2
CONTROL INPUTS
VIH
VIL
High-level input voltage
Low-level input voltage
2
VCC + 0.3
0.8
V
V
–0.3
DIFFERENTIAL OUTPUTS
RL Differential load resistance
80
100
120
Ω
(1) Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded.
(2) Differential input voltage VID is defined as | IN+ – IN– |.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
DIFFERENTIAL INPUTS
Positive going differential
input high threshold
VIT+
50
mV
Negative going differential
input low threshold
VIT–
–50
80
mV
dB
Ω
A(EQ)
RT(D)
Equalizer gain
at 1.875 GHz (EQ=0)
12
Termination resistance,
differential
100
120
Open-circuit Input voltage
(input self-bias voltage)
VBB
AC-coupled inputs
1.6
30
V
Biasing network dc
impedance
R(BBDC)
kΩ
375 MHz
42
Biasing network ac
impedance
R(BBAC)
Ω
2.125 GHz
8.4
DIFFERENTIAL OUTPUTS
VODH
VODL
High-level output voltage
650
mVPP
mVPP
RL = 100 Ω±1%,
Px_2 = Px_1=0;
Low-level output voltage
–650
4 Gbps alternating 1010-pattern;
Figure 3
Output differential voltage
without preemphasis(2)
VODB(PP)
VOCM
1000
1300
1.65
1500
mVPP
V
Output common mode voltage
Change in steady-state
∆VOC(SS) common-mode output voltage
See Figure 2
1
mV
between logic states
(1) All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not
production tested.
(2) Differential output voltage V(ODB) is defined as | OUT+ – OUT– |.
5
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Output preemphasis voltage
ratio,
Px_2:Px_1 = 00
0
3
6
Px_2:Px_1 = 01
Px_2:Px_1 = 10
RL = 100 Ω± 1%;
x = L or S;
See Figure 3
V(PE)
dB
V
ODB(PP)
V
Px_2:Px_1 = 11
9
175
100
ODPE(PP)
Output preemphasis is set to 9 dB during test
Px_x = 1;
Measured with a 100-MHz clock signal;
RL = 100 Ω± 1%, See Figure 4
Preemphasis duration
measurement
t(PRE)
ps
Differential on-chip termination between OUT+ and
OUT–
ro
Output resistance
Ω
CONTROL INPUTS
IIH
High-level Input current
VIN = VCC
VIN = GND
5
µA
µA
kΩ
IIL
Low-level Input current
Pullup resistance
-125
-90
35
R(PU)
POWER CONSUMPTION
PD
Device power dissipation
All outputs terminated 100 Ω
560
750
600
mW
mW
Device power dissipation in
3-State
PZ
All outputs in 3-state
All outputs
terminated 100 Ω
PRBS 27-1 pattern at 4.25
Gbps
ICC
Device current consumption
220
mA
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MULTIPLEXER
t(SM) Multiplexer switch time
DIFFERENTIAL OUTPUTS
Low-to-high propagation
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
Multiplexer to valid output
3
6
ns
tPLH
0.5
0.5
0.7
0.7
ns
ns
delay
Propagation delay input to output
See Figure 6
High-to-low propagation
delay
tPHL
tr
Rise time
80
80
ps
ps
ps
ps
ps
ns
20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal;
See Figure 5 and Figure 8
tf
Fall time
(2)
tsk(p)
tsk(o)
tsk(pp)
tzd
Pulse skew, | tPHL– tPLH
Output skew(3)
Part-to-part skew(4)
|
20
100
300
20
All outputs terminated with 100 Ω
25
3-State switch time to
Disable
Assumes 50 Ohm to Vcm and 150 pF load on each output
Assumes 50 Ohm to Vcm and 150 pF load on each output
tze
3-State switch time to
Enable
10
2
ns
See Figure 8 for test circuit.
BERT setting 10–15
RJ
Device random jitter, rms
0.8
ps-rms
Alternating 10-pattern.
(1) All typical values are at 25°C and with 3.3 V supply unless otherwise noted.
(2) tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
(3) tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device.
(4) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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SWITCHING CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
0 dB preemphasis
(PREx_x = 0);
See Figure 8 for the test
circuit.
Intrinsic deterministic
PRBS 27-1
pattern
(5)(6)
device jitter
,
4.25 Gbps
30
ps
peak-to-peak
1.25Gbps;
EQ=1
Over 25-inch
FR4 trace
7
DJ
0 dB preemphasis
(PREx_x = 0);
Absolute deterministic
PRBS 27-1
pattern
4.25 Gbps;
EQ=0
ps
output jitter(7), peak-to-peak See Figure 8 for the test
circuit.
Over FR4
trace 2-inch
to 43 inches
long
20
(5) Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation
(DJ(OUT)– DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in PSPP. DJ(IN) is the
peak-to-peak deterministic jitter of the pattern generator driving the device.
(6) The SN65LVCP404 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the
LVCP404 typically reduces jitter by 60 ps from the device input to the device output.
(7) Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP404 output. The value is a real measured
value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated
over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP404))
.
Table 2. Preemphasis Controls PL_2, PL_1, PS_2, and PS_1
OUTPUT
PREEMPHASIS
LEVEL IN dB
OUTPUT LEVEL IN mVpp
TYPICAL FR4
TRACE LENGTH
Px_2(1)
Px_1(1)
DE-EMPHASIZED
PRE-EMPHASIZED
0
0
1
1
0
1
0
1
0 dB
3 dB
6 dB
9 dB
1200
850
600
425
1200
1200
1200
1200
10 inches of FR4 trace
20 inches of FR4 trace
30 inches of FR4 trace
40 inches of FR4 trace
(1) x = L or S
Table 3. Receive Equalization Settings
EQ
EQUALIZATION
5 dB
TYPICAL TRACE
25 inches of FR4
43 inches of FR4
1
0
12 dB
7
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SLLS700–MARCH 2007
PARAMETER MEASUREMENT INFORMATION
1−bit
1 to N bit
0−dB Preemphasis
3−dB Preemphasis
6−dB Preemphasis
V
V
OH
9−dB Preemphasis
V
OCM
OL
V
ODB(PP)
Figure 3. Preemphasis and Output Voltage Waveforms and Definitions
1−bit
1 to N bit
9−dB Preemphasis
V
ODB(PP)
80%
20%
tPRE
Figure 4. t(PRE) Preemphasis Duration Measurement
80%
80%
V
ODB
20%
20%
t
t
f
r
Figure 5. Driver Output Transition Time
8
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SLLS700–MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
V
ID
= 0 V
IN
t
t
PLHD
PHLD
V
OD
= 0 V
OUT
Figure 6. Propagation Delay Input to Output
V
A
0 V
Clock Input
0 V
Ideal Output
V
B
V
Y
− V
Z
1/fo
1/fo
Period Jitter
Cycle-to-Cycle Jitter
Actual Output
0 V
Actual Output
V
0 V
− V
V
Y
− V
Z
Y
Z
t
t
t
c(n +1)
c(n)
c(n)
t
= | t
− t
c(n + 1)
|
t
= | t
− 1/fo |
jit(cc)
c(n)
jit(pp)
c(n)
Peak-to-Peak Jitter
V
A
V
Y
PRBS Input
0 V
0 V
PRBS Output
V
B
V
Z
t
jit(pp)
A. All input pulses are supplied by an Agilent 81250 Stimulus System.
B. The measurement is made with the AgilentParBert measurement software.
Figure 7. Driver Jitter Measurement Waveforms
<3-inch 50 W TL
(7,62 cm)
25-inch FR4
(63,5 cm)
<3-inch 50 W TL
(7,62 cm)
Figure 8. AC Test Circuit — Jitter and Output Rise Time Test Circuit
The SN65LVCP404 input equalizer provides 5-dB frequency gain to compensate for frequency loss of a shorter
backplane transmission line. For characterization purposes, a 25-inch (63,5 cm) FR-4 coupled transmission line
is used in place of the backplane trace. The 25-inch trace provides roughly 5 dB of attenuation between 375
MHz and 2.125 GHz, representing closely the characteristics of a short backplane trace. The loss tangent of the
FR4 in the test board is 0.018 with an effective ε(r) of 4.1.
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TYPICAL DEVICE BEHAVIOR
Eye After 51 inch FR-4 Trace, Input 800 mVPP
Eye After 51 inch FR-4 Trace, Input 800 mVPP
,
Through the 404 With Pre-emphasis at 3 dB
100 ps/div
Pre-emphasis Levels
50 ps/div
Figure 10. Preemphasis Signal Shape
NOTE: 51 Inches (129.54 cm) Input Trace, dR =
4.25 Gbps; 27- 1 PRBS
Figure 9. Data Input and Output Pattern
35-inches,
88.9 cm FR4
4.25 Gbps
Signal
Generator
51-inches,
129.54 cm FR4
7-1
PRBS 2
800 mV Input
PP
35-inches,
88.9 cm FR4
Figure 11. Data Output Pattern
10
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TYPICAL CHARACTERISTICS
DETERMINISTIC OUTPUT JITTER
DETERMINISTIC OUTPUT JITTER
vs
DIFFERENTIAL INPUT AMPLITUDE
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
DATA RATE
DATA RATE
1.4
50
25
4.25 Gbps
7-1
2
PRBS pattern,
45
40
35
30
1.2
1
The DJ is Measured on the Output of the
LVCP404
20
15
3.75 Gbps
3.125 Gbps
0.8
2.5 Gbps
25
20
15
10
0.6
10
0.4
0.2
0
5
0
1.25 Gbps
1500
5
0
0
0
1
2
3
4
5
6
7
8
500
1000
2000
0
1
2
3
4
5
6
7
8
DR - Data Rate - Gbps
Figure 12.
Figure 13.
Figure 14.
SUPPLY NOISE vs DETERMINISTIC
JITTER
vs
DETERMINISTIC OUTPUT JITTER
vs
COMMON-MODE INPUT VOLTAGE
DATA RATE
35
25
Noise = 200 mV
Noise = 650 mV
Noise = 300 mV
30
25
20
15
4.25 Gbps
20
Noise = 100 mV
Noise = 50 mV
15
10
10
5
Noise = 400 mV
5
0
0
1
2.5
3
5000
0
0.5
2
4000
0
3000
1.5
- Common Mode Input Voltage - V
1000
2000
V
DR - Data Rate - Gbps
IC
Figure 15.
Figure 16.
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APPLICATION INFORMATION
CONFIGURATION EXAMPLES
S10
0
S30
1
S11
0
S31
0
S20
0
S40
1
S21
S10
0
S30
0
S11
0
S31
0
S20
0
S40
0
S21
0
S41
0
1
S41
1
1Y
1Z
1A
1B
1Y
1A
1B
1Z
2Y
2Z
2A
2B
2Y
2Z
3Y
3Z
3A
3B
3Y
3Z
4Y
4Z
4Y
4Z
4A
4B
S10
0
S11
0
S20
0
S21
0
S10
1
S11
1
S20
1
S21
1
S30
1
S31
0
S40
1
S41
0
S30
0
S31
0
S40
0
S41
0
1A
1B
1Y
1Z
1A
1B
1Y
1Z
2Y
2Z
2Y
2Z
3Y
3Z
3A
3B
3Y
3Z
4Y
4Z
4A
4B
4Y
4Z
12
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APPLICATION INFORMATION (continued)
BANDWIDTH REQUIREMENTS
Error free transmission of data over a transmission line has specific bandwidth demands. It is helpful to analyze
the frequency spectrum of the transmit data first. For an 8B10B coded data stream at 3.75 Gbps of random
data, the highest bit transition density occurs with a 1010 pattern (1.875 GHz). The least transition density in
8B10B allows for five consecutive ones or zeros. Hence, the lowest frequency of interest is 1.875 GHz/5 = 375
MHz. Real data signals consist of higher frequency components than sine waves due to the fast rise time. The
faster the rise time, the more bandwidth becomes required. For 80-ps rise time, the highest important frequency
component is at least 0.6/(π × 80 ps) = 2.4 GHz. Figure 17shows the Fourier transformation of the 375-MHz and
1.875-GHz trapezoidal signal.
0
20 dB/dec
1875 MHz With
−5
−10
−15
−20
−25
80 ps Rise Time
20 dB/dec
375 MHz With
80 ps Rise Time
40 dB/dec
80%
40 dB/dec
20%
t
r
t
= 1/f
Period
100
1000
f − Frequency − MHz
10000
1/(pi x 100/60 t ) = 2.4 GHz
r
Figure 17. Approximate Frequency Spectrum of the Transmit Output Signal With 80 ps Rise Time
The spectrum analysis of the data signal suggests building a backplane with little frequency attenuation up to
2 GHz. Practically, this is achievable only with expensive, specialized PCB material. To support material like
FR4, a compensation technique is necessary to compensate for backplane imperfections.
EXPLANATION OF EQUALIZATION
Backplane designs differ widely in size, layer stack-up, and connector placement. In addition, the performance is
impacted by trace architecture (trace width, coupling method) and isolation from adjacent signals. Common to
most commercial backplanes is the use of FR4 as board material and its related high-frequency signal
attenuation. Within a backplane, the shortest to longest trace lengths differ substantially – often ranging from
8 inches up to 40 inches. Increased loss is associated with longer signal traces. In addition, the backplane
connector often contributes a good amount of signal attenuation. As a result, the frequency signal attenuation for
a 300-MHz signal might range from 1 dB to 4 dB while the corresponding attenuation for a 2-GHz signal might
span 6 dB to 24 dB. This frequency dependent loss causes distortion jitter on the transmitted signal. Each
LVCP404 receiver input incorporates an equalizer and compensates for such frequency loss. The
SN65LVCP404 equalizer provides 5 dB of frequency gain between 375 MHz and 1.875 GHz, compensating
roughly for 20 inches of FR4 material with 8-mil trace width. Distortion jitter improvement is substantial, often
providing more than 30-ps jitter reduction. The 5-dB compensation is sufficient for most short backplane traces.
For longer trace lengths, it is recommended to enable transmit preemphasis in addition.
13
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SN65LVCP404
www.ti.com
SLLS700–MARCH 2007
APPLICATION INFORMATION (continued)
SETTING THE PREEMPHASIS LEVEL
The receive equalization compensates for ISI. This reduces jitter and opens the data eye. In order to find the
best preemphasis setting for each link, calibration of every link is recommended. Assuming each link consists of
a transmitter (with adjustable pre-emphasis such as LVCP404) and the LVCP404 receiver, the following steps
are necessary:
1. Set the transmitter and receiver to 0-dB preemphasis; record the data eye on the LVCP404 receiver
output.
2. Increase the transmitter preemphasis until the data eye on the LVCP404 receiver output looks the
cleanest.
14
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
SN65LVCP404RGZR
SN65LVCP404RGZRG4
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGZ
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
QFN
RGZ
48
2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
SN65LVCP404RGZR
RGZ
48
MLA
330
16
7.3
7.3
1.5
12
16 PKGORN
T2TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
MLA
Length (mm) Width (mm) Height (mm)
SN65LVCP404RGZR
RGZ
48
346.0
346.0
33.0
Pack Materials-Page 2
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