SN65LVDS051MPWREP [TI]
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS; 高速差分线路驱动器和接收
| 型号： | SN65LVDS051MPWREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS |
| 文件： | 总22页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
FEATURES
SN65LVDS179
D OR DGK PACKAGE
•
Controlled Baseline
One Assembly/Test Site, One Fabrication
Site
(TOP VIEW)
5
–
3
2
Y
Z
D
R
6
8
7
V
CC
A
B
Z
Y
1
2
3
4
8
7
6
5
R
D
•
Enhanced Diminishing Manufacturing Sources
(DMS) Support
A
B
GND
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
SN65LVDS180
D OR PW PACKAGE
(TOP VIEW)
Meet or Exceed the Requirements of ANSI
TIA/EIA-644-1995 Standard
9
NC
V
V
A
B
Z
Y
•
•
•
•
Signaling Rates up to 400 Mbps
Bus-Terminal ESD Exceeds 12 kV
Operates From a Single 3.3-V Supply
1
2
3
4
5
6
7
14
13
12
11
10
9
5
CC
Y
Z
D
10
R
RE
CC
4
3
DE
RE
DE
D
12
11
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100-Ω Load
A
B
2
R
GND
GND
NC
8
•
•
Propagation Delay Times
SN65LVDS050
–
–
Driver: 1.7 ns Typ
14
13
D OR PW PACKAGE
(TOP VIEW)
15
1Y
1Z
Receiver: 3.7 ns Typ
1D
12
9
Power Dissipation at 200 MHz
1B
1A
1R
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
DE
2D
10
11
2Y
2Z
–
–
Driver: 25 mW Typical
1D
1Y
1Z
DE
2Z
Receiver: 60 mW Typical
RE
2R
2
1
•
•
LVTTL Input Levels Are 5-V Tolerant
3
1A
1B
1R
Receiver Maintains High Input Impedance
With VCC < 1.5 V
2A
4
5
RE
2R
6
7
2B
GND
10 2Y
2D
2A
2B
•
Receiver Has Open-Circuit Fail Safe
9
SN65LVDS051
D OR PW PACKAGE
(TOP VIEW)
14
15
1Y
1D
13
1Z
1B
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
4
3
1DE
1R
2
1
1D
1Y
1A
1B
1R
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
1DE
2R
1Z
2DE
10
11
9
2Y
2Z
2D
2A
11 2Z
12
10
9
2B
GND
2Y
2D
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
2DE
2R
6
7
2A
2B
5
DESCRIPTION/ORDERING INFORMATION
The SN65LVDS179, SN65LVDS180, SN65LVDS050, and SN65LVDS051 are differential line drivers and
receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The
TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of
247 mV into a 100-Ω load, and receipt of 100-mV signals with up to 1 V of ground potential difference between
a transmitter and receiver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media
may be printed circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
application specific characteristics.)
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since these
devices are intended for use in simplex or distributed simplex bus structures, the driver enable function does not
put the differential outputs into a high-impedance state, but rather disconnects the input and reduces the
quiescent power used by the device. (For these functions with a high-impedance driver output, see the
SN65LVDM series of devices.) All devices are characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS(1)
TA
PACKAGE
SMALL OUTLINE (DGK)
SMALL OUTLINE (PW)
SMALL OUTLINE (D)
SN65LVDS050MDREP(2)
SN65LVDS051MDREP(2)
SN65LVDS179MDREP(2)
SN65LVDS180MDREP(2)
SN65LVDS050MPWREP(2)
SN65LVDS051MPWREP(2)
-55°C TO 125°C
SN65LVDS179MDGKREP
SN65LVDS180MPWREP(2)
(1) For the most current packaging and odering infomation, see the Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
(2) Product Preview
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
FUNCTION TABLES
BLK
SN65LVDS179 Receiver(1)
INPUTS
OUTPUT
R
VID = VA – VB
V
ID ≥ 100 mV
H
?
– 100 mV < VID < 100 mV
VID ≥ 100 mV
L
Open
H
(1) H = high level, L = low level, ? = indeterminate
SN65LVDS179 Driver(1)
INPUT
D
OUTPUTS
Y
L
Z
H
L
L
H
H
L
Open
H
(1) H = high level, L = low level
SN65LVDS180, SN65LVDS050, and SN65LVDS051
Receiver(1)
INPUTS
VID = VA – VB
ID ≥ 100 mV
– 100 mV < VID < 100 mV
OUTPUT
R
RE
L
V
H
?
L
VID ≤– 100 mV
L
L
Open
X
L
H
Z
H
(1) H = high level, L = low level, Z = high impedance, X = don't care
SN65LVDS180, SN65LVDS050, and SN65LVDS051
Driver(1)
INPUTS
OUTPUTS
D
L
DE
H
Y
L
Z
H
H
H
H
L
Open
X
H
L
H
L
OFF
OFF
(1) H = high level, L = low level, OFF = No Output, X = don't care
3
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
V
CC
300 kΩ
50 Ω
5 Ω
50 Ω
10 kΩ
Y or Z
Output
D or
RE
Input
DE
Input
7 V
7 V
7 V
300 kΩ
V
CC
V
CC
300 kΩ
300 kΩ
5 Ω
R Output
A Input
B Input
7 V
7 V
7 V
4
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
VCC
Supply voltage range(2)
Voltage range
4
6
4
V
D, R, DE, and RE
Y, Z, A, and B
Y, Z, A, B, and GND(3)
All
V
Class 3, A: 12 kV, B: 600 V
Class 3, A: 7 kV, B: 500 V
Electrostatic discharge
See Dissipation Rating
Table
Continuous power dissipation
Storage temperature range
– 65
150
250
°C
°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7
Dissipation Ratings Table
DERATING
T
A ≤ 25°C
FACTOR
ABOVE TA
25°C(1)
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PACKAGE
POWER RATING
=
DGK
PW(14)
PW(16)
D(8)
424 mW
736mw
839mw
635mw
987mw
1110mw
3.4 mW/°C
5.9 mW/°C
6.7 mW/°C
5.1 mW/°C
7.9 mW/°C
8.9 mW/°C
220 mW
383 mW
437 mW
330 mW
513 mW
577 mW
84mW
146mW
169mW
125mW
197mW
220mW
D(14)
D(16)
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air
flow.
Recommended Operating Conditions
MIN
3
NOM
MAX
UNIT
V
VCC
VIH
VIL
Supply voltage
3.3
3.6
High-level input voltage
2
V
Low-level input voltage
0.8
0.6
V
|VID
|
Magnitude of differential input voltage
Magnitude of differential output voltage with disabled driver
Driver output voltage
0.1
V
|VOD(dis)
|
520
2.4
mV
V
VOY or VOZ
0
ŤVIDŤ
2
ŤVIDŤ
2.4 *
VIC
Common-mode input voltage (see Figure 5)
Operating free-air temperature(1)
V
2
VCC – 0.8
125
TA
–55
°C
(1) Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging
5
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
Device Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
SN65LVDS179
TEST CONDITIONS
No receiver load, Driver RL = 100 Ω
MIN TYP(1) MAX
UNIT
9
12
mA
Driver and receiver enabled, No receiver load,
Driver RL = 100 Ω
9
12
Driver enabled, Receiver disabled, RL = 100 Ω
Driver disabled, Receiver enabled, No load
Disabled
5
1.5
0.5
7
2
1
SN65LVDS180
mA
Supply
current
ICC
Drivers and receivers enabled, No receiver loads,
Driver RL = 100 Ω
12
20
Drivers enabled, Receivers disabled, RL = 100 Ω
Drivers disabled, Receivers enabled, No loads
Disabled
10
3
16
6
SN65LVDS050
SN65LVDS051
mA
mA
0.5
12
3
1
Drivers enabled, No receiver loads, Driver RL = 100 Ω
Drivers disabled, No loads
20
6
(1) All typical values are at 25°C and with a 3.3-V supply.
Driver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
|VOD
|
Differential output voltage magnitude
247 340
454
RL = 100 Ω,
See Figure 1 and
Figure 2
mV
Change in differential output voltage magnitude
between logic states
∆|VOD
|
–50
50
VOC(SS)
∆VOC(SS)
VOC(PP)
Steady-state common-mode output voltage
1.125
–50
1.2 1.375
50
V
Change in steady-state common-mode output voltage
between logic states
See Figure 3
mV
mV
Peak-to-peak common-mode output voltage
50
–0.5
2
150
–20
20
DE
IIH
High-level input current
D
VIH = 5 V
µA
µA
DE
–0.5
2
–10
10
IIL
Low-level input current
D
VIL = 0.8 V
VOY or VOZ = 0 V
VOD = 0 V
3
10
IOS
Short-circuit output current
mA
3
10
DE = 0 V,
VOY = VOZ = 0 V
IO(OFF)
Off-state output current
Input capacitance
–1
1
µA
DE = VCC
VOY = VOZ = 0 V,
VCC < 1.5 V
,
CIN
3
pF
6
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
Receiver Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
100
VIT+
VIT–
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
See Figure 5 and Table 1
mV
–100
IOH = –8 mA
IOH = –4 mA
IOL = 8 mA
VI = 0
2.4
2.8
VOH
VOL
II
High-level output voltage
Low-level output voltage
Input current (A or B inputs)
V
V
0.4
–2 –11
–20
µA
VI = 2.4 V
VCC = 0 V
VIH = 5 V
–1.2
–3
II(OFF)
IIH
Power-off input current (A or B inputs)
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
Input capacitance
±20
±10
±10
±10
µA
µA
µA
µA
pF
IIL
VIL = 0.8 V
VO = 0 or 5 V
IOZ
CI
5
Driver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
4.5
UNIT
ns
tPLH
tPHL
tr
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL – tPLH|)(2)
1.7
1.7
0.8
0.8
300
150
4.3
3.1
4.5
ns
1.2
ns
RL = 100 Ω, CL = 10 pF,
See Figure 2
tf
1.2
ns
tsk(p)
tsk(o)
ten
ps
Channel-to-channel output skew(3)
ps
Enable time
10
10
ns
See Figure 4
tdis
Disable time
ns
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(3) tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
Receiver Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
4.5
UNIT
ns
tPLH
tPHL
tsk(p)
tr
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Pulse skew (|tPHL – tPLH|)(2)
3.7
3.7
0.3
0.7
0.9
2.5
2.5
7
4.5
ns
CL = 10 pF,
See Figure 6
ns
Output signal rise time
1.5
1.5
ns
tf
Output signal fall time
ns
tPZH
tPZL
tPHZ
tPLZ
Propagation delay time, high-impedance to high-level output
Propagation delay time, high-impedance to low-level output
Propagation delay time, high-level to high-impedance output
Propagation delay time, low-level to high-impedance output
ns
ns
See Figure 7
ns
4
ns
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
7
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
Driver
I
OY
Driver Enable
Y
Z
I
I
A
V
OD
V
) V
OY
OZ
I
OZ
V
OY
2
V
I
V
OC
V
OZ
Figure 1. Driver Voltage and Current Definitions
Driver Enable
Y
Z
100 Ω
±1%
V
OD
Input
C
L
= 10 pF
(2 Places)
2 V
Input
1.4 V
0.8 V
t
PHL
t
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
8
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Driver Enable
49.9 Ω, ±1% (2 Places)
3 V
0 V
Y
Input
Z
V
OC
V
OC(PP)
C
= 10 pF
L
V
OC(SS)
(2 Places)
V
OC
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
1.2 V
DE
C
= 10 pF
L
V
OY
V
OZ
(2 Places)
2 V
1.4 V
0.8 V
DE
~1.4 V
1.25 V
1.2 V
V
V
or V
D at 2 V and input to DE
D at 0.8 V and input to DE
OY
OZ
t
t
en
t
t
dis
1.2 V
1.15 V
~1 V
or V
OZ
OY
en
dis
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Receiver
A
V
) V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMON-MODE
APPLIED VOLTAGES
(V)
INPUT VOLTAGE
(V)
VIA
1.25
1.15
2.4
2.3
0.1
0
VIB
1.15
1.25
2.3
2.4
0
VID
100
VIC
1.2
–100
100
1.2
2.35
2.35
0.05
0.05
1.2
–100
100
0.1
0.9
1.5
1.8
2.4
0
–100
600
1.5
0.9
2.4
1.8
0.6
0
–600
600
1.2
2.1
–600
600
2.1
0.3
0.6
–600
0.3
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SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
−0.4 V
t
t
PHL
PLH
V
V
O
OH
2.4 V
0.4 V
1.4 V
V
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
11
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
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SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
B
1.2 V
500 Ω
A
C
L
10 pF
+
−
V
O
V
TEST
Inputs
RE
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
RE
1.4 V
0.8 V
t
PZL
t
t
PZL
PLZ
2.5 V
1.4 V
R
V
OL
+0.5 V
V
OL
0 V
V
TEST
A
1.4 V
2 V
RE
1.4 V
0.8 V
t
PZH
t
t
PZH
PHZ
V
OH
V
OH
−0.5 V
R
1.4 V
0 V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
12
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
DISABLED DRIVER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
40
30
20
10
0
V
= 3.3 V
= 25°C
CC
V
= 0 V
OZ
T
A
DE = 0 V
V
= 1.2 V
OZ
V
OZ
= V
OY
−10
V
OZ
= 2.4 V
−20
−30
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage − V
O
Figure 8.
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
4
3
3.5
3
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
2.5
2
2
1
1.5
1
0.5
0
0
0
2
4
6
−1
−4
−3
−2
0
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
Figure 9.
Figure 10.
13
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
5
4
3
2
1
0
4
V
T
A
= 3.3 V
= 25°C
CC
V
T
A
= 3.3 V
= 25°C
CC
3
2
1
0
0
10
60
−80
−60
− High-Level Output Current − mA
0
20
30
40
50
−40
−20
I
− Low-Level Output Current − mA
I
OH
OL
Figure 11.
Figure 12.
DRIVER
DRIVER
HIGH- TO LOW-LEVEL PROPAGATION DELAY TIME
vs
LOW- TO HIGH-LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.5
FREE-AIR TEMPERATURE
2.5
2
2
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3 V
V
CC
= 3 V
V
= 3.6 V
30
V
= 3.6 V
30
CC
CC
1.5
−50
1.5
−50
−30 −10
10
50
90
−30 −10
10
50
90
70
70
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 13.
Figure 14.
14
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
TYPICAL CHARACTERISTICS (continued)
RECEIVER
HIGH- TO LOW-LEVEL PROPAGATION DELAY TIME
RECEIVER
LOW- TO HIGH-LEVEL PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE−AIR TEMPERATURE
4.5
4.5
V
CC
= 3 V
V
CC
= 3.3 V
4
4
V
CC
= 3.3 V
V
CC
= 3 V
3.5
3.5
V
CC
= 3.6 V
V
CC
= 3.6 V
3
3
2.5
−50
2.5
−50
−30 −10
10
50
90
−30 −10
10
50
90
30
70
30
70
T − Free−Air Temperature − °C
A
T − Free-Air Temperature − °C
A
Figure 15.
Figure 16.
15
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common-mode output and balanced interface for very low noise
emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL
speeds without the power and dual supply requirements.
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
100M
Data Rate − Hz
Figure 17. Data Transmission Distance Versus Rate
16
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SN65LVDS179-EP, SN65LVDS180-EP
SN65LVDS050-EP, SN65LVDS051-EP
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
www.ti.com
SGLS203B–SEPTEMBER 2003–REVISED JANUARY 2007
APPLICATION INFORMATION (continued)
Fail Safe
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV
and within its recommended input common-mode voltage range. However, TI's LVDS receiver is different in how
it handles the open-input circuit situation.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 18. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
V
CC
300 kΩ
300 kΩ
A
R
t
100 Ω Typ
Y
B
V
IT
≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as
it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could
defeat the pullup currents from the receiver and the fail-safe feature.
17
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN65LVDS179MDGKREP
V62/07612-03NE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSOP
DGK
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP
DGK
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS179-EP :
Catalog: SN65LVDS179
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN65LVDS179MDGKREP MSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
MSOP DGK
SPQ
Length (mm) Width (mm) Height (mm)
358.0 335.0 35.0
SN65LVDS179MDGKREP
8
2500
Pack Materials-Page 2
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