SN65LVDS301ZXHR [TI]
SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter;
| 型号： | SN65LVDS301ZXHR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter |
| 文件： | 总43页 (文件大小：2387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS301
SLLS681E – FEBRUARY 2006 – REVISED OCTOBER 2020
SN65LVDS301 Programmable 27-Bit Parallel-to-Serial Transmitter
1 Features
3 Description
•
•
FlatLink™3G serial interface technology
Compatible with FlatLink3G receivers such as
SN65LVDS302
The SN65LVDS301 serializer device converts 27
parallel data inputs to 1, 2, or 3 Sub Low-Voltage
Differential Signaling (SubLVDS) serial outputs. It
loads a shift register with 24 pixel bits and 3 control
bits from the parallel CMOS input interface. In addition
to the 27 data bits, the device adds a parity bit and
two reserved bits into a 30-bit data word. Each word is
latched into the device by the pixel clock (PCLK). The
parity bit (odd parity) allows a receiver to detect single
bit errors. The serial shift register is uploaded at 30,
15, or 10 times the pixel-clock data rate depending on
the number of serial links used. A copy of the pixel
clock is output on a separate differential output.
•
•
Input supports 24-bit RGB video mode interface
24-Bit RGB data, 3 control bits, 1 parity bit and 2
reserved bits transmitted over 1, 2 or 3 differential
lines
SubLVDS differential voltage levels
Effective data throughput up to 1755 Mbps
Three operating modes to conserve power
– Active-mode QVGA 17.4 mW (typ)
– Active-mode VGA 28.8 mW (typ)
– Shutdown mode 0.5 μA (typ)
– Standby mode 0.5 μA (typ)
Bus swap for increased PCB layout flexibility
1.8-V supply voltage
ESD rating > 2 kV (HBM)
Pixel clock range of 4 MHz–65 MHz
Failsafe on all CMOS inputs
•
•
•
FPC
cabling
typically
interconnects
the
SN65LVDS301 with the display. Compared to parallel
signaling, the LVDS301 outputs significantly reduce
the EMI of the interconnect by over 20 dB. The
electromagnetic emission of the device itself is very
low and meets the meets SAE J1752/3 'M'-spec. (see
Figure 6-22)
•
•
•
•
•
•
•
Packaging: 80 pin 5mm × 5mm nFBGA®
Very low EMI meets SAE J1752/3 'M'-spec
The SN65LVDS301 is characterized for operation
over ambient air temperatures of –40°C to 85°C. All
CMOS inputs offer failsafe features to protect them
from damage during power-up and to avoid current
flow into the device inputs during power-up. An input
voltage of up to 2.165 V can be applied to all CMOS
inputs while VDD is between 0V and 1.65V.
2 Applications
•
•
•
•
•
•
•
Wearables (non-medical)
Tablets
Mobile phones
Portable electronics
Gaming
Retail automation & payment
Building automation
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN65LVDS301
nFBGA (80)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
LCD
VDS314
L
or
VDS302
L
Application
Processor
with CMOS
Video Interface
LVDS301
or
LVDS311
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65LVDS301
SLLS681E – FEBRUARY 2006 – REVISED OCTOBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings (1) ...................................5
6.2 Thermal Information....................................................5
6.3 Recommended Operating Conditions (1) ................... 6
6.4 Device Electrical Characteristics.................................7
6.5 Output Electrical Characteristics.................................7
6.6 Input Electrical Characteristics....................................8
6.7 Switching Characteristics............................................8
6.8 Timing Characteristics.................................................9
6.9 Device Power Dissipation........................................... 9
6.10 Typical characteristics.............................................10
7 Parameter Measurement Information..........................14
8 Detailed Description......................................................22
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................23
8.3 Feature Description...................................................23
8.4 Device Functional Modes..........................................25
9 Application information................................................ 30
9.1 Application Information............................................. 30
9.2 Preventing Increased Leakage Currents in
Control Inputs..............................................................30
9.3 VGA Application........................................................30
9.4 Dual LCD-Display Application...................................31
9.5 Typical Application Frequencies............................... 31
10 Power Supply Design Recommendation...................33
10.1 Decoupling Recommendation.................................33
11 Layout...........................................................................34
11.1 Layout Guidelines................................................... 34
12 Device and Documentation Support..........................35
12.1 Support Resources................................................. 35
12.2 Trademarks.............................................................35
12.3 Electrostatic Discharge Caution..............................35
12.4 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
Information.................................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2012) to Revision E (October 2020)
Page
•
NOTE: The device in the MicroStar Jr. BGA packaging were redesigned using a laminate nFBGA package.
This nFBGA package offers datasheet-equivalent electrical performance. It is also footprint equivalent to the
MicroStar Jr. BGA. The new package designator in place of the discontinued package designator will be
updated throughout the datasheet......................................................................................................................1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 1
Changed u*jr ZQE to nFBGA ZXH..................................................................................................................... 3
Changed u*jr ZQE to nFBGA ZXH, updated thermal information.......................................................................5
Added overview................................................................................................................................................ 22
•
•
•
•
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5 Pin Configuration and Functions
Figure 5-1. 80-Ball ZXH (Top View)
Pin Functions
NAME
D0+, D0–
PIN
I/O
DESCRIPTION
J5, J4
SubLVDS Data Link (active during normal operation)
SubLVDS Data Link (active during normal operation when LS0 = high and
LS1 = low, or LS0 = low and LS1=high; high impedance if LS0 = LS1 = low)
D1+, D1–
F9, G9
SubLVDS Out
SubLVDS Data Link (active during normal operation when LS0 = low and
LS1 = high, high-impedance when LS1 = low)
D2+, D2–
D9, E9
J7, J6
CLK+, CLK–
SubLVDS output Clock; clock polarity is fixed
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Pin Functions (continued)
NAME
PIN
I/O
DESCRIPTION
A5/C2, B6/C1,
A6/D2, B7/D1,
A7/E1, B8/F2,
A8/F1, B9/G2
R0–R7
Red Pixel Data (8); pin assignment depends on SWAP pin setting
B1/B5, B2/A4,
A2/B4, B3/A3,
A3/B3, B4/A2,
A4/B2, B5/B1
G0–G7
B0–B7
Green Pixel Data (8); pin assignment depends on SWAP pin setting
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
B9/G2, A8/F1,
B8/F2, A7/E1,
B7/D1, A6/D2,
B6/C1, A5/C2
HS
VS
DE
H1
H2
J2
Horizontal Sync
Vertical Sync
Data Enable
CMOS IN
Input Pixel Clock; rising or falling clock polarity is selected by control input
CPOL
PCLK
G1
Link Select (Determines active SubLVDS Data Links and PLL Range) See
Table 8-2
LS0, LS1
C9, D8
Disables the CMOS Drivers and Turns Off the PLL, putting device in
shutdown mode
1 – Transmitter enabled
0 – Transmitter disabled
(Shutdown)
TXEN
CPOL
J3
Note: The TXEN input incorporates glitch-suppression logic to avoid device
malfunction on short input spikes. It is necessary to pull TXEN high for
longer than 10 μs to enable the transmitter. It is necessary to pull the TXEN
input low for longer than 10 μs to disable the transmitter. At power up, the
transmitter is enabled immediately if TXEN = 1 and disabled if TXEN = 0
Input Clock Polarity Selection
H9
CMOS In
CMOS In
0 – rising edge clocking
1 – falling edge clocking
Bus Swap swaps the bus pins to allow device placement on top or bottom
of pcb. See pinout drawing for pin assignments.
SWAP
VDD
J8
0 – data input from B0...R7
1 – data input from R7...B0
C4
Supply Voltage
A1, A9, C5, C8, D4,
D5, D6, D7, E2, E4,
E5, E6, E7, F4, F5,
F6, F7, G4, G5, G6,
G7, H3, J1
GND
Supply Ground
Power Supply(1)
VDDLVDS
GNDLVDS
VDDPLLA
GNDPLLA
VDDPLLD
GNDPLLD
H5, H8
G8, H4
H7
SubLVDS I/O supply Voltage
SubLVDS Ground
PLL analog supply Voltage
PLL analog GND
H6
F8
PLL digital supply Voltage
PLL digital GND
E8
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
-0.3 to 2.175
-0.5 to 2.175
-0.5 to VDD + 2.175
±3
UNIT
V
Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
Voltage range at any input When VDDx > 0 V
V
or output terminal
When VDDx ≤ 0 V
V
Human Body Model(3) (all Pins)
kV
V
Electrostatic discharge
Charged-Device Mode(4)l (all Pins)
Machine Model(5) (all pins)
±500
±200
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
(3) In accordance with JEDEC Standard 22, Test Method A114-A.
(4) In accordance with JEDEC Standard 22, Test Method C101.
(5) In accordance with JEDEC Standard 22, Test Method A115-A
6.2 Thermal Information
SN65LVDS301
ZXH
THERMAL METRIC(1)
UNIT
(nFBGA)
80 PINS
47.6
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
33.1
30.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.7
ψJB
30.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.3 Recommended Operating Conditions (1)
MIN
NOM
MAX UNIT
VDD
Supply voltages
1.65
1.8
1.95
V
VDDPLLA
VDDPLLD
VDDLVDS
VDDn(PP)
Test set-up see Figure 7-5
f(PCLK) ≤ 50 MHz; f(noise) = 1 Hz to 2 GHz
f(PCLK) > 50 MHz; f(noise) = 1 Hz to 1 MHz
f(PCLK) > 50 MHz; f(noise) > 1 MHz
1-Channel transmit mode, see Figure 8-4
2-Channel transmit mode, see Figure 8-5
3-Channel transmit mode, see Figure 8-6
100
100
40
15
30
65
3
Supply voltage noise
magnitude (all supplies)
mV
4
8
fPCLK
Pixel clock frequency
PCLK input duty cycle
MHz
°C
20
0.5
Frequency threshold Standby mode to active
mode(2), see Figure 7-9
tH x fPCLK
TA
0.33
–40
0.67
85
Operating free-air
temperature
tjit(per)PCLK
tjit(TJ)PCLK
tjit(CC)PCLK
PCLK RMS period jitter(3)
5
0.05/fPCLK
0.02/fPCLK
ps-rms
PCLK total jitter
s
s
Measured on PCLK input
PCLK peak
cycle-to-cycle jitter(4)
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
VIH
VIL
tDS
High-level input voltage
Low-level input voltage
0.7×VDD
VDD
V
V
0.3×VDD
Data set up time prior to
PCLK transition
2.0
2.0
ns
f (PCLK) = 65 MHz; see Figure 7-1
tDH
Data hold time after PCLK
transition
ns
(1) Unused single-ended inputs must be held high or low to prevent them from floating.
(2) PCLK input frequencies lower than 500 kHz force the SN65LVDS301into standby mode. Input frequencies between 500 kHz and 3
MHz may or may not activate the SN65LVDS301. Input frequencies beyond 3 MHz activate the SN65LVDS301.
(3) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle
pairs.
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6.4 Device Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAM
ETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(CLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD
alternating 1010 serial bit pattern
fPCLK = 4 MHz
fPCLK = 6 MHz
fPCLK = 15 MHz
fPCLK = 4 MHz
fPCLK = 6 MHz
fPCLK = 15 MHz
fPCLK = 8 MHz
fPCLK = 22 MHz
fPCLK = 30 MHz
fPCLK = 8 MHz
fPCLK = 22 MHz
fPCLK = 30 MHz
fPCLK = 20 MHz
fPCLK = 65 MHz
9.0
10.6
16
11.4
12.6
18.8
,
mA
1ChM
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
8.0
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD
,
8.9
mA
mA
typical power test pattern (see Table 7-2)
14.0
13.7
18.4
21.4
11.5
16.0
19.1
20.0
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(CLK)=R
15.9
22.0
25.8
L(Dx)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD
,
alternating 1010 serial bit pattern;
2ChM
3ChM
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD
,
IDD
mA
mA
typical power test pattern (see Table 7-3)
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
22.5
36.8
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD
,
29.1
15.9
24.7
0.61
alternating 1010 serial bit pattern
VDD =VDDPLLA=VDDPLLD=VDDLVDS, RL(PCLK)=R
fPCLK = 20 MHz
fPCLK = 65 MHz
L(D0)=100 Ω, VIH=VDD, VIL=0 V, TXEN at VDD
,
mA
μA
typical power test pattern (see Table 7-4)
Standby Mode
VDD = VDDPLLA = VDDPLLD
= VDDLVDS, RL(PCLK)=R
L(D0)=100 Ω, VIH=VDD, V
IL=0 V, all inputs held static
high or static low
10
10
Shutdown Mode
0.55
μA
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
6.5 Output Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
subLVDS output (D0+, D0–, D1+, D1–, D2+, D1–, CLK+, and CLK–)
VOCM(SS) Steady-state common-mode output voltage
VOCM(SS) Change in steady-state common-mode output voltage
VOCM(PP) Peak-to-peak common mode output voltage
Output load see Figure 7-3
0.8
0.9
1.0
10
V
–10
mV
mV
75
|VOD
|
Differential output voltage magnitude
|VDx+ – VDx– |, |VCLK+ – VCLK–
100
–10
150
200
mV
|
Δ|VOD
|
Change in differential output voltage between logic states
10
10
3
mV
Ω
ZOD(CLK) Differential small-signal output impedance
TXEN at VDD
210
5
IOSD
IOS
Differential short-circuit output current
Short circuit output current(2)
VOD = 0 V, fPCLK = 28 MHz
VO = 0 V or VDD
mA
μA
IOZ
High-impedance state output current
VO = 0 V or VDD(max),
TXEN at GND
–3
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) All SN65LVDS301 outputs tolerate shorts to GND or VDD without permanent device damage.
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6.6 Input Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], CPOL, TXEN, SWAP
IIH
High-level input current
Low-level input current
Input capacitance
VIN = 0.7 × VDD
VIN = 0.3 × VDD
–200
–200
200
nA
IIL
200
CIN
1.5
pF
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
6.7 Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
tr
tf
20%-to-80% differential
output signal rise time
See Figure 7-2 and Figure 7-3
250
500
ps
20%-to-80% differential
output signal fall time
See Figure 7-2 and Figure 7-3
Tested from PCLK input to
250
500
fPCLK = 22 MHz
fPCLK = 65 MHz
0.082 × fPCLK
0.07 × fPCLK
PLL bandwidth (3dB cutoff
frequency)
fBW
CLK output, See Figure 6-1
MHz
s
(3)
tpd(L)
Propagation delay time,
input to serial output (data
latency Figure 7-4)
TXEN at VDD, VIH=VDD, V
IL=GND, RL=100 Ω
1-channel mode
2-channel mode
3-channel mode
0.8/fPCLK
1.0/fPCLK
1.1/fPCLK
0.45
1/fPCLK
1.21/fPCLK
1.31/fPCLK
0.50
1.2/fPCLK
1.5/fPCLK
1.6/fPCLK
0.55
tH × fCLK0
Output CLK duty cycle
1-channel and 3-channel
mode
2-channel mode
0.49
3.8
0.53
0.58
10
tGS
TXEN Glitch suppression
pulse width(2)
VIH=VDD, VIL=GND, TXEN toggles between VIL and VIH
,
μs
see Figure 7-7 and Figure 7-8
tpwrup
tpwrdn
Enable time from power
down (↑TXEN)
Time from TXEN pulled high to CLK and Dx outputs
enabled and transmit valid data; see Figure 7-8
0.24
0.5
2
ms
Disable time from active
mode (↓TXEN)
TXEN is pulled low during transmit mode; time
measurement until output is disabled and PLL is
Shutdown; see Figure 7-8
11
μs
ms
μs
twakup
Enable time from Standby
(↕PCLK)
TXEN at VDD; device in standby; time measurement from
PCLK starts switching to CLK and Dx outputs enabled
and transmit valid data; see Figure 7-8
0.23
0.4
2
tsleep
Disable time from Active
mode (PCLK stopping)
TXEN at VDD; device is transmitting; time measurement
from PCLK input signal stops until CLK + Dx outputs are
disabled and PLL is disabled; see Figure 7-8
100
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or
low-to-high transition that is suppressed.
(3) The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter
is functionality tested only on Automatic Test Equipment (ATE).
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12.0%
9.0
8.5
8.0
7.5
7.0
6.5
6.0
4 MHz:
8.5%
8 MHz:
8.5%
11.0%
10.0%
9.0%
8.0%
7.0%
6.0%
5.0%
4.0%
20 MHz:
8.3%
RX PLL BW
Spec Limit
1ChM
Spec
Limit
2ChM
9%
8.5%
Spec Limit 3ChM
30 MHz:
7.6%
15 MHz:
7.6%
7.5%
7%
65 MHz:
7.0%
TX PLL BW
0
100
200
300
400
500
600
700
0
10
20
30
40
50
60
70
PLL frequency − MHz
PCLK FREQUENCY - MHz
Figure 6-1. LVDS301 PLL Bandwidth (also showing the LVDS302 PLL bandwidth)
6.8 Timing Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1ChM: x=0..29, fPCLK=15 MHz; TXEN at
VDD, VIH=VDD, VIL=GND, RL=100 Ω, test
pattern as in Table 7-7 (3)
x
x
- 330 ps
+ 330 ps
30 × fPCLK
30 × fPCLK
1ChM: x=0..29,
x – 0.1845
30 × fPCLK
x + 0.1845
30 × fPCLK
fPCLK=4 MHz to 15 MHz (4)
2ChM: x = 0..14, fPCLK = 30 MHz
x
x
- 330 ps
+ 330 ps
TXEN at VDD, VIH=VDD, VIL=GND, R
15 × fPCLK
15 × fPCLK
L=100 Ω, test pattern as in Table 7-8 (3)
Output Pulse Position,
tPPOSX ⇅serial data to ↑CLK; see (1)
(2)and Figure 7-6
ps
2ChM: x=0..14,
x – 0.1845
15 × fPCLK
x + 0.1845
15 × fPCLK
fPCLK= 8 MHz to 30 MHz (4)
3ChM: x=0..9, fPCLK=65 MHz,
x
x
- 210 ps
+ 210 ps
TXEN at VDD, VIH=VDD, VIL=GND, R
10 × fPCLK
10 × fPCLK
L=100 Ω, test pattern as in Table 7-9 (3)
3ChM: x=0..9,
x - 0.153
10 × fPCLK
x + 0.153
10 × fPCLK
fPCLK=20 MHz to 65 MHz (4)
(1) This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS302
receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined
with the SN65LVDS302 receiver;
(2) The pulse position min/max variation is given with a bit error rate target of 10–12; The measurement estimates the random jitter
contribution to the total jitter contribution by multiplying the random RMS jitter by the factor 14; Measurements of the total jitter are
taken over a sample amount of > 10–12 samples.
(3) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
(4) These Minimum and Maximum Limits are simulated only.
6.9 Device Power Dissipation
PARAMETER
TEST CONDITIONS
TYP
14.4
44.5
MAX
UNIT
fCLK = 4 MHz
fCLK = 65 MHz
fCLK = 4 MHz
fCLK = 65 MHz
VDDx = 1.8 V, TA = 25°C
mW
Device Power
Dissipation
PD
22.3
71.8
VDDx = 1.95 V, TA = –40°C
mW
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6.10 Typical characteristics
1.0
20
15
10
5
2-Channel Mode, 22 MHz (VGA)
2-Channel Mode, 11 MHz (HVGA)
Standby Current
Power-Down Current
0.1
0
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
Temperature - °C
Temperature - °C
Figure 6-2. Powerdown, Standby Supply Current
vs Temperature
Figure 6-3. Supply Current IDD vs Temperature
200
30
85°C
190
25°C
180
3-Channel Mode
25
170
–40°C
2-Channel Mode
20
160
150
140
130
120
110
100
15
10
1-Channel Mode
5
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
FREQUENCY - MHz
FREQUENCY - MHz
Figure 6-4. Supply Current vs PCLK Frequency
Figure 6-5. Differential Output Swing vs PCLK
Frequency
500
400
300
200
9.0
Spec Limit 1ChM, 4 MHz: 8.5%
Spec Limit 2ChM8 MHz: 8.5%
8.5
Spec Limit 3ChM 20 MHz: 8.3%
8.0
7.5
Spec Limit 2ChM
30 MHz: 7.6%
Spec Limit 1ChM,
15 MHz: 7.6%
7.0
6.5
6.0
5.5
5.0
4.5
4.0
Spec Limit 3ChM
65 MHz: 7.0%
3-ChM
2-ChM
3-Channel Mode
100
2-Channel Mode
40
1-Channel Mode
0
0
10
20
30
50
60
70
0
10
20
30
40
50
60
70
FREQUENCY - MHz
FREQUENCY - MHz
Figure 6-7. Cycle-to-cycle Output Jitter vs PCLK
Frequency
Figure 6-6. PLL Bandwidth
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200
120
100
80
60
40
20
0
2-Channel Mode,
11 MHz (VGA)
2-Channel Mode,
f(PCLK) = 11 MHz
150
100
50
2-Channel Mode,
22 MHz (HVGA)
2-Channel Mode,
f(PCLK) = 22 MHz
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE - °C
Temperature - °C
Figure 6-9. Output Pulse Position vs Temperature
Figure 6-8. Cycle-to-cycle Output Jitter vs
Temperature
250
250
190
175
2-Channel Mode,
f(PCLK) = 22 MHz
3-Channel Mode,
f(PCLK) = 65 MHz
0
0
–175
–190
–250
–250
500 ps/div
200 ps/div
Figure 6-10. Data Eye Pattern, 2-channel Mode
Figure 6-11. Data Eye Pattern, 3-channel Mode
249
250
190
190
1-Channel Mode,
f(PCLK) = 5.5 MHz
2-Channel Mode,
f(PCLK) = 22 MHz
0
0
–190
–190
–251
–250
1 ns/div
500 ps/div
Response Over 80-inch of FR-4 + 1m Coax Cable
Response Over 8-inch FR-4 + 1m Coax Cable
Figure 6-12. QVGA Output Waveform
Figure 6-13. VGA 2-channel Output Waveform
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249
190
249
190
2-Channel Mode,
f(PCLK) = 22 MHz
3-Channel Mode,
f(PCLK) = 22 MHz
0
0
–190
–190
–251
–251
500 ps/div
1 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 6-14. VGA 2-channel Output Waveform
Figure 6-15. VGA 3-channel Output Waveform
249
190
0
3-Channel Mode,
f(PCLK) = 56 MHz
–190
3-Channel Mode,
f(PCLK) = 56 MHz
–251
300 ps/div
3.5 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Response With 10-pF Load
Figure 6-16. XGA 3-channel Output Waveform
Figure 6-17. XGA 3-channel Output Waveform on
the SN65LVDS302 when driven by the
SN65LVDS301
-50
-60
-70
-80
-90
0
–5
-100
f(PCLK) = 65 MHz
-110
-120
-130
-140
-150
-160
-170
-180
CLK
D0
–10
D2
D1
–15
0
500
1000
FREQUENCY - Hz
1500
2000
1
10
100
1k
10k
FREQUENCY - Hz
100k
1M
10M
Figure 6-18. PLL Phase Noise
Figure 6-19. Output Return Loss
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0
0
-20
–5
–10
–15
–20
D0
CLK
-40
D0 to D1
D1
D2
-60
D0 to D2
-80
-100
0
500
1000
FREQUENCY - MHz
1500
2000
0
500
1000
1500
2000
FREQUENCY - MHz
Figure 6-21. Crosstalk
Figure 6-20. Output Common Mode Noise
Rejection
20
f(PCLK)=65MHz
2-ChM, f(PCLK)=22MHz
320MHz; 16dBuV
3-ChM, f(PCLK)=65MHz,
988MHz, 12dBuV
15
2-ChM, f(PCLK)=22MHz
683MHz; 12dBuV
3-ChM, f(PCLK)=65MHz,
282MHz
3-ChM, f(PCLK)=65MHz
777MHz; 11dBuV
10
1-ChM f(PCLK)=5MHz,
960MHz; 8dBuV
3-ChM, f(PCLK)=65MHz
113MHz; 6dBuV
5
0
0
200
400
600
800
1000
FREQUENCY - MHz
Figure 6-22. GTEM SAE J1752/3 EMI Test
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7 Parameter Measurement Information
t
DS
VIH
VIL
R[7:0], G[7:0], B[7:0];
VS, HS, DE, LS0, LS1,
TXEN, SWAP, CPOL
t
DH
VIH
VIL
PCLK
(CPOL=low)
t
R
Figure 7-1. Setup/Hold Time
150mV (nom)
V
OD
t
f
t
r
80%
0 V
20%
−150mV (nom)
Figure 7-2. Rise and Fall Time Definitions
975mV (nom)
825mV (nom)
V
or V
CLK+
Dx+
V
or V
CLK−
Dx−
R1 = 49.9
R2 = 49.9
CLK+, Dx+
V
OD
V
V
OCM
OCM
CLK−, Dx−
SN65LVDS301
V
OCM
(pp)
V
OCM
(ss)
C1 = 1 pF
C2 = 1 pF
NOTES:
A. 20 MHz output test pattern on all differental outputs (CLK, D0, D1, and D2):
this is achieved by: 1. Device is set to 3-channel-mode;
2. f
= 20 MHz
PCLK
3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND.
B. C1, C2 and C3 includes instrumentation and fixture capacitance; tolerance± 20%; C, R1 and R2 tolerance± 1%.
C. The measurement of V (pp) and V (ss) are taken with test equipment bandwidth >1 GHz.
OCM
OC
Figure 7-3. Driver Output Voltage Test Circuit and Definitions
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CMOS
Data In
pixel
R7
pixel
(n)
(n+1)
R7
R7
R6
(n−1)
(n)
(n+1)
R6
R6
(n)
(n−1)
(n+1)
V
DD
/2
PCLK
t
PROP
CLK−
CLK+
R7 R6
CP
CP R7 R6
D0+
pixel
(n−1)
pixel
(n−2)
R6
(n)
R6
R7
(n−1)
(n−1)
R7
(n)
Figure 7-4. tpd(L) Propagation Delay Input to Output (LS0 = LS1 = 0; CPOL = 0)
SN65LVDS301
V
DDPLLD
V
1
2
DDPLLA
1
V
DD
Noise
Generator
100 mV
10 mF
V
DDLVDS
GND
1.8 V
supply
Note: The generator regulates the
noise amplitude at point 1 to the
target amplitude given under the table
1.6
H
Recommended Operating Conditions
Figure 7-5. Power Supply Noise Test Set-Up
t
CLK+
CLK−
CLK+
Next Cycle
Current Cycle
Bit 0
Bit1
Bit2
Bitx
Bit0
Bit1
D[0:m]+
t
PPOS0
Note:
t
PPOS1
1−channel mode: x=0..29; m=0
2−channel mode: x=0..14; m=1
3−channel mode: x=0....9; m=2
t
PPOS2
t
PPOSx
Figure 7-6. tSK(0) SubLVDS Output Pulse Position Measurement
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V /2
DD
TXEN
PCLK
t
GS
PLL Approaches Lock
VCO Internal Signal
t
pwrup
CLK
D0, D1, D2
Figure 7-7. Transmitter Behavior While Approaching Sync
<20 ns
2 s
3
s
Glitch Shorter
Will Be
Ignored
Less Than 20 ns
Spike Will be
Rejected
Than t
GS
Glitch Shorter
Than t Will Be
Ignored
GS
TXEN
CLK+
t
pwrup
t
pwrdn
t
GS
I
CC
t
GS
PCLK
Transmitter Disabled
(OFF)
Transmitter Aquires Lock
Transmitter Enabled
(ON)
Transmitter
Disabled
(OFF)
Transmitter
Turns OFF
Figure 7-8. Transmitter Enable Glitch Suppression Time
PCLK
twakeup
tsleep
CLK+
Transmitter Disabled
(OFF)
Transmitter Aquires Lock,
Outputs Still Disabled
Transmitter Enabled,
Output Data Valid
Transmitter
Enabled,
Output Data
Valid
Transmitter
Disabled
(OFF)
Figure 7-9. Standby Detection
7.1.1 Power Consumption Tests
Table 7-1 shows an example test pattern word.
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Table 7-1. Example Test Pattern Word
Word
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x7C3E1E7
7
C
3
E
1
E
7
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
VS HS DE
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
7.1.1.1 Typical IC Power Consumption Test Pattern
The typical power consumption test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight
30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The pattern repeats
itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the
same probability to occur during typical device operation.
7.1.1.2
Table 7-2. Typical IC Power Consumption Test
Pattern, 1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000007
0xFFF0007
0x01FFF47
0xF0E07F7
0x7C3E1E7
0xE707C37
0xE1CE6C7
0xF1B9237
0x91BB347
0xD4CCC67
0xAD53377
0xACB2207
0xAAB2697
0x5556957
0xAAAAAB3
0xAAAAAA5
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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Table 7-3. Typical IC Power Consumption Test
Pattern, 2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
3
4
5
6
7
8
0x0000001
0x03F03F1
0xBFFBFF1
0x1D71D71
0x4C74C71
0xC45C451
0xA3aA3A5
0x5555553
Table 7-4. Typical IC Power Consumption Test
Pattern, 3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
3
4
5
0xFFFFFF1
0x0000001
0xF0F0F01
0xCCCCCC1
0xAAAAAA7
7.1.2 Maximum Power Consumption Test Pattern
The maximum (or worst-case) power consumption of the SN65LVDS301 is tested using the two different test
patterns shown in Table 7-5 and Table 7-6. The test patterns consist of sixteen 30-bit transmit words in 1-channel
mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The
pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on
RGB inputs has the same probability to occur during typical device operation.
Table 7-5. Worst-Case Power Consumption Test
Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0xAAAAAA5
0x5555555
Table 7-6. Worst-Case Power Consumption Test
Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000000
0xFFFFFF7
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7.1.3 Output Skew Pulse Position & Jitter Performance
The following test patterns are used to measure the output-skew pulse position and the jitter performance of the
SN65LVDS301. The jitter test pattern stresses the interconnect, particularly to test for ISI. Very long run-lengths
of consecutive bits incorporate very high and low data rates, maximinges switching noise. Each pattern is self-
repeating for the duration of the test.
Table 7-7. Transmit Jitter Test Pattern, 1-Channel
Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
0x0000031
0x00000F1
0x00003F1
0x0000FF1
0x0003FF1
0x000FFF1
0x0F0F0F1
0x0C30C31
0x0842111
0x1C71C71
0x18C6311
0x1111111
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0x3333331
0x2452413
0x22A2A25
0x5555553
0xDB6DB65
0xCCCCCC1
0xEEEEEE1
0xE739CE1
0xE38E381
0xF7BDEE1
0xF3CF3C1
0xF0F0F01
0xFFF0001
0xFFFC001
0xFFFF001
0xFFFFC01
0xFFFFF01
0xFFFFFC1
0xFFFFFF1
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Table 7-8. Transmit Jitter Test Pattern, 2-Channel
Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x000FFF3
3
0x8008001
4
0x0030037
5
0xE00E001
6
0x00FF001
7
0x007E001
8
0x003C001
9
0x0018001
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0x1C7E381
0x3333331
0x555AAA5
0x6DBDB61
0x7777771
0x555AAA3
0xAAAAAA5
0x5555553
0xAAA5555
0x8888881
0x9242491
0xAAA5571
0xCCCCCC1
0xE3E1C71
0xFFE7FF1
0xFFC3FF1
0xFF81FF1
0xFE00FF1
0x1FF1FF1
0xFFCFFC3
0x7FF7FF1
0xFFF0007
0xFFFFFF1
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Table 7-9. Transmit Jitter Test Pattern, 3-Channel
Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x0000001
3
0x0000003
4
0x0101013
5
0x0303033
6
0x0707073
7
0x1818183
8
0xE7E7E71
9
0x3535351
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0x0202021
0x5454543
0xA5A5A51
0xADADAD1
0x5555551
0xA6A2AA3
0xA6A2AA5
0x5555553
0x5555555
0xAAAAAA1
0x5252521
0x5A5A5A1
0xABABAB1
0xFDFCFD1
0xCAAACA1
0x1818181
0xE7E7E71
0xF8F8F81
0xFCFCFC1
0xFEFEFE1
0xFFFFFF1
0xFFFFFF5
0xFFFFFF5
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8 Detailed Description
8.1 Overview
The SN65LVDS301 is a serialising device where the input paralle data is converted to Sub Low-Voltage
Differential Signaling (SubLVDS) serial outputs. The SN65LVDS301 supports three power modes (Shutdown,
Standby and Active) to conserve power. When transmitting, the PLL locks to the incoming pixel clock PCLK and
generates an internal high-speed clock at the line rate of the data lines. The parallel data are latched on the
rising or falling edge of PCLK as selected by the external control signal CPOL. The serialized data is presented
on the serial outputs D0, D1, D2 with a recreated PCLK generated from the internal high-speed clock, output on
the CLK output. If PCLK stops, the device enters a standby mode to conserve power
The parallel (CMOS) input bus offers a bus-swap feature. The SWAP pin configures the input order of the pixel
data to be either R[7:0]. G[7:0], B[7:0], VS, HS, DE or B[0:7]. G[0:7], R[0:7], VS, HS, DE. This gives a PCB
designer the flexibility to better match the bus to the host controller pinout or to put the transmitter device on the
top side or the bottom side of the PCB.
Two Link Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used
to put the SN65LVDS301 in a shutdown mode. The SN65LVDS301 enters an active Standby mode if the input
clock PCLK stops.
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8.2 Functional Block Diagram
Parity
Calc
D0+
SubLVDS
SWAP
D0−
Bit29
Bit28=0
Bit27=0
1
0
D1+
SubLVDS
D1−
8
[0..26]
R[0:7]
8
D2+
G[0:7]
SubLVDS
D2−
8
B[0:7]
HS
VS
DE
CLK+
SubLVDS
CLK−
PCLK
0
1
iPCLK
x10, x15, or x30
x1
PLL
multiplier
CPOL
LS0
LS1
Control /
Glitch
supression
standby Monitor
TXEN
Figure 8-1. Functional Block Diagram
8.3 Feature Description
8.3.1 Swap Pin Functionality
The SWAP pin allows the pcb designer to reverse the RGB bus to minimize potential signal crossovers in the
PCB routing. The two drawings beneath show the RGB signal pin assignment based on the SWAP-pin setting.
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9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A
B
C
D
E
F
G2
G1
B7
B5
G4
G6
G5
R0
G7
R2
R1
R4
R3
R6
R5
G5
G6
R0
R2
G3
G1
G2
B7
G0
B5
B6
B3
B4
B1
B2
G0
B6
G3
R7
G7
R1
G4
B0
SN65LVDS301
Top View
SN65LVDS301
Top View
B4
R3
B3
R4
B1
B2
B0
VS
DE
R6
R5
R7
VS
DE
G
H
J
G
H
J
PCLK
HS
PCLK
HS
SWAP=1
SWAP
SWAP
1.8V
SWAP=0
Figure 8-2. SWAP PIN = 0
Figure 8-3. SWAP PIN = 1
Table 8-1. NUMERIC PIN LIST
PIN
SWAP
SIGNAL
GND
G2
G5
G4
G3
G6
G1
R0
. PIN
SWAP
SIGNAL
B6
. PIN
SWAP
SIGNAL
B1
A1
—
0
0
C1
C2
F1
F2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
—
0
1
0
1
0
1
0
1
0
1
1
0
1
R1
1
R6
A2
A3
A4
A5
A6
A7
B7
0
B2
R0
1
R5
C3
C4
C5
C6
C7
C8
C9
UNPOPULATED
F3
F4
F5
F6
F7
F8
F9
G1
—
—
—
—
—
—
—
—
0
VDD
GND
GND
GND
GND
VDDPLLD
D1+
—
VDD
GND
VDD
VDD
GND
LS0
B4
—
—
—
—
—
0
B7
R2
B5
R4
PCLK
B0
D1
D2
B3
1
R3
G2
R6
0
B5
1
R7
A8
A9
B1
B1
1
R2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
—
—
—
—
—
—
—
—
—
—
—
—
VDD
GND
G0
G7
G1
G6
G3
G4
G5
G2
G7
G0
D3
D4
D5
D6
D7
D8
D9
—
—
—
—
—
—
—
0
VDD
GND
GND
GND
GND
LS1
D2+
B3
GND
GND
GND
GND
GNDLVDS
D1–
B2
B3
B4
B5
HS
VS
E1
1
R4
GND
GNDLVDS
VDDLVDS
E2
E3
—
—
GND
VDD
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Table 8-1. NUMERIC PIN LIST (continued)
PIN
B6
SWAP
SIGNAL
R1
. PIN
SWAP
SIGNAL
. PIN
SWAP
SIGNAL
GNDPLLA
0
E4
E5
E6
E7
E8
E9
—
GND
H6
H7
H8
H9
J1
J2
J3
J4
J5
J6
J7
J8
J9
—
—
—
—
—
—
—
—
—
—
—
—
—
1
0
1
0
1
0
1
B6
—
—
—
—
—
GND
GND
VDDPLLA
VDDLVDS
CPOL
GND
R3
B7
B8
B9
B4
GND
R5
GNDPLLD
D2–
B2
DE
R7
TXEN
D0–
B0
D0+
CLK–
CLK+
SWAP
GNDLVDS
8.3.2 Parity Bit Generation
The SN65LVDS301 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two
reserved bits are not included in the parity generation. ODD Parity bit signaling is used. The transmitter sets the
Parity bit if the sum of the 27 data bits result in an even number of ones. The Parity bit is cleared otherwise. This
allows the receiver to verify Parity and detect single bit errors.
8.4 Device Functional Modes
8.4.1 Serialization Modes
The SN65LVDS301 transmitter has three modes of operation controlled by link-select pins LS0 and LS1. Table
8-2 shows the serializer modes of operation.
Table 8-2. Logic Table: Link Select Operating Modes
LS1
LS0
Mode of Operation
Data Links Status
0
0
1ChM
2ChM
3ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 high-impedance
0
1
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 high-impedance
1
1
0
1
3-channel mode (10-bit serialization rate)
Reserved
D0, D1, D2 active
Reserved
8.4.1.1 1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS301 transmits payload data over a single SubLVDS data pair,
D0. The PLL locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is
used to serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data
frame. Figure 8-4 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal
high-speed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK
output. While in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode
is intended for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth
capabilities of the SN65LVDS301.
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CLK–
CLK+
D0 +/– CHANNEL
0
0
CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE
0
0
CP R7 R6
Figure 8-4. Data and Clock Output in 1-Channel Mode (LS0 and LS1 = low).
8.4.1.2 2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS301 transmits payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed
clock is used to serialize the data payload on D0, and D1. Two reserved bits and the parity bit are added to the
data frame. Figure 8-5 illustrates the timing and the mapping of the data payload into the 30-bit frame and how
the frame becomes split into the two output channels. The internal high-speed clock is divided by 15 to recreate
the pixel clock, and presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8 MHz
through 30 MHz in this mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.
CLK–
CLK +
D0 +/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS
0
CP R7 R6
D1 +/– Channel
G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE G3 G2
0 0
Figure 8-5. Data and Clock Output in 2-Channel Mode (LS0 = high; LS1 = low).
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8.4.1.3 3-Channel Mode
While LS0 is held low and LS1 is held high, the SN65LVDS301 transmits payload data over three SubLVDS data
pairs D0, D1, and D2. The PLL locks to PCLK, and internally multiplies it by 10. The internal high-speed clock is
used to serialize the data payload on D0, D1, and D2. Two reserved bits and the parity bit are added to the data
frame. Figure 8-6 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the
frame becomes split over the three output channels. The internal high speed clock is divided back down by a
factor of 10 to recreate the pixel clock and presented on SubLVDS CLK output. While in this mode, the PLL can
lock to a clock in the range of 20 MHz through 65 MHz. The 3-channel mode supports applications with very
large display resolutions such as VGA or XGA.
CLK -
CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL
D2 +/- CHANNEL
0
0
G7 G6 G5 G4 G3 G2 G1 G0 HS
B7 B6 B5 B4 B3 B2 B1 B0 DE
0
0
G7 G6
B7 B6
Figure 8-6. Data and Clock Output in 3-Channel Mode (LS0 = low; LS1 = high).
8.4.2 Powerdown Modes
The SN65LVDS301 Transmitter has two powerdown modes to facilitate efficient power management.
8.4.3 Shutdown Mode
The SN65LVDS301 enters Shutdown mode when the TXEN pin is asserted low. This turns off all transmitter
circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are high-
impedance. Current consumption in Shutdown mode is nearly zero.
8.4.4 Standby Mode
The SN65LVDS301 enters the Standby mode if TXEN is high and the PCLK input signal frequency is less than
500kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter high-impedance mode.
The current consumption in Standby mode is very low. When the PCLK input signal is completely stopped, the I
DD current consumption is less than 10 μA. The PCLK input must not be left floating.
Note
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. To prevent large
leakage current, a CMOS gate must be kept at a valid logic level, either V IH or V IL. This can be
achieved by applying an external voltage of VIH or VIL to all SN65LVDS301 inputs.
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8.4.5 Active Modes
When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS301 enters Active
mode. Current consumption in Active mode depends on operating frequency and the number of data transitions
in the data payload.
8.4.6 Acquire Mode (PLL approaches lock)
The PLL is enabled and attempts to lock to the input Clock. All outputs remain in high-impedance mode. When
the PLL monitor detects stable PLL operation, the device switches from Acquire to Transmit mode. For proper
device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended
operating conditions. If the pixel clock frequency is larger than 3 MHz but smaller than f PCLK(min), the
SN65LVDS301 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel
clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may not
be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL
deadlock (loss of VCO oscillation).
8.4.7 Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK pin outputs a copy of PCLK.
Based on the selected mode of operation, the D0, D1, and D2 outputs carry the serialized data. In 1-channel
mode, outputs D1 and D2 remain high-impedance. In the 2-channel mode, output D2 remains high-impedance.
8.4.8 Status Detect and Operating Modes Flow diagram
The SN65LVDS301 switches between the power saving and active modes in the following way:
Power Up
TXEN = 1
CLK Inactive
Power Up
TXEN = 0
TXEN Low
> 10 ms
TXEN High > 10 ms
Shutdown
Mode
Standby
Mode
PCLK
Stops or Lost
PCLK
Active
TXEN Low
> 10 ms
PCLK
Stops or Lost
Power Up
TXEN = 1
CLK Active
TXEN Low
> 10 ms
PLL Achieved Lock
Transmit
Mode
Acquire
Mode
Figure 8-7. Status Detect and Operating Modes Flow Diagram
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Table 8-3. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
Shutdown Mode
Least amount of power consumption(1) (most circuitry turned TXEN is low(1) (2)
off); All outputs are high-impedance
Standby Mode
Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or
is disabled to conserve power); All outputs are high-
impedance
inactive(2)
Acquire Mode
Transmit Mode
PLL tries to achieve lock; All outputs are high-impedance
TXEN is high; PCLK input monitor detected input
activity
Data transfer (normal operation); Transmitter serializes data TXEN is high and PLL is locked to incoming clock
and transmits data on serial output; unused outputs remain
high-impedance
(1) In Shutdown Mode, all SN65LVDS301 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
(2) Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied
to a valid logic level VIL or VIH during Shutdown or Standby Mode.
Table 8-4. Operating Mode Transitions
MODE TRANSITION
USE CASE
TRANSITION SPECIFICS
Shutdown → Standby
Drive TXEN high to enable
transmitter
1. TXEN high > 10 μs
2. Transmitter enters standby mode
a. All outputs are high-impedance
b. Transmitter turns on clock input monitor
1. PCLK input monitor detects clock input activity;
2. Outputs remain high-impedance;
Standby → Acquire
Acquire → Transmit
Transmitter activity detected
Link is ready to transfer data
3. PLL circuit is enabled
1. PLL is active and approaches lock
2. PLL achieved lock within 2 ms
3. Parallel Data input latches into shift register
4. CLK output turns on
5. selected Data outputs turn on and send out first serial data bit
1. PCLK Input monitor detects missing PCLK
2. Transmitter indicates standby, putting all outputs into high-impedance;
3. PLL shuts down;
Transmit → Standby
Request Transmitter to enter
Standby mode by stopping
PCLK
4. PCLK activity input monitor remains active
1. TXEN pulled low for longer than 10us
Transmit/Standby →
Shutdown
Turn off Transmitter
2. Transmitter indicates standby, putting output CLK+ and CLK– into high-
impedance state;
3. Transmitter puts all other outputs into high-impedance state
4. Most IC circuitry is shut down for least power consumption
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9 Application information
9.1 Application Information
General application guidelines and hints for LVDS drivers and receivers may be found in the LVDS application
notes and design guides.
9.2 Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
Input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
9.3 VGA Application
Figure 9-1 shows a possible implementation of a VGA display. The LVDS301 interfaces to the SN65LVDS302,
which is the corresponding receiver device to deserialize the data and drive the display driver. The pixel clock
rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The application assumes 24-
bit color resolution. It is also shown, how the application processor provides a powerdown (reset) signal for both
serializer and the display driver. The signal count over the FPC could be further decreased by using the standby
option on the SN65LVDS302 and pulling RXEN high with a 30 kΩ resistor to VDD
.
2x0.1uF
2x0.1uF
FPC
GND
2.7V
1.8V
GND
GND
2.7V
1.8V
GND
2x0.01uF
2x0.01uF
Application
Processor
(e.g. OMAP)
Video Mode Display
Driver
CLK+
CLK-
CLK+
CLK-
D0+
22MHz
D0+
D0-
330Mbps
330Mbps
Pixel CLK
PCLK
PCLK
D0-
22MHz
22MHz
D1+
D1-
D1+
D1-
R[7:0]
G[7:0]
B[7:0]
D[7:0]
D[15:8]
R[7:0]
G[7:0]
B[7:0]
D[23:16]
HS,VS,DE
27
27
HS,VS,DE
HS,VS,DE
SN65LVDS301
SN65LVDS302
1.8V
1.8V
If FPC wire count is critical, replace this
connection with a pull-up resistor at RXEN
Serial port interface
(3-wire IF)
3
Figure 9-1. Typical VGA Display Application
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9.4 Dual LCD-Display Application
The example in Figure 9-2 shows a possible application setup driving two video mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to QVGA
resolution at 60 Hz refresh rate and 10% blanking overhead.
2x0.1uF
2x0.1uF
FPC
GND
2.7V
1.8V
GND
GND
2.7V
1.8V
GND
2x0.01uF
2x0.01uF
Display Driver1
Application
Processor
(e.g. OMAP)
21
CLK+
CLK-
CLK+
CLK-
D0+
5.5MHz
PCLK
PCLK
Pixel CLK
PCLK
5.5MHz
R[5:0]
G[5:0]
B[5:0]
D0+
D0-
EN
330Mbps
SIN
SOUT
SCLK
D0-
D[5:0]
D[11:6]
D[17:12]
HS,VS,DE
R[5:0]
G[5:0]
B[5:0]
HS,VS,DE
HS,VS,DE
18+3
SN65LVDS301
SN65LVDS302
Display Driver2
PCLK
EN
1.8V
1.8V
SIN
SOUT
SCLK
Figure 9-2. Example Dual-QVGA Display Application
9.5 Typical Application Frequencies
The SN65LVDS301 supports pixel clock frequencies from 4 MHz to 65 MHz over 1, 2, or 3 data lanes. Table 9-1
provides a few typical display resolution examples and shows the number of data lanes necessary to connect
the LVDS301 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is
smaller, resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh
rate of 60 Hz or 90 Hz. The actual refresh rate may differ depending on the application-processor clock
implementation.
Table 9-1. Typical Application Data Rates & Serial Lane Usage
Display Screen
Resolution
Visible Pixel Blanking
Display
Refresh
Rate
Pixel Clock Frequency
[MHz]
Serial Data Rate Per Lane
Count
Overhead
1-ChM
2-ChM
3-ChM
176x220 (QCIF+)
240x320 (QVGA)
640x200
38,720
76,800
20%
90 Hz
60 Hz
4.2 MHz
5.5 MHz
125 Mbps
166 Mbps
276 Mbps
316 Mbps
335 Mbps
332 Mbps
432 Mbps
442 Mbps
128,000
146,432
154,880
153,600
200,000
204,800
307,200
327,680
409,920
480,000
786,432
9.2 MHz
138 Mbps
158 Mbps
167 Mbps
166 Mbps
216 Mbps
221 Mbps
332 Mbps
354 Mbps
443 Mbps
352x416 (CIF+)
352x440
10.5 MHz
11.2 MHz
11.1 MHz
14.4 MHz
14.7 MHz
22.1 MHz
23.6 MHz
29.5 MHz
34.6 MHz
56.6 MHz
320x480 (HVGA)
800x250
640x320
640x480 (VGA)
1024x320
221 Mbps
236 Mbps
295 Mbps
346 Mbps
566 Mbps
854x480 (WVGA)
800x600 (SVGA)
1024x768 (XGA)
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9.5.1 Calculation Example: HVGA Display
This example calculation shows a typical Half-VGA display with these parameters:
Display Resolution:
Frame Refresh Rate:
480 x 320
58.4 Hz
Hsync = 5
Visible area = 480 column
HFP = 20
Horizontal Visible Pixel:
Horizontal Front Porch:
Horizontal Sync:
480 columns
20 columns
5 columns
3 columns
Vsync = 5
VBP = 3
Horizontal Back Porch:
Vertical Visible Pixel:
Vertical Front Porch:
Vertical Sync:
320 lines
10 lines
5 lines
Visible area
= 320 lines
Visible area
Vertical Back Porch:
3 lines
VFP = 10
Entire display
Figure 9-3. HVGA Display Parameters
Calculation of the total number of pixel and Blanking overhead:
Visible Area Pixel Count:
Total Frame Pixel Count:
Blanking Overhead:
480 × 320 = 153600 pixel
(480+20+5+3) × (320+10+5+3) = 171704 pixel
(171704-153600) ÷ 153600 = 11.8 %
The application requires following serial-link parameters:
Pixel Clk Frequency:
Serial Data Rate:
171704 × 58.4 Hz = 10.0 MHz
1-channel mode: 10.0 MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10.0 MHz × 15 bit/channel = 150 Mbps
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10 Power Supply Design Recommendation
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
10.1 Decoupling Recommendation
The SN65LVDS301 was designed to operate reliably in a constricted environment with other digital switching
ICs. In many designs, the SN65LVDS301 often shares a power supply with the application processor. The
SN65LVDS301 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS301 power pins. The use
of four ceramic capacitors (2×0.01 μF and 2×0.1 μF) provides good performance. At the very least, it is
recommended to install one 0.1 μF and one 0.01 μF capacitor near the SN65LVDS301. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS301 on the bottom of the pcb is often a good choice.
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11 Layout
11.1 Layout Guidelines
Use chamfered corners (45° bends) instead of right-angle (90°) bends. Right-angle bends increase the effective
trace width, which changes the differential trace impedance creating large discontinuities. A 45° bend is seen as
a smaller discontinuity.
When routing traces next to a via or between an array of vias, make sure that the via clearance section does not
interrupt the path of the return current on the ground plane below.
Avoid metal layers and traces underneath or between the pads of the LVDS connectors for better impedance
matching. Otherwise they cause the differential impedance to drop below 75 Ω and fail the board during TDR
testing.
Use solid power and ground planes for 100 Ω impedance control and minimum power noise.
For a multilayer PCB, TI recommends keeping one common GND layer underneath the device and connect all
ground terminals directly to this plane. For 100 Ω differential impedance, use the smallest trace spacing
possible, which is usually specified by the PCB vendor.
Keep the trace length as short as possible to minimize attenuation.
Place bulk capacitors (10 μF) close to power sources, such as voltage regulators or where the power is supplied
to the PCB.
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12 Device and Documentation Support
12.1 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.2 Trademarks
FlatLink™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
nFBGA® is a registered trademark of Tessera, Inc..
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.4 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Nov-2020
PACKAGING INFORMATION
Orderable Device
SN65LVDS301ZQE
SN65LVDS301ZQER
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQE
80
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
LVDS301
ACTIVE
BGA
ZQE
2500
Green (RoHS
& no Sb/Br)
SNAGCU
-40 to 85
LVDS301
MICROSTAR
JUNIOR
SN65LVDS301ZXH
SN65LVDS301ZXHR
ACTIVE
ACTIVE
NFBGA
ZXH
ZXH
80
80
360
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
LVDS301
LVDS301
NFBGA
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
ZXH0080A
NFBGA - 1 mm max height
S
C
A
L
E
3
.
0
0
0
BALL GRID ARRAY
5.1
4.9
A
B
BALL A1 CORNER
INDEX AREA
5.1
4.9
0.7
0.6
C
1 MAX
SEATING PLANE
0.08 C
BALL TYP
0.25
TYP
0.15
4 TYP
SYMM
J
H
G
F
SYMM
80X
4
E
D
C
B
A
TYP
0.35
0.25
0.15
0.05
C B
C
A
0.5 TYP
1
2
3
4
5
6
7
8
9
0.5 TYP
4221325/A 01/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis is for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This is a Pb-free solder ball design.
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EXAMPLE BOARD LAYOUT
ZXH0080A
NFBGA - 1 mm max height
BALL GRID ARRAY
(0.5) TYP
0.265
0.235
80X
6
7
9
2
3
4
5
8
1
A
B
C
(0.5) TYP
D
E
F
G
H
J
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
0.05 MIN
METAL
UNDER
MASK
(
0.25)
METAL
(
0.25)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221325/A 01/2014
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SBVA017 (www.ti.com/lit/sbva017).
www.ti.com
EXAMPLE STENCIL DESIGN
ZXH0080A
NFBGA - 1 mm max height
BALL GRID ARRAY
(0.5) TYP
80X ( 0.25)
(R0.05) TYP
5
4
3
6
7
9
2
8
1
A
(0.5)
TYP
B
C
METAL
TYP
D
E
F
G
H
J
SYMM
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:20X
4221325/A 01/2014
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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