SN65LVDS33-EP [TI]
HIGH-SPEED DIFFERENTIAL RECEIVER; 高速差分接收器
| 型号： | SN65LVDS33-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL RECEIVER |
| 文件： | 总23页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS33-EP, SN65LVDT33-EP
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SGLS309B–JUNE 2005–REVISED APRIL 2007
HIGH-SPEED DIFFERENTIAL RECEIVER
FEATURES
•
•
TTL Inputs Are 5-V Tolerant
•
•
•
Controlled Baseline – One Assembly/Test
Site, One Fabrication Site
Pin-Compatible With the AM26LS32,
SN65LVDS32B, µA9637, SN65LVDS9637B
Extended Temperature Performance of Up to
–55°C to 125°C
DESCRIPTION
Enhanced Diminishing Manufacturing Sources
(DMS) Support
This family of four LVDS data line receivers offers
the widest common-mode input voltage range in the
industry. These receivers provide an input voltage
range specification compatible with a 5-V PECL
signal as well as an overall increased ground-noise
tolerance. They are in industry standard footprints
with integrated termination as an option.
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
400-Mbps Signaling Rate (2) and 200-Mxfr/s
Data Transfer Rate
•
•
Operates With a Single 3.3-V Supply
Precise control of the differential input voltage
thresholds allows for inclusion of 50 mV of input
voltage hysteresis to improve noise rejection on
slowly changing input signals. The input thresholds
are still no more than +50 mV over the full input
common-mode voltage range.
–4 V to 5 V Common-Mode Input Voltage
Range
•
•
Differential Input Thresholds < ±50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
Integrated 110-Ω Line Termination Resistors
On LVDT Products
•
•
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level Output
With No Input
•
•
Bus-Pin ESD Protection Exceeds 15-kV HBM
Input Remains High-Impedance On Power
Down
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
(2) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
ORDERING INFORMATION(1)
TA
PACKAGE(2)
Reel of 2500
Reel of 2500
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LVDS33M
SOIC - D
SOIC - D
SN65LVDS33MDREP
SN65LVDT33MDREP(3)
–55°C to 125°C
LVDT33M
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(3) Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2005–2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS33-EP, SN65LVDT33-EP
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SGLS309B–JUNE 2005–REVISED APRIL 2007
DESCRIPTION (CONTINUED)
The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at
the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external
resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or
other termination circuits.
The receivers can withstand ±15-kV human-body model (HBM) and ±600-V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) failsafe circuit that provides a high-level output within 600 ns after
loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these
fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of
the SN65LVDS32B application note.
The intended application and signaling technique of these devices is point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDS33-EP is characterized for operation from –55°C to 125°C.
FUNCTION TABLE(1)
SN65LVDS33 and SN65LVDT33
DIFFERENTIAL INPUT
VID = VA – VB
ENABLES
OUTPUT
G
H
X
H
X
H
X
L
G
X
L
Y
H
H
?
VID ≥ –32 mV
X
L
–100 mV < VID ≤ –32 mV
?
X
L
L
VID ≤ –100 mV
L
X
H
X
L
Z
H
H
H
X
Open
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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SGLS309B–JUNE 2005–REVISED APRIL 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
Attenuation
Network
6.5 kΩ
6.5 kΩ
V
CC
1 pF
60 kΩ
B Input
A Input
200 kΩ
3 pF
7 V
7 V
7 V
7 V
250 kΩ
LVDT Only 110 Ω
V
CC
V
CC
300 kΩ
(G Only)
100 Ω
Enable
Inputs
37 Ω
Y Output
7 V
7 V
300 kΩ
(G Only)
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SGLS309B–JUNE 2005–REVISED APRIL 2007
150C (2 YRS)
Estimated Wirebond life at Elevated Temperature for device LVDS33MD
0.1
0.01
195C ( 16 days)
175C ( 98 days)
185C (40 days)
150C (2 YRS)
0.001
0.0001
0.00001
0.000001
Silicon Operating Life Design Goal is 10 years @ 105C Junction Temperature
0.0021
0.0022
0.0023
0.0024
0.0025
0.0026
0.0027
1/JUNCTION TEMP IN DEG K
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE/UNIT
(2)
Supply voltage range, VCC
–0.5 V to 4 V
–1 V to 6 V
–5 V to 6 V
1 V
Enables or Y
Voltage range
A or B
|VA – VB| (LVDT)
A, B, and GND(3)
All pins(4)
Electrostatic discharge
Class 3, A: 15 kV, B: 500 V
±500 V
Charged-device mode
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATINGS
T
A ≤ 25°C
OPERATING FACTOR(1)
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PACKAGE
POWER RATING
ABOVE TA = 25°C
D16
950 mW
7.6 mW/°C
494 mW
189 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
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SGLS309B–JUNE 2005–REVISED APRIL 2007
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX UNIT
VCC
VIH
VIL
Supply voltage
3.3
3.6
5
V
V
V
High-level input voltage
Low-level input voltage
Enables
Enables
LVDS
2
0
0.8
3
0.1
|VID
|
Magnitude of differential input voltage
V
LVDT
0.8
5
VI or VIC
TA
Voltage at any bus terminal (separately or common-mode)
Operating free-air temperature
–4
°C
–55
125
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VIT1
VIT2
VIT3
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential input failsafe voltage threshold
50
VIB = –4 V or 5 V, See Figure 2
See Table 1 and Figure 5
mV
–50
–32
–100
mV
V
Differential input voltage hysteresis,
VIT1 – VIT2
VID(HYS)
50
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –4 mA
IOL = 4 mA
2.4
V
V
0.4
25
G at VCC, No load,
G at GND
Steady state
16
ICC
Supply current
SN65LVDx33
SN65LVDS
mA
1.1
6
VI = 0 V,
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
VIC= –4 V or 5 V
VIC= –4 V or 5 V
±25
±25
±80
±45
±50
±50
±180
±95
±5
VI = 2.4 V,
VI = –4 V,
μA
VI = 5 V,
Input current
(A or B inputs)
II
VI = 0 V,
VI = 2.4 V,
VI = –4 V,
SN65LVDT
μA
VI = 5 V,
SN65LVDS
SN65LVDT
VID = 100 mV,
VID = 200 mV,
μA
Differential input current
IIO
(IIA – IIB
)
1.55
2.4
mA
VA or VB = 0 V or 2.4 V, VCC = 0 V
VA or VB = –4 or 5 V, VCC = 0 V
VA or VB = 0 V or 2.4 V, VCC = 0 V
VA or VB = –4 V or 5 V, VCC = 0 V
VIH = 2 V
±25
±60
±35
±120
12
SN65LVDS
SN65LVDT
Power-off input current
(A or B inputs)
II(OFF)
μA
IIH
IIL
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
μA
μA
μA
pF
VIL = 0.8 V
12
IOZ
CI
–10
12
Input capacitance, A or B input to GND
VI = 0.4 sin (4E6πt) + 0.5 V
5
(1) All typical values are at 25°C and with a 3.3-V supply.
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 3
CL = 10 pF,
MIN TYP(1)
MAX
8
UNIT
ns
ns
ns
μs
ps
ps
ns
ns
ns
ns
ns
ns
ns
tPLH(1) Propagation delay time, low-to-high level output
1.8
1.8
4
4
tPHL(1) Propagation delay time, high-to-low level output
8
td1
Delay time, failsafe deactivate time
Delay time, failsafe activate time
Pulse skew (|tPHL(1) – tPLH(1)|)
Output skew(2)
11
2
See Figure 3 and Figure 6
td2
0.2
tsk(p)
tsk(o)
200
150
tsk(pp) Part-to-part skew(3)
See Figure 3
1.2
tr
Output signal rise time
0.8
0.8
5.5
4.4
3.8
7
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time, high level-to-high impedance output
Propagation delay time, low level-to-high impedance output
Propagation delay time, high impedance-to-high level output
Propagation delay time, high impedance-to-low level output
12
12
12
12
See Figure 4
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven
together.
(3) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
I
IA
A
B
V
O
Y
V
ID
V
IA
I
IB
(V + V )/2
V
O
IA
IB
V
IC
V
IB
Figure 1. Voltage and Current Definitions
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1000 Ω
100 Ω
†
100 Ω
V
ID
1000 Ω
V
O
10 pF,
+
V
IC
2 Places
−
10 pF
†
Remove for testing LVDT device.
V
IT1
0 V
V
ID
−100 mV
V
O
100 mV
0 V
V
ID
V
IT2
V
O
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions
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V
ID
V
IA
V
O
C
L
= 10 pF
V
IB
V
V
1.4 V
IA
1 V
IB
0.4 V
V
ID
0 V
−0.4 V
t
t
PLH
PHL
V
OH
80%
20%
80%
1.4 V
V
O
20%
V
OL
t
f
t
r
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ±0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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B
A
1.2 V
500 Ω
10 pF
±
V
O
Inputs
G
G
V
TEST
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse
r
f
repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . C includes instrumentation and fixture
L
capacitance within 0,06 mm of the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G
G
2 V
1.4 V
0.8 V
t
t
PLZ
PLZ
t
t
PZL
PZL
2.5 V
1.4 V
OL
OL
Y
V
V
+0.5 V
V
TEST
0
1.4 V
A
G
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
t
PHZ
G
t
PHZ
t
t
PZH
PZH
V
V
OH
OH
−0.5 V
Y
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
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Table 1. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages
APPLIED VOLTAGES(1)
VIA (mV) VIB (mV)
–4000 –3900
RESULTANT INPUTS
VID (mV)
–100
–32
VIC (mV)
–3950
–3984
4950
Output
L
H
L
–4000
4900
4968
–3968
5000
5000
–100
–32
4984
H
(1) These voltages are applied for a minimum of 1.5 µs.
V
V
IA
−100 mV @ 250 KHz
IB
V
O
a) No Failsafe
V
IA
−32 mV @ 250 KHz
V
IB
V
O
Failsafe Asserted
b) Failsafe Asserted
Figure 5. VIT3 Failsafe Threshold Test
1.4 V
1 V
0.4 V
>1.5 µs
0 V
−0.2 V
−0.4 V
t
d1
t
d2
V
OH
1.4 V
V
OL
Figure 6. Waveforms for Failsafe Activate and Deactivate
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TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
4
3
4
3
V
T
A
= 3.3 V
= 25°C
V
= 3.3 V
CC
CC
T = 25°C
A
2
1
2
1
0
0
0
10
20
30
40
−40
−30
−20
−10
0
I
− Low-Level Output Current − mA
I
OH
− High-Level Output Current − mA
OL
Figure 7.
Figure 8.
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
5
4.5
4
4.5
4
V
= 3 V
CC
V
= 3 V
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3
3.5
3
−50
0
50
100
−50
0
50
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY
140
120
V
= 3.3 V
100
80
CC
V
CC
= 3.6 V
60
40
V
CC
= 3 V
20
0
0
100
150
200
f − Switching Frequency − MHz
Figure 11.
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APPLICATION INFORMATION
0.01 µF
≈3.6 V
16
V
CC
5 V
1
2
1B
1A
0.1 µF
(see Note A)
1N645
(2 places)
100 Ω
15
14
4B
4A
3
4
5
6
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Operation With 5-V Supply
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local Texas Instruments sales office or the Texas
Instruments Web site at www.ti.com for more information.
For more application guidelines, see the following documents:
•
•
•
•
•
•
Low-Voltage Differential Signalling Design Notes (SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
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APPLICATION INFORMATION (continued)
ACTIVE FAILSAFE FEATURE
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the
limitations seen in present solutions. A detailed theory of operation is presented in application note, The Active
Failsafe Feature of the SN65LVDS32B (SLLA082A).
Figure 13 shows one receiver channel with active failsafe. It consists of a main receiver that can respond to a
high-speed input differential signal. Also connected to the input pair are two failsafe receivers that form a window
comparator. The window comparator has a much slower response than the main receiver and it detects when
the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator outputs. When
failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 13. Receiver With Active Failsafe
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APPLICATION INFORMATION (continued)
ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a
design option, designers have been able to take advantage of LVDS by implementing a small resistor divider
network at the input of the LVDS receiver. Texas Instruments has taken the next step by introducing a wide
common-mode LVDS receiver (no divider network required) which can be connected directly to an ECL driver
with only the termination bias voltage required for ECL termination (VCC – 2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving five meters of CAT-5 cable and being
received by Texas Instruments wide common-mode receiver and the resulting eye-pattern. The values for R3
are required in order to provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1
simply needs to match the characteristic load impedance of 50 Ω. The R2 resistor is a small value and is
intended to minimize any possible common-mode current reflections.
V
V
CC
CC
R1 = 50 Ω
R2 = 50 Ω
I
I
CC
CC
V
B
5 Meters
of CAT-5
LV/PECL
LVDS
V
B
R3
R3
R1
R1
V
EE
R2
R3 = 240 Ω
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS33 at 500 Mbps Receiver Output (CH1)
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APPLICATION INFORMATION (continued)
TEST CONDITIONS
•
•
•
VCC = 3.3 V
TA = 25°C (ambient temperature)
All four channels switching simultaneously with NRZ data. The scope is pulse-triggered simultaneously with
NRZ data.
EQUIPMENT
•
•
•
Tektronix PS25216 programmable power supply
Tektronix HFS 9003 stimulus system
Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Tektronix PS25216
Programmable
Power Supply
Tektronix HFS 9003
Stimulus System
Trigger
Tektronix TDS 784D 4-Channel
Digital Phosphor Oscilloscope
− DPO
Bench Test Board
Figure 16. Equipment Setup
100 Mbit/s
200 Mbit/s
Figure 17. Typical Eye Pattern SN65LVDS33
17
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN65LVDS33MDREP
V62/05614-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS33-EP :
Catalog: SN65LVDS33
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS33MDREP
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN65LVDS33MDREP
D
2500
Pack Materials-Page 2
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