SN65LVDS93AIDGGRQ1 [TI]
10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器 | DGG | 56 | -40 to 85;
| 型号： | SN65LVDS93AIDGGRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10MHz – 135MHz 28 位平板显示器链路 LVDS 串行解串器发送器 | DGG | 56 | -40 to 85 显示器 |
| 文件： | 总35页 (文件大小：1897K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
SN65LVDS93A-Q1 FlatLink™ 发送器
1 特性
发送数据时，数据位 D0 至 D27 会在输入时钟信号
1
(CLKIN) 边沿逐个载入寄存器。 可通过时钟选择
(CLKSEL) 引脚来选择时钟的上升沿或下降沿。
CLKIN 的频率会进行 7 倍倍频，然后用于以串行方式
分 7 位时间片上传数据寄存器。 接着会将 4 个串行数
据流和锁相时钟 (CLKOUT) 输出至 LVDS 输出驱动
器。 CLKOUT 的频率与输入时钟 (CLKIN) 相同。
•
具有符合 AEC-Q100 标准的以下结果：
–
–
–
温度等级 3：-40°C 至 85°C
人体模型 (HBM) 静电放电 (ESD) 分类等级 3
充电器件模型 (CDM) ESD 分类等级 C6
•
低压差分信号 (LVDS) 显示系列接口，可直接连接
具有集成 LVDS 的 LCD 显示面板
•
•
封装：14mm x 6.1mm 薄型小外形尺寸 (TSSOP)
SN65LVDS93A-Q1 无需外部元件或者很少，而且也无
需控制。 发送器输入端的数据总线与接收器输出端的
相同，数据传输对于用户而言是透明的。 用户唯一能
够干预的是选择时钟上升沿（向 CLKSEL 输入高电
平）或下降沿（向 CLKSEL 输入低电平），以及能够
使用关断/清零 (SHTDN) 引脚。 SHTDN 是一个低电
平有效输入，可禁用时钟并关断 LVDS 输出驱动器，
从而降低功耗。 该信号为低电平时，可将所有内部寄
存器置为低电平。
1.8V 至 3.3V 耐压数据输入，可直接连接低功耗、
低压应用和图形处理器
•
•
•
•
传输速率高达 135Mpps（每秒百万像素）；像素时
钟频率范围为 10MHz 至 135MHz
适合 HVGA 到高清 (HD) 范围内的显示分辨率，并
且电磁干扰 (EMI) 较低
通过 3.3V 单电源供电运行，75MHz 频率下的功耗
为 170mW（典型值）
28 个数据通道 + 时钟输入低压晶体管-晶体管逻辑
(TTL)，4 个数据通道 + 时钟输出低压差分
SN65LVDS93A-Q1 额定工作环境温度范围为 -40°C
至 85°C。
•
•
•
•
禁用时的功耗不到 1mW
可选择上升或下降时钟沿触发输入
支持扩频时钟 (SSC)
器件信息(1)
器件型号
封装
封装尺寸（标称值）
兼容所有 OMAP™ 2x、OMAP™ 3x 和 DaVinci™
应用处理器
SN65LVDS93A-Q1
TSSOP (56)
14.00mm x 6.10mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
简化电路原理图
•
•
•
LCD 显示面板驱动器
超便携移动个人电脑 (UMPC) 和上网本
数码相框
3 说明
SN65LVDS93A-Q1 Flatlink™ 发送器在单个集成电路
上包含了四个 7 位并联负载串行输出移位寄存器、一
个 7X 时钟合成器以及五个低压差分信号 (LVDS) 线路
驱动器。 凭借这些功能，该器件可通过 5 条平衡双股
线同步发送 28 位单端低电压晶体管-晶体管逻辑
(LVTTL) 数据，这些数据将由 SN75LVDS94 和具有集
成 LVDS 接收器的 LCD 面板等兼容接收器来接收。
Application
processor
SN65LVDS93A-Q1
FlatLinkTM Transmitter
(e.g. OMAPTM
)
Package Options
TSSOP: 14 mm x 6.1 mm DGG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEM1
SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
目录
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application .................................................. 16
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 7
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 13
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 25
12 器件和文档支持 ..................................................... 27
12.1 商标....................................................................... 27
12.2 静电放电警告......................................................... 27
12.3 术语表 ................................................................... 27
13 机械、封装和可订购信息....................................... 27
7
8
4 修订历史记录
Changes from Revision A (February 2015) to Revision B
Page
•
•
Changed "Toggle LVDS83B" To "Toggle SN65LVDS93A-Q1" in item 4 in the Power Up Sequence section .................... 17
Changed "this allows the LVDS83B" To "this allows the SN65LVDS93A-Q1" in item 5 in the Power Up Sequence
section .................................................................................................................................................................................. 17
Changes from Original (February 2015) to Revision A
Page
•
•
已将特性中的“人体模型 (HBM) 静电放电 (ESD) 分类等级 2”更改为“人体模型 (HBM) 静电放电 (ESD) 分类等级 3” ............. 1
已删除特性中的“ESD：5kV HBM，1.5kV CDM”.................................................................................................................... 1
2
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
5 Pin Configuration and Functions
56-PIN
DGG PACKAGE
(TOP VIEW)
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D4
IOVCC
D5
D3
2
3
D2
D6
4
GND
D1
D7
5
GND
D8
D0
6
D27
GND
D9
7
D10
8
Y0M
9
VCC
D11
10
11
12
13
14
15
16
Y0P
Y1M
D12
D13
Y1P
LVDSVCC
GND
Y2M
GND
D14
D15
D16
Y2P
CLKSEL
D17
CLKOUTM
CLKOUTP
Y3M
17
18
19
20
21
22
23
24
25
26
27
28
40
39
38
37
36
35
34
33
32
31
30
29
D18
Y3P
D19
GND
D20
GND
GND
D21
PLLVCC
GND
D22
D23
SHTDN
CLKIN
IOVCC
D24
D26
GND
D25
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CMOS IN with Input pixel clock; rising or falling clock polarity is selectable by Control input
CLKIN
31
pulldn
CLKSEL.
CLKOUTP,
CLKOUTM
39
40
Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).
LVDS Out
CMOS IN with Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge
CLKSEL
17
pulldn
input clock trigger (CLKSEL = VIL).
2, 3, 4, 6
7, 8, 10, 11
12, 14, 15 , 16
D5, D6, D7, D8
Data inputs; supports 1.8 V to 3.3 V input voltage selectable by VDD supply. To
connect a graphic source successfully to a display, the bit assignment of D[27:0]
D9, D10, D11, D12
D13, D14, D15, D16
D17, D18, D19, D20
D21, D22, D23, D24
D25, D26, D27
18, 19, 20, 22 CMOS IN with is critical (and not necessarily intuitive).
23, 24, 25, 27
28, 30, 50
51, 52, 54, 55,
56
pulldn
For input bit assignment see Figure 15 to Figure 18 for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10,
D11, D16, D17, D23, and D27 to GND.
D0, D1, D2, D3, D4
5, 13, 21, 29,
33, 35, 36, 43,
49, 53
Power
GND
Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.
Supply(1)
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
Copyright © 2015, Texas Instruments Incorporated
3
SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Power
I/O supply reference voltage (1.8 V up to 3.3 V matching the GPU data output
signal swing)
IOVCC
1, 26
Supply(1)
Power
LVDSVCC
PLLVCC
SHTDN
VCC
44
34
32
9
3.3 V LVDS output analog supply
3.3 V PLL analog supply
Supply(1)
Power
Supply(1)
CMOS IN with Device shut down; pull low (de-assert) to shut down the device (low power,
pulldn
resets all registers) and high (assert) for normal operation.
Power
3.3 V digital supply voltage
Supply(1)
Y0P, Y0M
Y1P, Y1M
Y2P, Y2M
47, 48
45, 46
41, 42
Differential LVDS data outputs.
Outputs are high-impedance when SHTDN is pulled low (de-asserted)
LVDS Out
LVDS Out
Differential LVDS Data outputs.
Output is high-impedance when SHTDN is pulled low (de-asserted).
Note: if the application only requires 18-bit color, this output can be left open.
Y3P, Y3M
37, 38
4
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.5
–0.5
–0.5
MAX
4
UNIT
Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC(2)
Voltage range at any output terminal
Voltage range at any input terminal
Continuous power dissipation
V
V
V
VCC + 0.5
IOVCC + 0.5
See Thermal Information
–65 150
Storage temperature, Tstg
°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) All voltages are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q200-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q200-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
3
NOM
MAX
3.6
3.6
3.6
3.6
0.1
UNIT
Supply voltage, VCC
3.3
3.3
LVDS output Supply voltage, LVDSVCC
PLL analog supply voltage, PLLVCC
IO input reference supply voltage, IOVCC
Power supply noise on any VCC terminal
3
3
3.3
V
1.62
1.8 / 2.5 / 3.3
IOVCC = 1.8 V
IOVCC = 2.5 V
IOVCC = 3.3 V
IOVCC = 1.8 V
IOVCC = 2.5 V
IOVCC = 3.3 V
IOVCC/2 + 0.3 V
IOVCC/2 + 0.4 V
IOVCC/2 + 0.5 V
High-level input voltage, VIH
Low-level input voltage, VIL
V
V
IOVCC/2 - 0.3 V
IOVCC/2 - 0.4 V
IOVCC/2 - 0.5 V
Differential load impedance, ZL
Operating free-air temperature, TA
Virtual junction temperature, TJ
90
132
85
Ω
–40
°C
°C
105
6.4 Thermal Information
DGG
56 PINS
63.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
15.9
32.5
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
32.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated
5
SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
V
VT
Input voltage threshold
IOVCC/2
Differential steady-state output voltage
magnitude
mV
|VOD
|
250
450
35
RL = 100Ω, See Figure 7
Change in the steady-state differential
output voltage magnitude between
opposite binary states
Δ|VOD
|
1
mV
Steady-state common-mode output
voltage
VOC(SS)
VOC(PP)
1.125
1.375
35
V
See Figure 7
tR/F (Dx, CLKin) = 1ns
Peak-to-peak common-mode output
voltage
mV
IIH
IIL
High-level input current
Low-level input current
VIH = IOVCC
VIL = 0 V
25
±10
±24
±12
±20
μA
μA
VOY = 0 V
mA
mA
μA
IOS
Short-circuit output current
VOD = 0 V
IOZ
High-impedance state output current
VO = 0 V to VCC
IOVCC = 1.8 V
IOVCC = 3.3 V
200
100
Input pull-down integrated resistor on all
inputs (Dx, CLKSEL, SHTDN, CLKIN)
Rpdn
kΩ
μA
disabled, all inputs at GND;
SHTDN = VIL
IQ
Quiescent current (average)
2
100
SHTDN = VIH, RL = 100Ω (5 places),
grayscale pattern (Figure 8)
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
51.9
0.4
I(IOVCC) with IOVCC = 3.3 V
I(IOVCC) with IOVCC = 1.8 V
mA
mA
mA
mA
0.1
SHTDN = VIH, RL = 100Ω (5 places), 50%
transition density pattern (Figure 8),
VCC = 3.3 V, fCLK = 75 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 3.3 V
I(IOVCC) with IOVCC = 1.8 V
53.3
0.6
0.2
SHTDN = VIH, RL = 100Ω (5 places), worst-
case pattern (Figure 9),
VCC = 3.6 V, fCLK = 75 MHz
ICC
Supply current (average)
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 3.3 V
I(IOVCC) with IOVCC = 1.8 V
63.7
1.3
0.5
SHTDN = VIH, RL = 100Ω (5 places), worst-
case pattern (Figure 9),
fCLK = 100 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 3.6 V
I(IOVCC) with IOVCC = 1.8 V
81.6
1.6
0.6
SHTDN = VIH, RL = 100Ω (5 places), worst-
case pattern (Figure 9),
fCLK = 135 MHz
I(VCC) + I(PLLVCC) + I(LVDSVCC)
I(IOVCC) with IOVCC = 3.6 V
I(IOVCC) with IOVCC = 1.8 V
102.2
2.1
0.8
2
mA
pF
CI
Input capacitance
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
6.6 Timing Requirements
PARAMETER
MIN
MAX
100
8%
UNIT
Input clock period, tc
Input clock modulation
7.4
ns
with modulation frequency 30 kHz
with modulation frequency 50 kHz
6%
High-level input clock pulse width duration, tw
Input signal transition time, tt
0.4 tc
0.6 tc
3
ns
ns
ns
ns
Data set up time, D0 through D27 before CLKIN (See Figure 6)
Data hold time, D0 through D27 after CLKIN
2
0.8
Dn
CLKIN
or
CLKIN
CLKOUT
Previous cycle
Next
Current cycle
Y0
D7+1
D0-1
D7
D18
D26
D23
D6
D15
D25
D17
D4
D14
D24
D16
D3
D13
D22
D11
D2
D12
D21
D10
D1
D9
D0
D8
Y1
Y2
Y3
D8-1
D19-1
D27-1
D18+1
D26+1
D23+1
D20
D5
D19
D27
Figure 1. Typical SN65LVDS93A-Q1 Load and Shift Sequences
LVDSVCC
IOVCC
5W
YnP or
YnM
D or
SHTDN
50W
10kW
7V
7V
300kW
Figure 2. Equivalent Input and Output Schematic Diagrams
Copyright © 2015, Texas Instruments Incorporated
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SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Delay time, CLKOUT↑ after Yn valid
(serial bit position 0, equal D1, D9,
D20, D5)
t0
t1
t2
t3
t4
t5
-0.1
0
0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
7 tc + 0.1
ns
Delay time, CLKOUT↑ after Yn valid
(serial bit position 1, equal D0, D8,
D19, D27)
1
2
3
4
5
6
1
2
3
4
5
6
/
/
/
/
/
/
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
7 tc - 0.1
/
/
/
/
/
/
ns
ns
ns
ns
ns
Delay time, CLKOUT↑ after Yn valid
(serial bit position 2, equal D7, D18,
D26. D23)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 3; equal D6, D15,
D25, D17)
See Figure 10, tC = 10ns,
|Input clock jitter| < 25ps
(2)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 4, equal D4, D14,
D24, D16)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 5, equal D3, D13,
D22, D11)
Delay time, CLKOUT↑ after Yn valid
(serial bit position 6, equal D2, D12,
D21, D10)
t6
ns
ns
tc(o)
Output clock period
tc
tC = 10ns; clean reference clock, see
Figure 11
±26
tC = 10ns with 0.05UI added noise
modulated at 3MHz, see Figure 11
±44
±35
(3)
Δtc(o)
Output clock cycle-to-cycle jitter
ps
tC = 7.4ns; clean reference clock,
see Figure 11
tC = 7.4ns with 0.05UI added noise
modulated at 3MHz, see Figure 11
±42
High-level output clock pulse
duration
4
tw
/
7 tc
ns
ps
µs
ns
Differential output voltage transition
time (tr or tf)
tr/f
ten
tdis
See Figure 7
225
6
500
Enable time, SHTDN↑ to phase lock
(Yn valid)
f(clk) = 135 MHz, See Figure 12
f(clk) = 135 MHz, See Figure 13
Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)
7
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed
over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
8
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
6.8 Typical Characteristics
100
90
800
700
600
500
400
300
200
Output Jitter
Input Jitter
80
V
CC
= 3.6V
70
60
50
V
= 3.3V
CC
40
V
= 3V
70
CC
100
0
30
20
0.01
0.10
1
10
10
30
50
90
110
130
f
- Input Modular Frequency - MHz
f
- Clock Frequency - MHz
(mod)
clk
CLK Frequency During Test = 100 MHz
Total Device Current (Using Grayscale pattern) Over Pixel Clock
Frequency
Figure 3. Average Grayscale ICC vs Clock Frequency
Figure 4. Output Clock Jitter vs Input Clock Jitter
PRBS Data Signal
CLKL Signal
t
- Time - 1ns/div
k
Clock Signal = 135 MHz
Figure 5. Typical PRBS Output Signal Over One Clock Period
Copyright © 2015, Texas Instruments Incorporated
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7 Parameter Measurement Information
tsu
thold
Dn
CLKIN
All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns.
CLKSEL = 0 V.
Figure 6. Set Up and Hold Time Definition
49.9W ꢀ1 ꢁ( ꢂPLCS
Yꢂ
V
OD
V
YM
OL
ꢀ001
801
V
ODꢁHS
0V
V
ODꢁPS
(01
01
t
t
r
f
V
OLꢁꢂꢂS
V
V
OLꢁCCS
OLꢁCCS
0V
Figure 7. Test Load and Voltage Definitions for LVDS Outputs
10
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Parameter Measurement Information (continued)
CLKIN
D0,8,16
D1,9,17
D2,10,18
D3,11,19
D4-7,12-15,20-23
D24-27
The 16 grayscale test pattern test device power consumption for a typical display pattern.
Figure 8. 16 Grayscale Test Pattern
T
CLKIN
EVEN Dn
ODD Dn
The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
Figure 9. Worst-Case Power Test Pattern
t7
CLKIN
CLKOUT
t6
t5
t4
t3
t2
t1
t0
Yn
VOD(H)
0.00V
VOD(L)
~2.5V
CLKOUT
or Yn
1.40V
CLKIN
~0.5V
t7
t0-6
CLKOUT is shown with CLKSEL at high-level.
CLKIN polarity depends on CLKSEL input level.
Figure 10. SN65LVDS93A-Q1 Timing Definitions
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www.ti.com.cn
Parameter Measurement Information (continued)
Device
Under
Test
+
Reference
VCO
+
Modulation
v(t) = A sin(2 pf
t)
mod
HP8656B Signal
Generator,
0.1 MHz-990 MHz
HP8665A Synthesized
Signal Generator,
0.1 MHz-4200 MHz
Device Under
Test
DTS2070C
Digital
TimeScope
Input
RF Output
CLKIN
CLKOUT
RF Output
Modulation Input
Figure 11. Output Clock Jitter Test Set Up
CLKIN
Dn
ten
SHTDN
Yn
Invalid
Valid
Figure 12. Enable Time Waveforms
CLKIN
tdis
SHTDN
CLKOUT
Figure 13. Disable Time Waveforms
12
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ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
8 Detailed Description
8.1 Overview
FlatLink™ is an LVDS SerDes data transmission system. The SN65LVDS93A-Q1 takes in three (or four) data
words each containing seven single-ended data bits and converts this to an LVDS serial output. Each serial
output runs at seven times that of the parallel data rate. The deserializer (receiver) device operates in the
reverse manner. The three (or four) LVDS serial inputs are transformed back to the original seven-bit parallel
single-ended data. FlatLink™ devices are available in 21:3 or 28:4 SerDes ratios.
•
The 21-bit devices are designed for 6-bit RGB video for a total of 18 bits in addition to three extra bits for
horizontal synchronization, vertical synchronization, and data enable.
•
The 28-bit devices are intended for 8-bit RGB video applications. Again, the extra four bits are for horizontal
synchronization, vertical synchronization, data enable, and the remaining is the reserved bit. These 28-bit
devices can also be used in 6-bit and 4-bit RGB applications as shown in the subsequent system diagrams.
8.2 Functional Block Diagram
Parallel-Load 7-bit
Shift Register
D0, D1, D2, D3,
D4, D6, D7
7
7
7
7
Y0P
Y0M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
Shift Register
D8, D9, D12, D13,
D14, D15, D18
Y1P
Y1M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
ShiftRegister
D19, D20, D21, D22,
D24, D25, D26
Y2P
Y2M
A,B,...G
SHIFT/LOAD
>CLK
Parallel-Load 7-bit
Shift Register
D27, D5, D10, D11,
D16, D17, D23
Y3P
Y3M
A,B,...G
SHIFT/LOAD
>CLK
Control Logic
SHTDN
7X Clock/PLL
7XCLK
CLKOUTP
CLKOUTM
>CLK
CLKIN
CLKINH
CLKSEL
RISING/FALLING EDGE
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8.3 Feature Description
8.3.1 TTL Input Data
The data inputs to the transmitter come from the graphics processor and consist of up to 24 bits of video
information, a horizontal synchronization bit, a vertical synchronization bit, an enable bit, and a spare bit. The
data can be loaded into the registers upon either the rising or falling edge of the input clock selectable by the
CLKSEL pin. Data inputs are 1.8 V to 3.3 V tolerant for the SN65LVDS93A-Q1 and can connect directly to low-
power, low-voltage application and graphic processors. The bit mapping is listed in Table 1.
Table 1. Pixel Bit Ordering
RED
R0
R1
R2
R3
R4
R5
R6
R7
GREEN
G0
BLUE
B0
LSB
G1
B1
G2
B2
4-bit MSB
6-bit MSB
G3
B3
G4
B4
G5
B5
G6
B6
8-bit MSB
G7
B7
8.3.2 LVDS Output Data
The pixel data assignment is listed in Table 2 for 24-bit, 18-bit, and 12-bit color hosts.
Table 2. Pixel Data Assignment
8-BIT
6-BIT
4-BIT
SERIAL
CHANNEL
DATA BITS
NON-LINEAR STEP LINEAR STEP
FORMAT-1
FORMAT-2
FORMAT-3
SIZE
SIZE
VCC
GND
R0
D0
D1
R0
R1
R2
R3
R2
R3
R0
R1
R2
R3
D2
R2
R4
R4
R2
R0
Y0
Y1
Y2
D3
R3
R5
R5
R3
R1
R1
D4
R4
R6
R6
R4
R2
R2
D6
R5
R7
R7
R5
R3
R3
D7
G0
G2
G2
G0
G2
VCC
GND
G0
D8
G1
G3
G3
G1
G3
D9
G2
G4
G4
G2
G0
D12
D13
D14
D15
D18
D19
D20
D21
D22
D24
D25
D26
G3
G5
G5
G3
G1
G1
G4
G6
G6
G4
G2
G2
G5
G7
G7
G5
G3
G3
B0
B2
B2
B0
B2
VCC
GND
B0
B1
B3
B3
B1
B3
B2
B4
B4
B2
B0
B3
B5
B5
B3
B1
B1
B4
B6
B6
B4
B2
B2
B5
B7
B7
B5
B3
B3
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
HSYNC
VSYNC
ENABLE
14
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ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
Table 2. Pixel Data Assignment (continued)
8-BIT
6-BIT
4-BIT
SERIAL
CHANNEL
DATA BITS
NON-LINEAR STEP LINEAR STEP
FORMAT-1
FORMAT-2
FORMAT-3
SIZE
GND
GND
GND
GND
GND
GND
GND
CLK
SIZE
GND
GND
GND
GND
GND
GND
GND
CLK
D27
D5
R6
R7
R0
R1
GND
GND
GND
GND
GND
GND
GND
CLK
GND
GND
GND
GND
GND
GND
GND
CLK
D10
D11
D16
D17
D23
CLKIN
G6
G0
Y3
G7
G1
B6
B0
B7
B1
RSVD
CLK
RSVD
CLK
CLKOUT
8.4 Device Functional Modes
8.4.1 Input Clock Edge
The transmission of data bits D0 through D27 occurs as each are loaded into registers upon the edge of the
CLKIN signal, where the rising or falling edge of the clock may be selected via CLKSEL. The selection of a clock
rising edge occurs by inputting a high level to CLKSEL, which is achieved by populating pull-up resistor to pull
CLKSEL=high. Inputting a low level to select a clock falling edge is achieved by directly connecting CLKSEL to
GND.
8.4.2 Low Power Mode
The SN65LVDS93A-Q1 can be put in low-power consumption mode by active-low input SHTDN#. Connecting
pin SHTDN# to GND will inhibit the clock and shut off the LVDS output drivers for lower power consumption. A
low-level on this signal clears all internal registers to a low-level. Populate a pull-up to VCC on SHTDN# to
enable the device for normal operation.
Copyright © 2015, Texas Instruments Incorporated
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This section describes the power up sequence, provides information on device connectivity to various GPU and
LCD display panels, and offers a PCB routing example.
9.2 Typical Application
J1
U1H
J2
sma_surface
C3
GND1
C5
GND2
D3
GND3
F5
J3
GND4
sma_surface
G3
H3
J5
A1
B1
F2
U1A
GND5
D1
D2
GND6
CLKM
CLKP
GND7
J4
PLLGND
LVDSGND1
LVDSGND2
sma_surface
H2
H1
Y0P
Y0M
G2
G1
J5
sma_surface
Y1P
Y1M
SN65LVDS93A-Q1ZQL
E1
E2
Y2P
Y2M
J6
sma_surface
IOVCC
C2
C1
Y3P
Y3M
R4
R5
R6
R7
R8
R9
R10
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
J7
sma_surface
JMP1
SN65LVDS93A-Q1ZQL
U1B
J2
D0
D1
D2
D3
D4
D6
D7
D0
K1
D1
K2
1
2
J8
sma_surface
D2
J3
D3
K3
D4
J4
J9
D6
K5
D7
sma_surface
14
Header 7x2
SN65LVDS93A-Q1ZQL
J10
sma_surface
IOVCC
R11
4.7k
R12
4.7k
R13
4.7k
R14
4.7k
R15
4.7k
R16
4.7k
R17
4.7k
sma_surface
JMP2
U1C
K6
D8
D8
J6
D9
1
2
D9
IOVCC
IOVCC
G5
D12
D13
D14
D15
D18
D12
G6
D13
F6
D14
E5
D15
D5
D18
14
R1
R2
Header 7x2
4.7k
SN65LVDS93A-Q1ZQL
IOVCC
R18
4.7k
R19
4.7k
R20
4.7k
R21
4.7k
R22
4.7k
R23
4.7k
R24
4.7k
JMP6
U1G
JMP3
B3
SHTDN
U1D
SHTDN
1
3
2
4
D4
CLKSEL
C6
D19
D19
D20
D21
D22
D24
D25
D26
CLKSEL
1
2
B6
D20
Header 2x2
B5
D21
A6
D22
SN65LVDS93A-Q1ZQL
A4
D24
B4
D25
A3
D26
14
U1J
E3
NC1
E4
Header 7x2
NC2
F3
NC3
SN65LVDS93A-Q1ZQL
F4
NC4
IOVCC
R25
4.7k
R26
4.7k
R27
4.7k
R28
4.7k
R29
4.7k
R30
4.7k
R31
4.7k
SN65LVDS93A-Q1ZQL
JMP4
U1E
K4
D5
D5
VCC
IOVCC
1
2
H4
D10
H6
D10
D11
D16
D17
D23
D27
U1I
D11
E6
D16
G4
VCC
B2
D6
PLLVCC
F1
LVDSVCC
D17
A5
D23
J1
D27
14
H5
IOVCC1
C4
IOVCC2
Header 7x2
SN65LVDS93A-Q1ZQL
SN65LVDS93A-Q1ZQL
IOVCC
VCC
VCC
VCC
C31
1uF
C32
0.1uF
C33
0.01uF
C34
1uF
C35
0.1uF
C36
0.01uF
C40
1uF
C41
C42
C37
1uF
C38
C39
0.1uF
0.01uF
0.1uF
0.01uF
PLACE UNDER LVDS93A-Q1
(bottom pcb side)
Figure 14. Schematic Example (SN65LVDS93A-Q1 Evaluation Board)
16
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Typical Application (continued)
9.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
VCC
VCCIO
CLKIN
3.3 V
1.8 V
Falling edge
High
SHTDN#
Format
18-bit GPU to 24-bit LCD
9.2.2 Detailed Design Procedure
9.2.2.1 Power Up Sequence
The SN65LVDS93A-Q1 does not require a specific power up sequence.
It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to
GND. The input level of the SHTDN during this time does not matter as only the input stage is powered up while
all other device blocks are still powered down.
It is also permitted to power up all 3.3V power domains while IOVCC is still powered down to GND. The device
will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH, regardless of their true
input voltage level. Hence, connecting SHTDN to GND will still be interpreted as a logic HIGH; the LVDS output
stage will turn on. The power consumption in this condition is significantly higher than standby mode, but still
lower than normal mode.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (SN65LVDS93A-Q1 SHTDN input initially low):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Enable video source output; start sending black video data.
4. Toggle SN65LVDS93A-Q1 shutdown to SHTDN = VIH.
5. Send >1ms of black video data; this allows the SN65LVDS93A-Q1 to be phase locked, and the display to
show black data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (SN65LVDS93A-Q1 SHTDN input initially high):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set SN65LVDS93A-Q1 input SHTDN = GND; wait for 250ns.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
9.2.2.2 Signal Connectivity
While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the
industry has aligned over the years on a certain data format (bit order). Figure 15 through Figure 18 show how
each signal should be connected from the graphic source through the SN65LVDS93A-Q1 input, output and
LVDS LCD panel input. Detailed notes are provided with each figure.
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24-bpc GPU
SN65LVDS93A-Q1
FORMAT1 FORMAT2 (See Note A)
R0(LSB)
R1
R2
D0
D1
D27
D5
D2
D3
D4
D6
D27
D5
D7
D8
D0
D1
D2
D3
R3
R4
R5
R6
Y0M
Y0P
100
100
to column
driver
D4
R7(MSB)
G0(LSB)
G1
D6
Y1M
Y1P
D10
D11
D7
FPC
Cable
LVDS
timing
Controller
G2
G3
D9
Y2M
Y2P
100
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
D8
G4
D9
(8bpc, 24bpp)
G5
G6
D12
D13
D14
D16
D17
D15
D18
D19
D20
D21
D22
D24
D25
D26
D23
Y3M
Y3P
100
to row driver
G7(MSB)
B0(LSB)
B1
CLKOUTM
CLKOUTP
100
B2
B3
B4
B5
24-bpp LCD Display
B6
B7(MSB)
HSYNC
VSYNC
ENABLE
RSVD (Note C)
CLK
CLKIN CLKIN
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note B)
Main Board
Note A. FORMAT: The majority of 24-bit LCD display panels require the two most significant bits (2 MSB ) of each
color to be transferred over the 4th serial data output Y3. A few 24-bit LCD display panels require the two LSBs of
each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by
checking the LCD display data sheet.
•
Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the
dominate data format for LCD panels.
•
Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel.
Note B. Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Note C. If RSVD is not driven to a valid logic level, then an external connection to GND is recommended.
Note D. RSVD must be driven to a valid logic level. All unused SN65LVDS93A-Q1 inputs must be tied to a valid logic
level.
Figure 15. 24-Bit Color Host to 24-Bit LCD Panel Application
18
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ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
18-bpp GPU
SN65LVDS93A-Q1
R0(LSB)
R1
R2
D0
D1
D2
R3
R4
D3
D4
D6
Y0M
Y0P
100
R5(MSB)
to column
driver
D27
D5
D7
D8
Y1M
Y1P
100
G0(LSB)
G1
G2
FPC
Cable
D9
Y2M
Y2P
LVDS
100
timing
Controller
(6-bpc, 18-bpp)
G3
G4
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
G5(MSB)
CLKOUTM
CLKOUTP
100
to row driver
B0(LSB)
B1
B2
B3
B4
B5(MSB)
18-bpp LCD Display
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
3.3V
C2
3.3V
C3
4.8k
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note B)
Main Board
Note A. Leave output Y3 NC.
Note B.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 16. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application
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12-bpp GPU
SN65LVDS93A-Q1
(See Note B)
R2 or VCC
R3 or GND
R0
D0
D1
D2
R1
R2
D3
D4
D6
Y0M
Y0P
100
100
R3(MSB)
to column
driver
D27
D5
D7
D8
Y1M
Y1P
(See Note B)
G2 or VCC
G3 or GND
G0
FPC
Cable
D9
Y2M
Y2P
LVDS
timing
Controller
100
G1
G2
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
(6-bpc, 18-bpp)
G3(MSB)
CLKOUTM
CLKOUTP
100
to row driver
(See Note B)
B2 or VCC
B3 or GND
B0
B1
B2
18-bpp LCD Display
B3(MSB)
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 N.C.
Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of
the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic
range, connect D1, D8, and D18 to GND.
R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color
space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect
D0, D7, and D15 to VCC.
Note C.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 17. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application
20
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
24-bpp GPU
SN65LVDS93A-Q1
R0 and R1: NC
(See Note B)
R2
D0
R3
R4
D1
D2
R5
R6
D3
D4
D6
Y0M
Y0P
100
R7(MSB)
to column
driver
D27
D5
D7
D8
G0 and G1: NC
(See Note B)
Y1M
Y1P
100
G2
G3
FPC
Cable
G4
G5
G6
D9
Y2M
Y2P
LVDS
100
timing
Controller
(6-bpc, 18-bpp)
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
G7(MSB)
CLKOUTM
CLKOUTP
100
to row driver
B0 and B1: NC
(See Note B)
B2
B3
B4
B5
B6
B7(MSB)
18-bpp LCD Display
B0 and B1: NC
(See Note B)
Y3M
Y3P
(See Note A)
HSYNC
VSYNC
ENABLE
RSVD
CLK
4.8k
3.3V
C2
3.3V
C3
1.8V or 2.5V
or 3.3V
C1
Rpullup
Rpulldown
(See Note C)
Main Board
Note A. Leave output Y3 NC.
Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down
to18-bit per pixel.
NoteC.Rpullup: install only to use rising edge triggered clocking.
Rpulldown: install only to use falling edge triggered clocking.
•
•
•
C1: decoupling cap for the VDDIO supply; install at least 1x0.01µF.
C2: decoupling cap for the VDD supply; install at least 1x0.1µF and 1x0.01µF.
C3: decoupling cap for the VDDPLL and VDDLVDS supply; install at least 1x0.1µF and 1x0.01µF.
Figure 18. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
Copyright © 2015, Texas Instruments Incorporated
21
SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
9.2.2.3 PCB Routing
Figure 19 shows a possible breakout of the data input and output signals on two layers of a printed circuit board.
D27
D5
D10
D11
D16
D17
D23
Y0M
Y0P
D19
D20
D21
Y1M
Y1P
D22
D24
Y2M
Y2P
D25
D26
D8
D9
CLKINM
CLKINP
D12
D13
D14
D15
D18
Y3M
Y3P
D0
D1
D2
D3
D4
D6
D7
Figure 19. Printed Circuit Board Routing Example (See Figure 14 for the Schematic)
9.2.3 Application Curve
250
200
150
100
50
0
1
4
7
10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Pixel Samples
Figure 20. 18b GPU to 24b LCD
22
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
10 Power Supply Recommendations
Power supply PLL, IO, and LVDS pins must be uncoupled from each.
11 Layout
11.1 Layout Guidelines
11.1.1 Board Stackup
There is no fundamental information about how many layers should be used and how the board stackup should
look. Again, the easiest way the get good results is to use the design from the EVMs of Texas Instruments. The
magazine Elektronik Praxis has published an article with an analysis of different board stackups. These are listed
in Table 3. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a
GND plane. Better is the use of a four-layer PCB, with a GND and a VCC plane and two signal layers. If the
circuit is complex and signals must be routed as stripline, because of propagation delay and/or characteristic
impedance, a six-layer stackup should be used.
Table 3. Possible Board Stackup on a Four-Layer PCB
MODEL 1
SIG
MODEL 2
SIG
MODEL 3
SIG
MODEL 4
GND
SIG
Layer 1
Layer 2
SIG
GND
GND
Layer 3
VCC
VCC
SIG
VCC
SIG
Layer 4
GND
SIG
VCC
Decoupling
EMC
Good
Bad
Good
Bad
Bad
Bad
Bad
Bad
Signal Integrity
Self Disturbance
Bad
Bad
Good
Satisfaction
Bad
Satisfaction
Satisfaction
High
11.1.2 Power and Ground Planes
A complete ground plane in high-speed design is essential. Additionally, a complete power plane is
recommended as well. In a complex system, several regulated voltages can be present. The best solution is for
every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers
just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In
a mixed-signal design, e.g., using data converters, the manufacturer often recommends splitting the analog
ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part. Take
care when using split ground planes because:
•
•
Split ground planes act as slot antennas and radiate.
A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal,
and the signal can induce noise into the nonrelated reference plane (Figure 21).
•
With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the
ground plane. Always take care of the return current (Figure 22).
For Figure 22, do not route a signal referenced to digital ground over analog ground and vice versa. The return
current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal
induces noise, due to crosstalk (dotted red line) into the analog ground plane.
Copyright © 2015, Texas Instruments Incorporated
23
SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
Figure 21. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting
Figure 22. Crosstalk Induced by the Return Current Path
11.1.3 Traces, Vias, and Other PCB Components
A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the
characteristic impedance changes. This impedance change causes reflections.
•
•
•
Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any
impedance change, the best routing would be a round bend (see Figure 23).
Separate high-speed signals (e.g., clock signals) from low-speed signals and digital from analog signals;
again, placement is important.
To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route
them with 90° to each other.
24
Copyright © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
Figure 23. Poor and Good Right Angle Bends
11.2 Layout Example
Figure 24. SN65LVDS93A-Q1 EVM Top Layer – TSSOP Package
Copyright © 2015, Texas Instruments Incorporated
25
SN65LVDS93A-Q1
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
www.ti.com.cn
Layout Example (continued)
Figure 25. SN65LVDS93A-Q1 EVM VCC Layer – TSSOP Package
26
版权 © 2015, Texas Instruments Incorporated
SN65LVDS93A-Q1
www.ti.com.cn
ZHCSDA2B –FEBRUARY 2015–REVISED APRIL 2015
12 器件和文档支持
12.1 商标
OMAP, DaVinci, Flatlink are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2015, Texas Instruments Incorporated
27
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JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
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TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
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客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
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在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
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TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
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应用
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www.ti.com.cn/audio
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计算机及周边
消费电子
能源
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DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
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IMPORTANT NOTICE
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Copyright © 2015, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LVDS93AIDGGRQ1
ACTIVE
TSSOP
DGG
56
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
LVDS93AQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS93AIDGGRQ1 TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN65LVDS93AIDGGRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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