SN65LVDS9637BDR [TI]
HIGH-SPEED DIFFERENTIAL RECEIVERS; 高速差分接收器
| 型号： | SN65LVDS9637BDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL RECEIVERS |
| 文件： | 总20页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
SN65LVDS32B
SN65LVDT32B
Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard for Signaling
Rates up to 400 Mbps
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
†
Operates With a Single 3.3-V Supply
G
G
1B
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
–2-V to 4.4-V Common-Mode Input Voltage
Range
4B
4A
4Y
G
SN65LVDT32B
ONLY (4 Places)
1A
1Y
Differential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
1Y
G
1B
2Y
2A
11 3Y
10 3A
2A
2B
Integrated 110-Ω Line Termination
Resistors Offered With the LVDT Series
2B
2Y
3Y
4Y
9
GND
3B
Propagation Delay Times 4 ns (typ)
3A
3B
4A
4B
Active Fail Safe Assures a High-Level
Output With No Input
Bus-Pin ESD Protection Exceeds
15 kV HBM
Inputs Remain High-Impedance on Power
Down
SN65LVDS3486B
SN65LVDT3486B
Recommended Maximum Parallel Rate of
200 M-Transfers/s
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
Available in Small-Outline Package With
1,27 mm Terminal Pitch
SN65LVDT3486B
1B
1A
V
CC
4B
1
2
3
4
5
6
7
8
16
15
14
13
12
ONLY (4 Places)
1A
1B
Pin-Compatible With the AM26LS32,
MC3486, or µA9637
1Y
1Y
4A
1,2EN
1,2EN
2Y
4Y
description
2A
2B
3,4EN
2Y
3Y
4Y
2A
11 3Y
10 3A
This family of differential line receivers offers
improved performance and features that imple-
ment the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS is defined in
the TIA/EIA-644 standard. This improved perfor-
mance represents the second generation of
receiver products for this standard, providing a
better overall solution for the cabled environment.
This generation of products is an extension to TI’s
overall product portfolio and is not necessarily a
replacement for older LVDS receivers.
2B
3A
3B
GND
9
3B
3,4EN
4A
4B
SN65LVDS9637B
SN65LVDT9637B
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
Improved features include an input common-
mode voltage range 2 V wider than the minimum
required by the standard. This will allow longer
cable lengths by tripling the allowable ground
noise tolerance to 3 V between a driver and
receiver. TI has additionally introduced an even
wider input common-mode voltage range of –4 to
5 V in their SN65LVDS/T33 and SN65LVDS/T34.
V
1A
1
2
3
4
8
7
6
5
CC
1A
1Y
2Y
1B
1Y
2Y
2A
2B
1B
SN65LVDT9637B
GND
ONLY
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
description (continued)
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage
hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more
than ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates
this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available
for multidrop or other termination circuits.
The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and
SN65LVDT9637B are characterized for operation from -40°C to 85°C.
AVAILABLE OPTIONS
NUMBER OF
RECEIVERS
TERMINATION
RESISTOR
†
PART NUMBER
SYMBOLIZATION
†
SN65LVDS32BD
SN65LVDT32BD
4
4
4
4
2
2
No
Yes
No
LVDS32B
LVDT32B
LVDS3486
LVDT3486
DK637B
SN65LVDS3486BD
SN65LVDT3486BD
SN65LVDS9637BD
SN65LVDT9637BD
Yes
No
Yes
DR637B
†
Add the suffix R for taped and reeled carrier.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
Function Tables
SN65LVDS32B and SN65LVDT32B
DIFFERENTIAL INPUT
A-B
ENABLES
OUTPUT
Y
G
G
H
X
X
L
H
H
V
ID
≥ -32 mV
H
X
X
L
?
?
-100 mV < V ≤ -32 mV
ID
H
X
X
L
L
L
V
ID
≤ -100 mV
X
L
H
Z
H
X
X
L
H
H
Open
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SN65LVDS3486B and SN65LVDT3486B
DIFFERENTIAL INPUT
A-B
ENABLES
OUTPUT
EN
H
Y
H
?
V
≥ -32 mV
ID
-100 mV < V ≤ -32 mV
H
ID
V
ID
≤ -100 mV
X
H
L
L
Z
H
Open
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SN65LVDS9637B and SN65LVDT9637B
DIFFERENTIAL INPUT
A-B
OUTPUT
Y
H
?
V
≥ -32 mV
ID
-100 mV < V ≤ -32 mV
ID
V
ID
≤ -100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
equivalent input and output schematic diagrams
V
CC
Attenuation
Network
6.5 kΩ
6.5 kΩ
V
CC
1 pF
60 kΩ
B Input
A Input
200 kΩ
3 pF
7 V
7 V
7 V
7 V
250 kΩ
LVDT Only 110 Ω
V
CC
V
CC
300 kΩ
(G Only)
50 Ω
Enable
Inputs
37 Ω
Y Output
7 V
7 V
300 kΩ
(EN and G Only)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 3 V
CC
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to 6 V
V – V (LVDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
A
B
Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 15 kV, B: 600 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
OPERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D8
725 mW
5.8 mW/°C
7.6 mW/°C
377 mW
D16
950 mW
494 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
High-level input voltage, V
IH
Enables
Enables
LVDS
V
Low-level input voltage, V
0.8
3
V
IL
0.1
V
Magnitude of differential input voltage,
V
ID
LVDT
0.8
4.4
85
V
Voltage at any bus terminal (separately or common-mode), V or V
–2
V
I
IC
Operating free-air temperature, T
–40
°C
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential input fail-safe voltage threshold
Differential input voltage hysteresis,
50
IT1
IT2
IT3
V
IB
= –2 V or 4.4 V,
See Figures 1 and 2
mV
–50
–32
See Table 1 and Figure 5
–100
mV
mV
V
50
16
ID(HYS)
V
IT1
- V
IT2
V
V
High-level output voltage
Low-level output voltage
I
I
= –4 mA
2.4
V
V
OH
OH
= 4 mA
0.4
23
OL
OL
G or EN at V
Steady-state
,
No load,
CC
‘32B or ‘3486B
‘9637B
I
Supply current
mA
CC
G or EN at GND
No load,
1.1
8
5
12
Steady-state
V = 0 V,
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
±20
±20
±40
±40
±40
±40
±80
±80
I
V =2.4 V,
I
SN65LVDS
SN65LVDT
µA
V = –2 V,
I
V = 4.4 V,
I
I
Input current (A or B inputs)
Differential input current
I
V = 0 V,
I
V =2.4 V,
I
µA
V =–2 V,
I
V = 4.4 V,
I
V
= 100 mV,
V
= –2 V or 4.4 V,
ID
See Figure 1
IC
SN65LVDS
SN65LVDT
±3
2.22
±20
µA
I
I
ID
(I - I
IA IB
)
V
ID
= 0.2 V,
V
IC
= –2 V or 4.4 V
1.55
mA
V
or V = 0 V or 2.4 V,
B
= 0 V
A
V
CC
or V = –2 V or 4.4 V,
SN65LVDS
SN65LVDT
V
A
B
= 0 V
±35
±30
±50
V
CC
or V = 0 V or 2.4 V,
Power-off input current
(A or B inputs)
µA
I(OFF)
V
A
B
= 0 V
V
CC
or V = –2 V or 4.4 V,
V
A
B
= 0 V
V
V
V
CC
I
I
I
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
= 2 V
10
10
µA
µA
µA
pF
IH
IH
IL
= 0.8 V
IL
±10
OZ
C
Input capacitance, A or B input to GND
V = 0.4 sin (4E6πt) + 0.5 V
I
5
I
†
All typical values are at 25°C and with a 3.3 V supply.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, fail-safe deactivate time
TEST CONDITIONS
MIN TYP
MAX
6
UNIT
ns
ns
ns
µs
ps
ps
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
2.5
2.5
4
4
PLH
PHL
d1
See Figure 3
6
9
See Figures 3 and 6
Delay time, fail-safe activate time
0.3
1.5
d2
Pulse skew (|t
– t
|)
200
150
sk(p)
sk(o)
sk(pp)
r
PHL1 PLH1
§
Output skew
Part-to-part skew
C
= 10 pF,
L
‡
1
See Figure 3
Output signal rise time
Output signal fall time
0.8
0.8
5.5
4.4
3.8
7
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance -to-high-level output
Propagation delay time, high-impedance-to-low-level output
9
9
9
9
PHZ
PLZ
PZH
PZL
See Figure 4
†
‡
All typical values are at 25°C and with a 3.3-V supply.
t
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
sk(pp)
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
is the magnitude of the time difference between the t or t of all receivers of a single device with all of their inputs driven together.
§
t
sk(o)
PLH
PHL
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
V
O
Y
V
ID
V
IA
I
IB
(V + V )/2
IA IB
V
O
V
IC
V
IB
Figure 1. Voltage and Current Definitions
1000 Ω
†
100 Ω
100 Ω
V
ID
1000 Ω
V
O
10 pF,
+
V
IC
2 Places
–
10 pF
†
Removed for testing the LVDT device
V
IT1
0 V
V
ID
–100 mV
V
O
100 mV
0 V
V
ID
V
IT2
V
O
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
Figure 2. V
and V
Input Voltage Threshold Test Circuit and Definitions
IT2
IT1
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
V
ID
V
IA
V
O
C
= 10 pF
V
IB
L
V
V
1.4 V
IA
1 V
IB
0.4 V
V
ID
0 V
–0.4 V
t
t
PLH
PHL
V
OH
1.4 V
80%
20%
80%
20%
V
O
V
OL
t
t
r
f
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
r
f
Pulsewidth = 10 ±0.2 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 3. Timing Test Circuit and Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
B
1.2 V
500 Ω
A
10 pF
±
V
O
G
V
TEST
Inputs
G
1,2,EN, or 3,4, EN
NOTE: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse
r
f
repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 ±10 ns . C includes instrumentation and fixture
L
capacitance within 0,06 mm of the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G, 1,2EN,or 3,4EN
G
2 V
1.4 V
0.8 V
t
t
PLZ
PLZ
t
t
PZL
PZL
Y
2.5 V
1.4 V
OL
OL
V
V
+0.5 V
V
TEST
0
1.4 V
A
2 V
G, 1,2EN,or 3,4EN
G
1.4 V
0.8 V
2 V
1.4 V
0.8 V
t
t
PHZ
PHZ
t
t
PZH
PZH
Y
V
V
OH
OH
–0.5 V
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum V
Input Threshold Test Voltages
IT3
†
APPLIED VOLTAGES
RESULTANT INPUTS
V
IA
(mV) (mV)
V
V
(mV)
V (mV)
IC
Output
IB
ID
–100
–2000
–2000
4300
–1900
–1968
4400
–1950
–1984
4350
L
H
L
–32
–100
–32
4368
4400
4384
H
†
These voltages are applied for a minimum of 1.5 µs.
V
V
IA
–100 mV @ 250 KHz
IB
V
O
a) No Failsafe
V
IA
–32 mV @ 250 KHz
V
IB
V
O
Failsafe Asserted
b) Failsafe Asserted
Figure 5. V
Failsafe Threshold Test
IT3
1.4 V
1 V
0.4 V
>1.5 µs
0 V
–0.2 V
–0.4 V
t
t
d2
d1
V
OH
1.4 V
V
OL
Figure 6. Waveforms for Failsafe Activate and Deactivate
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
4
3
4
3
V
T
A
= 3.3 V
= 25°C
V
= 3.3 V
CC
CC
T = 25°C
A
2
1
2
1
0
0
0
10
20
30
40
–40
–30
–20
–10
0
I
– Low-Level Output Current – mA
I
OH
– High-Level Output Current – mA
OL
Figure 7
Figure 8
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
5
4.5
4
4.5
4
V
= 3 V
V
= 3 V
CC
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3
3.5
3
–50
0
50
100
–50
0
50
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 9
Figure 10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
140
120
V
= 3.3 V
100
80
CC
V
= 3.6 V
CC
60
40
V
CC
= 3 V
20
0
0
100
150
200
f – Switching Frequency – MHz
Figure 11
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
0.01 µF
≈3.6 V
16
V
CC
5 V
1
2
1B
1A
0.1 µF
(see Note A)
1N645
(2 places)
100 Ω
15
14
4B
4A
3
4
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
5
6
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
NOTES: A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground plane. The
CC
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to V or GND as appropriate.
CC
Figure 12. Operation with 5-V Supply
related information
IBISmodelingisavailableforthisdevice. PleasecontactthelocalTIsalesofficeortheTIWebsiteatwww.ti.com
for more information.
For more application guidelines, please see the following documents:
Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
terminated failsafe
A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. Current
LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated fail-safe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Fail-Safe Feature of the SN65LVDS32A, literature number SLLA082.
Figure 13 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to
a high-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form a
window comparator. The window comparator has a much slower response than the main receiver and detects
when the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs.
When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 13. Receiver With Terminated Failsafe
15
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SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
ECL/PECL-to-LVTTL conversion with TI’s LVDS receiver
The various versions of emitter-coupled logic (i.e. ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
LVDSprovide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network
at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDSreceiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (V
– 2 V).
CC
Figures 14 and 15 show the use of an LV/PECL driver driving 5 meters of CAT–5 cable and being received by
TI’s wide common-mode receiver and the resulting eye pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
V
V
CC
I
CC
I
R1 = 50 Ω
R2 = 50 Ω
CC
CC
V
B
5 Meters
of CAT-5
LV/PECL
LVDS
V
B
R3
R3
R1
R1
V
EE
R2
R3 = 240 Ω
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Figure 15. LV/PECL to Remote SN65LVDS32B at 500 Mbps Receiver Output (CH1)
16
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SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
APPLICATION INFORMATION
test conditions
V
= 3.3 V
CC
T = 25°C (ambient temperature)
A
All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with
NRZ data.
equipment
Tektronix PS25216 programmable power supply
Tektronix HFS 9003 stimulus system
Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Tektronix PS25216
Programmable
Power Supply
Tektronix HFS 9003
Stimulus System
Trigger
Tektronix TDS 784D 4-Channel
Digital Phosphor
Bench Test Board
Oscilloscope – DPO
Figure 16. Equipment Setup
100 Mbit/s
200 Mbit/s
Figure 17. Typical Eye Pattern SN65LVDS32B
17
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SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B
SN65LVDT3486B, SN65LVDS9637B, SN65LVDT9637B
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS440A – OCTOBER 2000 – REVISED MAY 2001
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN65LVDS32BD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
8
40
2500
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDS32BDR
SN65LVDS3486BD
SN65LVDS3486BDR
SN65LVDS9637BD
SN65LVDS9637BDR
SN65LVDT32BD
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
2500
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
8
2500
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
16
16
16
16
8
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDT32BDR
SN65LVDT3486BD
SN65LVDT3486BDR
SN65LVDT9637BD
SN65LVDT9637BDR
2500
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
2500
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
8
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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