SN65LVDT348DRG4 [TI]
QUAD LINE RECEIVER, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16;
| 型号： | SN65LVDT348DRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD LINE RECEIVER, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总25页 (文件大小：674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS348 , SN65LVDT348
SN65LVDS352, SN65LVDT352
www.ti.com
SLLS523E–FEBRUARY 2002–REVISED MAY 2004
QUAD HIGH-SPEED DIFFERENTIAL RECEIVERS
FEATURES
DESCRIPTION
•
•
•
Meets or Exceeds the Requirements of ANSI
TIA/EIA-644A Standard
The
SN65LVDS352, and SN65LVDT352 are high-speed,
quadruple differential receivers with wide
common-mode input voltage range. This allows
receipt of TIA/EIA-644 signals with up to 3-V of
SN65LVDS348,
SN65LVDT348,
a
Single-Channel Signaling Rates up to
560 Mbps
-4 V to 5 V Common-Mode Input Voltage
Range
ground noise or
a variety of differential and
single-ended logic levels. The '348 is in a 16-pin
package to match the industry-standard footprint of
the DS90LV048. The '352 adds two additional VCC
and GND pins in a 24-pin package to provide higher
data transfer rates with multiple receivers in
operation. All offer a flow-through architecture with all
inputs on one side and outputs on the other to ease
board layout and reduce crosstalk between
receivers. LVDT versions of both integrate a 110-Ω
line termination resistor.
•
•
Flow-Through Architecture
Active Failsafe Assures a High-level Output
When an Input Signal Is not Present
•
SN65LVDS348 Provides a Wide Common-
Mode Range Replacement for the
SN65LVDS048A or the DS90LV048A
APPLICATIONS
•
•
Logic Level Translator
Point-to-Point Baseband Data Transmission
Over 100-Ω Media
ECL/PECL-to-LVTTL Conversion
Wireless Base Stations
These receivers also provide 3x the standard's
minimum common-mode noise voltage tolerance.
The -4 V to 5 V common-mode range allows usage
in harsh operating environments or accepts LVPECL,
PECL, LVECL, ECL, CMOS, and LVCMOS levels
without level shifting circuitry. See the Application
Information Section for more details on the
ECL/PECL to LVDS interface.
•
•
•
Central Office or PABX Switches
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
550
Timer
SN65LVDS352PW
500
LVDT Device
Only
450
400
SN65LVDS348PW
350
(One of Four Shown)
300
15
2
-1 prbs NRZ, V = 0.4 V
ID
= 1.2 V, C = 5.5 pF, 40% Open Eye
L
250
200
V
IC
4 Receivers Switching, Input Jitter < 45 ps
-60
-40
-20
0
20
40
60
80
100
T - Free-Air Temperature - °C
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
SN65LVDS348 , SN65LVDT348
SN65LVDS352, SN65LVDT352
www.ti.com
SLLS523E–FEBRUARY 2002–REVISED MAY 2004
DESCRIPTION (CONTINUED)
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage
hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the full
input common-mode voltage range.
The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage.
This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent-pending) failsafe circuit that provides a high-level output approximately 600
ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for Wired-Or bus signaling.
The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space
requirements and parts count by eliminating the need for a separate termination resistor. This can also improve
signal integrity at the receiver by reducing the stub length from the line termination to the receiver.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from
-40°C to 85°C.
SN65LVDS348, SN65LVDT348
D or PW PACKAGE
(TOP VIEW)
SN65LVDS352, SN65LVDT352
PW PACKAGE
(TOP VIEW)
1
24
23
22
21
20
19
18
17
16
15
14
13
1A
1B
2A
NC
1Y
DGND1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
IN1–
R
IN1+
R
IN2+
R
IN2–
R
IN3–
R
IN3+
R
IN4+
R
IN4–
EN
2
R
R
V
OUT1
OUT2
CC
3
4
2B
V
CCD1
5
EN 1,2
2Y
NC
NC
3Y
GND
6
V
CCA
R
R
OUT3
7
AGND
EN 3,4
3A
OUT4
8
EN
9
V
CCD2
10
11
12
3B
4A
4B
DGND2
4Y
NC
NC – No internal connection
2
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
FUNCTIONAL BLOCK DIAGRAMS (one of four receivers shown)
To Three Other Receivers
348 Devices
To One Other Receiver
352 Devices
EN
EN
EN
R
IN+
A
R
OUT1
Y
R
IN–
B
Timer
Timer
SN65LVDT348
Only
SN65LVDT352
Only
Window Comparator
Window Comparator
AVAILABLE OPTIONS
PART NUMBER(1)
SN65LVDS348D
SN65LVDT348D
SN65LVDS348PW
SN65LVDT348PW
SN65LVDS352PW
SN65LVDT352PW
INTEGRATED TERMINATION
PACKAGE TYPE PACKAGE MARKING
SOIC
SOIC
LVDS348
LVDT348
DL348
√
√
√
TSSOP
TSSOP
TSSOP
TSSOP
DE348
DL352
DE352
(1) Add the R suffix to the device type (e.g., SN65LVDS348DR) for taped and reeled carrier.
FUNCTION TABLES
348 DEVICES
INPUTS
OUTPUTS
VID = VRIN+ - VRIN-
ID≥ -32 mV
100 mV < VID < -32 mV
EN
EN
L or OPEN
L or OPEN
L or OPEN
L or OPEN
X
ROUT
V
H
H
?
H
VID≤ -100 mV
H
L
Open
H
L or OPEN
X
H
Z
Z
X
H
352 DEVICES
INPUTS
OUTPUTS
VID = VIA - VIB
ID ≥ -32 mV
100 mV < VID < -32 mV
EN
H
Y
H
?
V
H
VID ≤ -100 mV
H
L
X
L or OPEN
H
Z
H
Open
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
6.5 kΩ
6.5 kΩ
1 pF
60 kΩ
Attenuation
Network
Attenuation
Network
R
IN+
, A
R , B
IN–
200 kΩ
7 V
7 V
250 kΩ
7 V
7 V
3 pF
110 Ω
’LVDT Only
Attenuation
Network
V
CC
V
CC
100 Ω
37 Ω
EN, EN
R
OUT,
Y
7 V
300 kΩ
7 V
4
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
-0.5 V TO 4 V
-0.5 V to 6 V
1 V
Supply voltage range(2), VCC,VCCA,VCCD1, and VCCD2
Enables, ROUT, or Y
Voltage range Differential input magnitude MVIDM (LVDT only)
RIN+, RIN-, A or B
-5 V to 6 V
Human body model(3)
A, B, RIN+, RIN- and GND
±15 kV
Electrostatic discharge
All pins
All pins
±7 kV
Charged-device model(4)
±500 V
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal (GND, AGND).
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
T
A ≤ 25°C
OPERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
POWER RATING
D16
950 mW
7.6 mW/°C
6.2 mW/°C
8.7 mW/°C
494 mW
402 mW
565 mW
PW16
PW24
774 mW
1087 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VCC,VCCA,VCCD1
and VCCD2
,
Supply voltage
3
3.3
3.6
V
VIH
VIL
High-level input voltage
Low-level input voltage
Enables
2
0
5
0.8
0.8
3
V
V
Enables
|VID| (LVDT348, 352)
|VID| (LVDS348, 352)
0.1
0.1
-4
Magnitude of differential
input voltage
V
Input voltage (any combination of common mode or input signals)
Operating free-air temperature
5
V
TA
-40
85
°C
5
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
Positive-going differential input voltage
threshold
VITH1
50
See Figure 1 and Figure 2
See Figure 1 and Table 1
mV
Negative-going differential input voltage
threshold
VITH2
VITH3
-50
-32
Differential input failsafe voltage threshold
-100
mV
mV
VID(HY Differential input voltage hysteresis,
50
VITH1 - VITH2
S)
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = -4 mA
IOL = 4 mA
2.4
V
V
0.4
20
4
Enabled, EN at VCC
,
EN at 0 V, No load
16
1.1
16
LVDS348,
LVDT348
mA
mA
Disabled, EN at 0 or EN at VCC
ICC
Supply current
Enabled, EN at VCC
Disabled, EN at 0
VI = -4 V,
,
No load
20
4
LVDS352,
LVDT352
1.1
Other input open
Other input 1.2 V
Other input open
Other input open
Other input open
Other input open
-75
-20
0
0
LVDS348,
LVDS352
0 V ≤ VI ≤ 2.4 V,
VI = 5 V,
0
µA
µA
40
0
Input current (RIN+, RIN-, A or B
inputs)
II
VI = -4 V,
-150
-40
0
LVDT348,
LVDT352
0 V ≤ VI ≤ 2.4 V,
VI = 5 V,
0
80
50
VCC = 1.5 V, VI = -4 V or 5 V, Other input open
-50
LVDS348,
LVDS352
µA
µA
VCC = 1.5 V, 0 V ≤ VI≤ 2.4 V, Other input
at 1.2 V
-20
-100
-40
20
100
40
Power-off input current (RIN+,
RIN-, A or B inputs)
II(OFF)
VCC = 1.5 V, VI = -4 V or 5 V, Other input open
LVDT348,
LVDT352
VCC = 1.5 V, VI = 0 V or 2.4 V, Other input
open
Differential input current
(IRIN+ - IRIN-, or IIA - IIB)
LVDS348,
LVDS352
IID
VID = 100 mV,
VIC = -3.9 V or 4.9 V
-4
4
µA
LVDT348,
LVDT352
RT
Differential input resistance
VCC = 0 V, VID = 250 mV, VI = 0 V or 2.4 V
90
111
132
Ω
IIH
IIL
High-level input current
Enables
Enables
VIH = 2 V
VIL = 0.8 V
VO = 0 V
0
0
10
10
10
µA
µA
µA
Low-level input current
IOZ
High-impedance output current
-10
Input capacitance, RIN+, RIN- input to GND or A
or B input to AGND
CIN
VI = 0.4 sin (4E6πft) + 0.5 V
5
pF
(1) All typical values are at 25°C and with a 3.3-V supply.
6
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
tPLH
tPHL
td1
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, failsafe disable time
2.5
2.5
4
4
6
6
ns
ns
ns
µs
ps
ps
ns
ns
ns
ps
ps
ns
ns
ns
ns
12
1.5
td2
Delay time, failsafe enable time
0.3
tsk(p)
tsk(o)
tsk(pp)
tr
Pulse skew (|tpHL1 - tpLH1|)
Output skew(2)
Part-to-part skew(3)
CL = 10 pF, See Figure 3
200
150
1
Output signal rise time
1.2
1
tf
Output signal fall time
tr
Output signal rise time
650
400
5
CL = 1 pF, See Figure 3
See Figure 4 and Figure 5
tf
Output signal fall time
tPHZ
tPLZ
tPZH
tPZL
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
9
9
5
8
12
12
8
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(o) is the magnitude of the time difference between the tPHL or tPLH of all receivers of a single device with all of their inputs connected
together.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
I
IA
or I
RIN+
A or R
IN+
Y or R
OUT
V
ID
I
or I
ROUT
OY
B or R
IN–
V
IA
or V
RIN+
I
or I
IB
RIN–
(V + V )/2 or
IA
IB
V
IC
V or V
OY ROUT
(V
RIN+
+ V
V
IB
or V
RIN–)/2
RIN–
Figure 1. Voltage and Current Definitions
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
1000 Ω
†
100 Ω
100 Ω
V
ID
1000 Ω
+
–
+
–
V
1
V
2
V
O
10 pF
10 pF
10 pF
+
–
V
IC
A. Remove for testing LVDT device.
B. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1ns.
C. Fixture capacitance ±20%.
D. Resistors are metal film, 1% tolerance, and surface mount
V
ITH1
0 V
V
ID
–100 mV
V
O
100 mV
0 V
V
ID
V
ITH2
V
O
Figure 2. VITH1 and VITH2, Input Voltage Threshold Test Circuit and Definitions
Table 1. Receiver Minimum and Maximum Failsafe Input Voltage
FAILSAFE THRESHOLD TEST VOLTAGES
APPLIED VOLTAGES(1)
RESULTANT INPUTS
Output
VIA (mV)
VIB (mV)
-3900
-3968
5000
VID (mV)
VIC (mV)
-3950
-3984
4950
-4000
-4000
4900
4968
-100
-32
L
H
L
-100
-32
5000
4984
H
(1) Voltage applied for greater than 1.5 µs.
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
A or R
IN+
Y or R
V
OUT
V
ID
V
IA
or V
RIN+
or V
B or R
OY
ROUT
IN–
C
L
V
IB
or V
RIN–
A or V
1.4 V
1 V
RIN+
B or V
RIN–
>1.5 µs
0.4 V
0 V
V
ID
–0.2 V
–0.4 V
t
t
t
d1
PHL
PLH
t
d2
V
OH
V
OY
or V
ROUT
V /2
CC
V
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 250
kHz, duty cycle = 50 ±2%, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is
±20%.
Figure 3. Timing Test Circuit and Waveforms
9
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
R
R
IN–
R
OUT
500 Ω
1.2 V
IN+
+
EN
EN
V
TEST
V
ROUT
_
Inputs
10 pF
2.5 V
V
TEST
V
RIN+
1 V
2 V
1.4 V
EN
0.8 V
2 V
1.4 V
0.8 V
EN
t
t
PLZ
PZL
t
t
PLZ
PZL
2.5 V
1.4 V
VOL +0.5 V
VOL
V
ROUT
V
TEST
0 V
1.4 V
V
RIN+
2 V
1.4 V
EN
0.8 V
2 V
1.4 V
EN
0.8 V
t
t
PHZ
PZH
t
t
PHZ
PZH
VOH
VOH –0.5 V
1.4 V
0 V
V
ROUT
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 500
kHz, duty cycle = 50 ±2%, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is
±20%.
Figure 4. 348 Enable/Disable Time Test Circuit and Waveforms
10
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
B
A
Y
500 Ω
1.2 V
Inputs
+
EN
V
TEST
V
O
_
10 pF
2.5 V
1 V
V
TEST
A
2 V
EN
1.4 V
0.8 V
t
t
PLZ
PZL
2.5 V
1.4 V
V
O
VOL +0.5 V
VOL
V
TEST
A
0 V
1.4 V
2 V
1.4 V
0.8 V
EN
t
t
PHZ
PZH
VOH
VOH –0.5 V
1.4 V
V
O
0 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 500
kHz, duty cycle = 50 ±2 %, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is
±20%.
Figure 5. 352 Enable/Disable Time Test Circuit and Waveforms
11
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
TYPICAL CHARACTERISTICS
LOW-TO-HIGH PROPAGATION DELAY
HIGH-TO-LOWPROPAGATION DELAY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
5
4.5
4
See NO TAG
See NO TAG
V
CC
= 3 V
4.5
V
CC
= 3 V
V
CC
= 3.3 V
V
CC
= 3.3 V
4
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3.5
3
3
-50
0
50
100
-50
0
50
100
T
A
- Free-Air Temperature - °C
T
A
- Free-Air Temperature - °C
Figure 6.
Figure 7.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
40
30
T
A
= 25°C,
T
V
= 25°C,
A
V
CC
= 3.3 V
= 3.3 V
CC
-10
-20
-30
-40
20
10
0
0
1
2
3
4
5
0
1
2
3
4
V
OH
- High-Level Output Voltage - V
V
OL
- Low-Level Output Voltage - V
Figure 8.
Figure 9.
12
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
TYPICAL CHARACTERISTICS (continued)
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
RMS SUPPLY CURRENT
vs
SWITCHING FREQUENCY
500
110
90
4 Receivers Switching,
50% Duty Cycle,
15
2
-1 prbs NRZ,
= 1.2 V,
= 5.5 pF,
V
CC
= 3.6 V
V
IC
C
T
= 5.5 pF,
= 25°C
L
C
L
450
400
350
300
A
40% Open Eye,
4 Receivers Switching,
V
CC
= 3.3 V,
V
CC
= 3.3 V
SN65LVDS348PW
70
V
= 0.4 V
ID
V
CC
= 3 V
50
30
V
ID
= 0.2 V
V
ID
= 0.1 V
250
200
10
0
50
100
150
200
250
300
-60
-40
-20
0
20
40
60
80
100
f - Switching Frequency - MHz
T
A
- Free-Air Temperature - °C
Figure 10.
Figure 11.
23
23
2
-1 prbs NRZ, T = 25°C, C = 5.5 pF,
2
-1 prbs NRZ, T = 25°C, C = 5.5 pF,
A L
A
L
4 Receivers Switching, V = 3.3 V
CC
4 Receivers Switching, V = 3.3 V
CC
Figure 12. SN65LVDS348 Eye
Pattern Running at 200 Mxfr/s
Figure 13. SN65LVDS352 Eye
Pattern Running at 200 Mxfr/s
13
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
APPLICATION INFORMATION
IMPEDANCE MATCHING AND REFLECTIONS
A termination mismatch can result in reflections that degrade the signal at the load. A low source impedance
causes the signal to alternate polarity at the load (oscillates) as shown in Figure 14. High source impedance
results in the signal accumulating monotonically to the final value (stair step) as shown in Figure 15. Both of
these modes result in a delay in valid signal and reduce the opening in the eye pattern. A 10% termination
mismatch results in a 5% reflection (r = ZL - ZO/ZL + ZO), even a 1:3 mismatch absorbs half of the incoming
signal. This shows that termination is important in the more critical cases, however, in a general sense, a rather
large termination mismatch is not as critical when the differential output signal is much greater than the receiver
sensitivity.
TIME DOMAIN RESPONSE
TIME DOMAIN RESPONSE
0.25
0.2
0.25
0.2
Z
Z
= 0 Ω
= 100 Ω
Z
Z
= 0 Ω
= 100 Ω
S
S
V at Load
O
O
Z = 132 Ω
T
Z = 90 Ω
T
V at Load
V
I
V
I
0.15
0.1
0.15
0.1
0.05
0
0.05
0
0
5
10
t - Time - ns
Figure 14. Low-Source Impedance
15
20
25
0
5
10
t - Time - ns
Figure 15. High-Source Impedance
15
20
25
For example a 200-mV drive signal into a 100-Ω lossless transmission media with a termination resistor of 90 Ω
to 132Ω results in ~227 mV to 189 mV into the receiver. This would typically be more than enough signal into a
receiver with a sensitivity of ±50 mV assuming no other disturbance or attenuation on the line. The other factors,
which reduce the signal margin, do affect this and therefore it is important to match the impedance as closely as
possible to allow more noise immunity at the receiver.
14
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
APPLICATION INFORMATION (continued)
ACTIVE FAILSAFE FEATURE
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves the
limitations seen in present solutions. A detailed theory of operation is presented in application note The Active
Fail-Safe in TI's LVDS Receivers, literature number SLLA082B.
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and it
detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 16. Receiver With Active Failsafe
ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know that established technology is capable of high-speed data
transmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDS
provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at
the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (VCC - 2 V).
Figure 17 shows the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received by TI's wide
common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a
resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value intended to minimize common-mode
reflections.
15
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
APPLICATION INFORMATION (continued)
V
V
CC
CC
R1 = 50 Ω
R2 = 50 Ω
I
I
CC
CC
V
B
5 Meters
of CAT-5
LV/PECL
LVDS
V
B
R3
R3
R1
R1
V
EE
R2
R3 = 240 Ω
Figure 17. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
DEVICE POWER AND GROUNDING
The SN65LVDS352 device provides separate power and ground pins for the analog input section and the two
digital output sections. All of the power pins and all of the ground pins of the device must be tied together at
some point in the system. Figure 18 shows one recommended scheme for power and ground to the device. This
point will be determined by the power and grounding distribution design, which can greatly affect system
performance.
Key points to remember when routing power and grounds in your system are:
•
•
•
•
The grounding system must provide a low impedance path back to the power source.
The signal return must be close to the signal path.
Ground noise occurs due to ground loops and common-mode noise pick-up.
Closely spaced power and ground planes reduce inductance and increase capacitance.
A good rule to remember when doing your power distribution and board layout is that the current always flows in
the lowest impedance path. At dc the lowest resistance is the lowest impedance, but at high frequencies the
lowest impedance is the lowest inductance path.
16
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SN65LVDS352, SN65LVDT352
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SLLS523E–FEBRUARY 2002–REVISED MAY 2004
APPLICATION INFORMATION (continued)
V
CC
V
CCD1
Bypass
†
Capacitor
DGND1
V
CCA
Bypass
†
Capacitor
AGND
V
CCD2
Bypass
†
Capacitor
DGND2
†
Bypass capacitors used for data sheet electrical testing were low ESR ceramic, surface mount, 0.01 µF ±10%. For a more accurate
determinationof these values refer to the application note, The Bypass Capacitor in High-Speed Environments, literature number SCBA007A.
Figure 18. Recommended Power and Ground Connection
17
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2009
PACKAGING INFORMATION
Orderable Device
SN65LVDS348D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
24
24
16
16
16
16
16
16
16
16
24
24
24
24
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDS348DG4
SN65LVDS348PW
SN65LVDS348PWG4
SN65LVDS348PWR
SN65LVDS348PWRG4
SN65LVDS352PW
SN65LVDS352PWG4
SN65LVDT348D
SOIC
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
PW
PW
PW
PW
PW
D
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT348DG4
SN65LVDT348DR
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT348DRG4
SN65LVDT348PW
SN65LVDT348PWG4
SN65LVDT348PWR
SN65LVDT348PWRG4
SN65LVDT352PW
SN65LVDT352PWG4
SN65LVDT352PWR
SN65LVDT352PWRG4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
PW
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2009
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS348PWR
SN65LVDT348DR
SN65LVDT348PWR
SN65LVDT352PWR
TSSOP
SOIC
PW
D
16
16
16
24
2000
2500
2000
2000
330.0
330.0
330.0
330.0
12.4
16.4
12.4
16.4
6.9
6.5
5.6
10.3
5.6
1.6
2.1
1.6
1.6
8.0
8.0
8.0
8.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
TSSOP
TSSOP
PW
PW
6.9
6.95
8.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LVDS348PWR
SN65LVDT348DR
SN65LVDT348PWR
SN65LVDT352PWR
TSSOP
SOIC
PW
D
16
16
16
24
2000
2500
2000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
29.0
33.0
29.0
33.0
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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