SN65LVDT41PWRG4 [TI]
MEMORY STICK⑩ INTERCONNECT EXTENDER CHIPSET WITH LVDS; MEMORY STICK互连延长芯片组具有LVDS
| 型号： | SN65LVDT41PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MEMORY STICK⑩ INTERCONNECT EXTENDER CHIPSET WITH LVDS |
| 文件： | 总16页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
MEMORY STICK™ INTERCONNECT EXTENDER CHIPSET WITH LVDS
SN65LVDT14—ONE DRIVER PLUS FOUR RECEIVERS
SN65LVDT41—FOUR DRIVERS PLUS ONE RECEIVER
FEATURES
APPLICATIONS
•
Memory Stick Interface Extensions With Long
Interconnects Between Host and Memory
Stick™
•
Integrated 110-Ω Nominal Receiver Line
Termination Resistor
•
•
•
•
•
•
Operates From a Single 3.3-V Supply
Greater Than 125 Mbps Data Rate
Flow-Through Pin-Out
•
Serial Peripheral Interface™ (SPI) Interface
Extension to Allow Long Interconnects
Between Master and Slave
LVTTL Compatible Logic I/Os
ESD Protection On Bus Pins Exceeds 16 kV
•
•
MultiMediaCard™ Interface in SPI Mode
General-Purpose Asymmetric Bidirectional
Communication
Meets or Exceeds the Requirements of
ANSI/TIA/EIA-644A Standard for LVDS
•
20-Pin PW Thin Shrink Small-Outline Package
With 26-Mil Terminal Pitch
DESCRIPTION
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. It is
designed to be used at the Memory Stick end of an LVDS based Memory Stick interface extension.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package.
It is designed to be used at the host end of an LVDS based Memory Stick interface extension.
SN65LVDT41 LOGIC DIAGRAM
SN65LVDT14 LOGIC DIAGRAM
(POSITIVE LOGIC)
(POSITIVE LOGIC)
1Y
1A
1D
2D
3D
4D
1R
2R
3R
4R
1Z
2Y
1B
2A
2Z
3Y
2B
3A
3Z
4Y
3B
4A
4Z
5A
4B
5Y
5R
5D
5B
5Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Serial Peripheral Interface is a trademark of Motorola.
MultiMediaCard is a trademark of MultiMediaCard Association.
Memory Stick is a trademark of Sony.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TYPICAL MEMORY STICK INTERFACE EXTENSION
SN65LVDT41
SN65LVDT14
1Y
1A
1D
2D
3D
4D
SCLK
1R
1Z
2Y
1B
2A
SCLK
SCLK
Memory
Stick
Host
Memory
Stick
BS
SDIO
DIR
BS
DIR
SD1
2R
3R
4R
BS
2Z
3Y
2B
3A
SDIO
Controller
3Z
4Y
3B
4A
CBT
4Z
5A
4B
5Y
CBT
SD2
5R
5D
5B
5Z
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN65LVDT14,
SN65LVDT41
UNIT
Supply voltage range(2)
Input voltage range
VCC
-0.5 to 4
-0.5 to 6
-0.5 to 4
±16
V
V
D or R
A, B, Y, or Z
V
Human body model(3), A, B, Y, Z, and GND
Human body model(3), all pins
Charged device model(4), all pins
KV
KV
V
Electrostatic discharge
±8
±500
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature range
-65 to 150
260
°C
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
PACKAGE DISSIPATION RATINGS
TA <25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
PW
774 mW
6.2 mW/°C
402 mW
2
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SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX
UNIT
VCC
VIH
VIL
Supply voltage
3.3
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
Magnitude of differential input voltage
2
0.8
0.6
|VID
VIC
TA
|
0.1
Ť Ť
V
ŤVIDŤ
2
V
ID
Common-mode input voltage, See Figure 1
2.4 *
2
VCC - 0.8
85
V
Operating free-air temperature
-40
°C
2.5
Max at V > 3.15 V
CC
Max at V = 3 V
CC
2
1.5
1
0.5
0
Minimum
0.4
0
0.1
0.2
0.3
0.5
0.6
|V |− Differential Input Voltage − V
ID
Figure 1. VIC vs VID and VCC
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VITH+
VITH-
VOH
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
100
mV
See Figure 2 and Table 1
-100
2.4
IOH = -8 mA
IOL = 8 mA
V
VOL
Low-level output voltage
0.4
±40
±40
V
VI = 0 V and VI = 2.4 V,
other input open
II
Input current (A or B inputs)
µA
II(OFF)
Ci
Power-off input current (A or B inputs)
Input capacitance, A or B input to GND
Termination impedance
VCC = 0 V, VI = 2.4 V
VI = A sin 2πft + CV
VID = 0.4 sin2.5E09 t V
µA
pF
Ω
5
Zt
88
132
(1) All typical values are at 25°C and with a 3.3-V supply.
3
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SN65LVDT14
SN65LVDT41
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SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
DRIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
|VOD
|
Differential output voltage magnitude
247
340
454
RL = 100 Ω,
See Figure 3 and
Figure 5
mV
50
Change in differential output voltage magnitude between
logic states
∆|VOD
|
-50
VOC(SS)
Steady-state common-mode output voltage
1.125
-50
1.375
50
V
Change in steady-state common-mode output voltage
between logic states
∆VOC(SS)
See Figure 6
mV
VOC(PP)
IIH
Peak-to-peak common-mode output voltage
High-level input current
50
150
20
mV
µA
µA
VIH = 2 V
IIL
Low-level input current
VIL = 0.8 V
10
VOY or VOZ = 0 V
VOD = 0 V
±24
±12
±1
IOS
Short-circuit output current
Power-off output current
mA
µA
IO(OFF)
VCC = 1.5 V, VO = 2.4 V
(1) All typical values are at 25°C and with a 3.3-V supply.
DEVICE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
SN65LVDT14
SN65LVDT41
25
Driver RL = 100 Ω, Driver VI = 0.8 V or 2 V,
Receiver VI = ±0.4 V
ICC
Supply current
mA
35
(1) All typical values are at 25°C and with a 3.3-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
1
1
2.6
2.6
3.8
3.8
1.2
1.2
600
400
1
ns
ns
ns
ns
ps
ps
ns
0.15
0.15
tf
Output signal fall time
CL = 10 pF, See Figure 4
tsk(p)
tsk(o)
tsk(pp)
Pulse skew (|tPHL - tPLH|)
Output skew(1)
Part-to-part skew(2)
150
100
(1) tsk(o) is the magnitude of the time difference between the tpLH or tpHL of all the receivers of a single device with all of their inputs
connected together.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
4
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SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
DRIVER SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM
MAX UNIT
tPLH
tPHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL - tPLH|)
0.9
0.9
1.7
1.6
2.9
2.9
ns
1
RL = 100 Ω, CL = 10 pF,
See Figure 7
0.26
0.26
tf
1
tsk(p)
tsk(o)
tsk(pp)
150
80
500
150
1.5
ps
ps
ns
RL = 100 Ω, CL = 10 pF,
See Figure 7
Output skew(1)
Part-to-part skew(2)
(1) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
A
V
) V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 2. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING
COMMON-MODE
INPUT VOLTAGE
RESULTING DIFFERENTIAL
APPLIED VOLTAGES
INPUT VOLTAGE
VIA
VIB
VID
VIC
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0.0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0.0 V
1.15 V
1.25 V
2.3 V
2.4 V
0.0 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0.0 V
0.6 V
100 mV
-100 mV
100 mV
-100 mV
100 mV
-100 mV
600 mV
-600 mV
600 mV
-600 mV
600 mV
-600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
5
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SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
I
OY
Y
Z
I
I
D
V
OD
V
) V
OY
OZ
I
OZ
V
OY
2
V
I
V
OC
V
OZ
Figure 3. Driver Voltage and Current Definitions
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
–0.4 V
t
t
PHL
PLH
V
V
O
OH
80%
20%
V
CC
V
OL
/2
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 m of the
D.U.T.
Figure 4. Receiver Timing Test Circuit and Waveforms
3.75 kΩ
Y
+
0 V ≤ V
≤ 2.4 V
V
OD
100 Ω
test
Input
_
Z
3.75 kΩ
Figure 5. Driver VDO Test Circuit
6
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SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
49.9 Ω, ±1% (2 Places)
3 V
0 V
Y
Z
D
Input
V
IA
2 pF
V
OC
V
OC(PP)
V
OC(SS)
V
OC
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 6. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
100 Ω
±1%
V
OD
Input
Z
C
L
(2 Places)
2 V
Input
1.4 V
0.8 V
t
PHL
t
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 7. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
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SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
SN65LVDT41 (Marked as LVDT41)
SN65LVDT14 (Marked as LVDT14)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1D
GND
2D
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
5A
5B
1A
1B
2A
2B
3A
3B
4A
4B
5Y
5Z
1R
GND
2R
V
CC
3R
GND
4R
V
CC
5D
GND
V
CC
3D
GND
4D
V
CC
5R
GND
Function Tables
RECEIVER
INPUTS
DRIVER
OUTPUTS
OUTPUT
INPUT
D
V
= V – V
B
R
H
Y
Z
ID
A
V
≥ 100 mV
H
L
H
L
L
L
H
H
ID
–100 mV < V < 100 mV
?
L
H
ID
Open
V
≤ –100 mV
ID
Open
H = high level, L = low level , ? = indeterminate
H = high level, L = low level
RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
110 Ω
A
B
300 kΩ
300 kΩ
5 Ω
R Output
A Input
B Input
7 V
7 V
7 V
8
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SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
50 Ω
D Input
5 Ω
Y or Z
Output
10 kΩ
7 V
300 kΩ
7 V
TYPICAL CHARACTERISTICS
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4
3.5
3
5
4.5
4
T
V
= 25°C,
T
V
= 25°C,
A
A
= 3.3 V
= 3.3 V
CC
CC
3.5
3
2.5
2.5
2
1.5
1
2
1.5
1
0.5
0
0.5
0
−70 −60
0
10
20
30
40
50
60
70
80
−50
−40
−30
−20
−10
0
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OH
OL
Figure 8.
Figure 9.
9
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SN65LVDT14
SN65LVDT41
www.ti.com
SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
RECEIVER (continued)
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3
2.9
2.8
2.7
2.6
2.5
2.4
2.8
2.7
2.6
2.5
2.4
2.3
2.2
V
= 3 V
CC
V
CC
= 3 V
V
CC
= 3.3 V
V
CC
= 3.3 V
V
= 3.6 V
CC
V
= 3.6 V
CC
2.3
2.2
2.1
2
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 10.
Figure 11.
DRIVER
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.1
2
2.2
2.1
V
CC
= 3 V
V
CC
= 3 V
2
1.9
1.8
1.7
1.6
1.5
V
CC
= 3.3 V
1.9
1.8
1.7
V
CC
= 3.6 V
V
CC
= 3.6 V
1.6
1.5
V
= 3.3 V
0
CC
−50
−25
0
25
50
75
100
−50
−25
25
50
75
100
Ta − Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 12.
Figure 13.
10
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SN65LVDT14
SN65LVDT41
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SLLS530B–APRIL 2002–REVISED FEBRUARY 2006
APPLICATION INFORMATION
EXTENDING THE MEMORY STICK INTERFACE USING LVDS SIGNALING OVER DIFFERENTIAL
TRANSMISSION CABLES
SN65LVDT41
SN65LVDT14
1Y
1A
1D
2D
3D
4D
SCLK
1R
1Z
2Y
1B
2A
SCLK
SCLK
Memory
Stick
Host
Memory
Stick
BS
BS
DIR
SD1
BS
2R
3R
4R
2Z
3Y
2B
3A
SDIO
SDIO
Controller
DIR
3Z
4Y
3B
4A
CBT
4B
5Y
4Z
5A
SD2
CBT
5R
5D
5B
5Z
Figure 14. System Level Block Diagram
The Memory Stick signaling interface operates in a
master-slave architecture, with three active signal
lines. The host (master) supplies a clock (SCLK) and
bus-state (BS) signal to control the operation of the
system. The SCLK and BS signals are unidirectional
(simplex) from the host to the Memory Stick. The
LVDS, as specified by the TIA/EIA-644-A standard,
provides several benefits when compared to
alternative long-distance signaling technologies: low
radiated emissions, high noise immunity, low power
consumption, inexpensive interconnect cables.
This device pair provides the necessary LVDS drivers
and receivers specifically targeted at implementing a
Memory Stick interconnect extension. It utilizes
simplex links for the SCLK and BS signals, and two
simplex links for the SDIO data. The half-duplex
SDIO data is split into two simplex streams under
control of the host processor by means of the
direction (DIR) signal. The DIR signal is also carried
from the host to the Memory Stick on a simplex LVDS
link.
serial data input-output (SDIO) signal is
a
bidirectional (half-duplex) signal used to communicate
both control and data information between the host
and the Memory Stick. The direction of data control is
managed by the host through a combination of BS
line states and control information delivered to the
Memory Stick.
The basic Memory Stick interface is capable of
operating only over short distances due to the
single-ended nature of the digital I/O signals. Such a
configuration is entirely suitable for compact and
portable devices where there is little if any separation
between the host and the Memory Stick. In
applications where a greater distance is needed
between the host controller and the Memory Stick, it
is necessary to utilize a different signaling method
such as low voltage differential signaling, or LVDS.
The switching of the SDIO signal flow direction in the
single-ended interfaces is managed by electronic
switch devices, identified by the CBT symbol in
Figure 14.
A suggested CBT device for this
application is the SN74CBTLV1G125 from Texas
Instruments Incorporated. These devices are
available in space saving SOT-23 or SC-70
packages.
11
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2006
PACKAGING INFORMATION
Orderable Device
SN65LVDT14PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
20
20
20
20
20
20
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT14PWG4
SN65LVDT14PWR
SN65LVDT14PWRG4
SN65LVDT41PW
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LVDT41PWG4
SN65LVDT41PWR
SN65LVDT41PWRG4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
(mm)
16
SN65LVDT14PWR
SN65LVDT14PWR
SN65LVDT41PWR
SN65LVDT41PWR
PW
PW
PW
PW
20
20
20
20
SITE 41
SITE 60
SITE 41
SITE 60
6.95
6.95
6.95
6.95
7.1
7.1
7.1
7.1
1.6
1.6
1.6
1.6
8
8
8
8
16
16
16
16
Q1
Q1
Q1
Q1
16
16
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65LVDT14PWR
SN65LVDT14PWR
SN65LVDT41PWR
SN65LVDT41PWR
PW
PW
PW
PW
20
20
20
20
SITE 41
SITE 60
SITE 41
SITE 60
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
33.0
33.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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