SN65LVDT9637A [TI]
HIGH-SPEED DIFFERENTIAL RECEIVERS; 高速差分接收器
| 型号： | SN65LVDT9637A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED DIFFERENTIAL RECEIVERS |
| 文件： | 总14页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
SN65LVDS32A
SN65LVDT32A
Meets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard for Signaling
Rates Up to 400 Mbps
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
†
Operates With a Single 3.3 V Supply
G
G
1B
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
–2 V to 4.4 V Common-Mode Input Voltage
Range
4B
4A
4Y
G
SN65LVDT32A
ONLY (4 Places)
1A
1Y
Differential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
1Y
G
1B
2Y
2A
11 3Y
10 3A
2A
2B
Integrated 110Ω Line Termination Resistors
Offered With the LVDT Series
2B
2Y
3Y
4Y
9
GND
3B
Propagation Delay Times 4 ns (typ)
3A
3B
4A
4B
Open-Circuit and Terminated Fail Safe
Assures a High-Level Output With No Input
Bus-Pin ESD Protection Exceeds 15 kV
HBM
Outputs High-Impedance With V
< 1.5 V
CC
Power Dissipation <400 mW With Four
Receivers Switching at 200 MHz
SN65LVDS3486A
SN65LVDT3486A
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
Available in Small-Outline Package With
1,27 mm Terminal Pitch
SN65LVDT3486A
Pin-Compatible With the AM26LS32,
MC3486, or uA9637
1B
1A
V
CC
4B
1
2
3
4
5
6
7
8
16
15
14
13
12
ONLY (4 Places)
1A
1B
1Y
1Y
4A
1,2EN
description
1,2EN
2Y
4Y
2A
2B
3,4EN
2Y
3Y
4Y
This family of differential line receivers offer
improved performance and features that imple-
ment the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS is defined in
the TIA/EIA-644 standard. This improved perfor-
mance represents the second generation of
receiver products for this standard providing a
better overall solution for the cabled environment.
The next generation family of products is an
extension to TI’s overall product portfolio and is
not necessarily a replacement for older LVDS
receivers.
2A
11 3Y
10 3A
2B
3A
3B
GND
9
3B
3,4EN
4A
4B
SN65LVDS9637A
SN65LVDT9637A
D PACKAGE
(TOP VIEW)
Logic Diagram
(positive logic)
Improved features include an input common-
mode voltage range 2 V wider than the minimum
required by the standard. This will allow longer
cable lengths by tripling the allowable ground
noise tolerance to 3 V between a driver and
receiver.
V
1A
1
2
3
4
8
7
6
5
CC
1A
1Y
2Y
1B
1Y
2Y
2A
2B
1B
SN65LVDT9637A
GND
ONLY
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
description (continued)
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage
hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more
than ±50 mV over the full input common-mode voltage range. See Application Information for more details on
this feature.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates
this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available
for multidrop or other termination circuits.
The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 500 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A, SN65LVDT3486A, SN65LVDS9637A, and
SN65LVDT9637A are characterized for operation from -40°C to 85°C.
Function Tables
SN65LVDS32A and SN65LVDT32A
DIFFERENTIAL INPUT
A-B
ENABLES
OUTPUT
Y
G
G
H
X
X
L
H
H
V
ID
≥ -70 mV
H
X
X
L
?
?
-100 mV < V ≤ -70 mV
ID
H
X
X
L
L
L
V
ID
≤ -100 mV
X
L
H
Z
H
X
X
L
H
H
Open
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SN65LVDS3486A and SN65LVDT3486A
DIFFERENTIAL INPUT
A-B
ENABLES
OUTPUT
EN
H
Y
H
?
V
≥ -70 mV
ID
-100 mV < V ≤ -70 mV
H
ID
V
ID
≤ -100 mV
X
H
L
L
Z
H
Open
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
Function Tables (Continued)
SN65LVDS9637A and SN65LVDT9637A
DIFFERENTIAL INPUT
A-B
OUTPUT
Y
H
?
V
≥ -70 mV
ID
-100 mV < V ≤ -70 mV
ID
V
ID
≤ -100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
equivalent input and output schematic diagrams
V
CC
Attenuation
Network
V
CC
B Input
A Input
18 V
7 V
7 V
18 V
LVDT Only 110 Ω
V
CC
V
CC
300 kΩ
(G Only)
50 Ω
Enable
Inputs
37 Ω
Y Output
7 V
7 V
300 kΩ
(EN and G Only)
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
CC
Voltage range: Enables or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 3 V
CC
A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to 6 V
Electrostatic discharge: A, B, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 15 kV, B: 600 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 7 kV, B: 500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage Temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
‡
T
≤ 25°C
OPERATING FACTOR
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
D8
725 mW
5.8 mW/°C
7.6 mW/°C
377 mW
D16
950 mW
494 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
High-level input voltage, V
IH
Enables
Enables
V
Low-level input voltage, V
IL
Magnitude of differential input voltage, V
0.8
3
V
0.1
–2
V
ID
Common-mode input voltage, V
IC
4.4
85
V
Operating free-air temperature, T
–40
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
Differential input fail-safe voltage threshold
Differential input voltage hysteresis,
50
ITH1
ITH2
ITH3
V
=-2 V or 4.4 V, See Figure 1
mV
IB
–50
–70
See Figure 2 and Table 1
–100
mV
mV
V
50
16
ID(HYS)
V
ITH1
- V
ITH2
V
V
High-level output voltage
Low-level output voltage
I
I
= –8 mA
= 8 mA
2.4
V
V
OH
OH
0.4
23
OL
OL
G or EN at V
Steady-state
,
No load,
CC
‘32A or ‘3486A
‘9637A
I
Supply current
mA
CC
G or EN at GND
No load,
1.1
8
5
12
Steady-state
V = 0 V,
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
Other input open
±20
±20
±40
±40
±40
±40
±80
±80
I
V =2.4 V,
I
SN65LVDS
SN65LVDT
µA
V =-2 V,
I
V = 4.4 V,
I
I
Input current (A or B inputs)
I
V = 0 V,
I
V =2.4 V,
I
µA
µA
V =-2 V,
I
V = 4.4 V,
I
V
= 100 mV,
V
= –2 V or 4.4 V,
ID
See Figure 1
IC
SN65LVDS
SN65LVDT
±2
Differential input current
(I - I
I
I
ID
)
V
V
= 0.4 V,
V
V
= –2 V or 4.4 V
= –2 V or 4.4 V
3.1
4.5
mA
mA
IA IB
ID
IC
= –0.4 V,
–3.1
–4.5
ID
IC
V
or V =0 or 2.4 V,
B
= 0 V
A
±30
±50
V
CC
or V =–2 V or 4.4 V,
Power-off input current (A or B inputs)
µA
I(OFF)
V
A
B
= 0 V
V
V
V
CC
I
I
I
High-level input current (enables)
Low-level input current (enables)
High-impedance output current
Input capacitance, A or B input to GND
= 2 V
10
10
µA
µA
µA
pF
IH
IH
IL
= 0.8 V
IL
±10
OZ
C
V = 0.4 sin (4E6πt) + 0.5 V
I
5
IN
†
All typical values are at 25°C and with a 3.3 V supply.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Delay time, fail-safe deactivate time
TEST CONDITIONS
MIN TYP
MAX
6
UNIT
ns
ns
ns
µs
ps
ps
ns
ps
ps
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
2.5
2.5
4
4
PLH
PHL
d1
6
6.1
1
Delay time, fail-safe activate time
0.3
d2
C
= 10 pF,
L
Pulse skew (|t
– t
|)
200
150
sk(p)
sk(o)
sk(pp)
r
PHL1 PLH1
See Figure 3
§
Output skew
Part-to-part skew
‡
1
Output signal rise time
Output signal fall time
600
600
5.5
4.4
3.8
7
f
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance -to-high-level output
Propagation delay time, high-impedance-to-low-level output
9
9
9
9
PHZ
PLZ
PZH
PZL
See Figure 4
†
‡
All typical values are at 25°C and with a 3.3 V supply.
t
is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
sk(pp)
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
§
t
is the magnitude of the time difference between the t
PLH
or t
of all receivers of a single device with all of their inputs driven together.
PHL
sk(o)
PARAMETER MEASUREMENT INFORMATION
I
IA
A
B
V
O
Y
V
ID
V
IA
I
IB
(V + V )/2
V
O
IA
IB
V
IC
V
IB
Figure 1. Voltage and Current Definitions
2 µs
V
ID
1 µs
0.2 V
V
IA
V
IT–
V
IT+
V
ID
C
< 50 pF
L
V
O
V
IB
–0.2 V
V
O
Figure 2. V
Input Voltage Threshold Test Circuit and Definitions
ITH3
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum Fail-Safe
Input Threshold Test Voltages
†
APPLIED VOLTAGES
RESULTANT INPUTS
V
IA
(mV) (mV)
V
V
(mV)
V (mV)
IC
Output
IB
ID
–100
–2050
–2035
4350
–1950
–1965
4450
–2000
–2000
4400
L
H
L
–70
–100
–70
4365
4435
4400
H
†
These voltages are applied for a minimum of 1 µs.
V
ID
V
IA
V
O
C
= 10 pF
V
IB
L
V
V
1.4 V
IA
1 V
IB
0.4 V
>1 µs
V
ID
0 V
–0.2 V
–0.4 V
t
t
t
t
D2
PHL
PLH
D1
V
OH
1.4 V
80%
20%
80%
20%
V
O
V
OL
t
t
r
f
NOTE A: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, Pulse Repetition Rate (PRR) = 50 Mpps,
r
f
Pulsewidth = 10 ± 0.2 ns . C includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
L
Figure 3. Timing Test Circuit and Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
B
1.2 V
500 Ω
A
10 pF
±
V
O
G
V
TEST
Inputs
G
1,2,EN, or 3,4, EN
NOTE B: All input pulses are supplied by a generator having the following characteristics: t or t ≤ 1 ns, pulse
r
f
repetition rate (PRR) = 50 Mpps, Pulsewidth = 10 ± 0.2 ns . C includes instrumentation and fixture
L
capacitance within 0,06 mm of the D.U.T.
2.5 V
V
TEST
A
1 V
2 V
1.4 V
0.8 V
G, 1,2EN,or 3,4EN
G
2 V
1.4 V
0.8 V
t
t
PLZ
PLZ
t
t
PZL
PZL
Y
2.5 V
1.4 V
OL
OL
V
V
+0.5 V
V
TEST
0
1.4 V
A
2 V
G, 1,2EN,or 3,4EN
G
1.4 V
0.8 V
2 V
1.4 V
0.8 V
t
t
PHZ
PHZ
t
t
PZH
PZH
Y
V
V
OH
OH
–0.5 V
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
4
3
4
3
V
T
A
= 3.3 V
= 25°C
V
T
A
= 3.3 V
= 25°C
CC
CC
2
1
2
1
0
0
–100
0
20
40
60
80
100
–80
–60
–40
–20
0
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 5
Figure 6
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
5
4.5
4
4.5
4
V
= 3 V
V
= 3 V
CC
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.6 V
V
CC
= 3.6 V
3.5
3
3.5
3
–50
0
50
100
–50
0
50
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 7
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
140
120
V
= 3.3 V
100
80
CC
V
= 3.6 V
CC
60
40
V
CC
= 3 V
20
0
0
100
150
200
f – Switching Frequency – MHz
Figure 9
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
APPLICATION INFORMATION
0.01 µF
≈3.6 V
16
V
CC
5 V
1
2
1B
1A
0.1 µF
(see Note A)
1N645
(2 places)
100 Ω
15
14
4B
4A
3
4
100 Ω
(see Note B)
1Y
G
V
CC
13
12
11
5
6
4Y
G
2Y
2A
See Note C
3Y
100 Ω
7
8
10
9
3A
3B
2B
100 Ω
GND
NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between V
and the ground plane. The
CC
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to V or GND as appropriate.
CC
Figure 10. Operation with 5-V Supply
related information
IBISmodelingisavailableforthisdevice. PleasecontactthelocalTIsalesofficeortheTIWebsiteatwww.ti.com
for more information.
For more application guidelines, please see the following documents:
Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
Reducing EMI With LVDS (SLLA030)
Slew Rate Control of LVDS Circuits (SLLA034)
Using an LVDS Receiver With RS-422 Data (SLLA031)
Evaluating the LVDS EVM (SLLA033)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
APPLICATION INFORMATION
abstract terminated failsafe
Differential data line receivers commonly have failsafe circuits to prevent the receiver from switching on input
noise. This can occur when the bus driver is turned off or the interconnecting cable is damaged or left floating.
This is generally solved with an external resistor network that applies a steady state bias voltage to the undriven
input pins. In addition to the cost of external components, this has the effect of lowering the input magnitude
therebyreducingthedifferentialnoisemargin. CurrentIntegratedsolutionswillnotworkinwired-ORorcommon
mode termininated bus applications. The terminated failsafe circuit works over its entire extended common
mode range and will ensure a known state regardless of the common mode signal present.
Output
Buffer
Main Receiver
+
_
A
B
R
Failsafe
Timer
Reset
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 11. Receiver with Terminated Failsafe
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A
SN65LVDT3486A, SN65LVDS9637A, SN65LVDT9637A
HIGH-SPEED DIFFERENTIAL RECEIVERS
SLLS368C – JULY 1999 – REVISED JANUARY 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明