SN65MLVD082DGGRG4 [TI]
8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS; 8通道半双工M- LVDS线路收发器
| 型号： | SN65MLVD082DGGRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS |
| 文件： | 总28页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65MLVD080
SN65MLVD082
www.ti.com
SLLS581B–SEPTEMBER 2003–REVISED SEPTEMBER 2005
8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
The M-LVDS standard defines two types of receivers,
designated as Type-1 and Type-2. Type-1 receivers
(SN65MLVD080) have thresholds centered about
zero with 25 mV of hysteresis to prevent output
oscillations with loss of input; Type-2 receivers
(SN65MLVD082) implement a failsafe by using an
offset threshold. In addition, the driver rise and fall
times are between 1 and 2.0 ns, complying with the
M-LVDS standard to provide operation at 250 Mbps
while also accommodating stubs on the bus. Receiver
outputs are slew rate controlled to reduce EMI and
crosstalk effects associated with large current surges.
The M-LVDS standard allows for 32 nodes on the bus
providing a high-speed replacement for RS-485
where lower common-mode can be tolerated or when
higher signaling rates are needed.
FEATURES
•
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers and Receivers for Signaling Rates
Up to 250 Mbps; Clock Frequencies Up to
125 MHz
(1)
•
•
•
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Data Interchange
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
–1 V to 3.4 V Common-Mode Voltage Range
Allows Data Transfer With 2 V of Ground
Noise
•
Bus Pins High Impedance When Driver
Disabled or VCC ≤ 1.5 V
The driver logic inputs and the receiver logic outputs
are on separate pins rather than tied together as in
some transceiver designs. The drivers have separate
enables (DE) and the receivers are enabled globally
through (RE). This arrangement of separate logic
inputs, logic outputs, and enable pins allows for a
listen-while-talking operation. The devices are
characterized for operation from –40°C to 85°C.
•
•
•
•
Independent Enables for each Driver
Bus Pin ESD Protection Exceeds 8 kV
Packaged in 64-Pin TSSOP (DGG)
M-LVDS Bus Power Up/Down Glitch Free
APPLICATIONS
•
Parallel Multipoint Data and Clock
Transmission Via Backplanes and Cables
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
Cellular Base Stations
Central-Office Switches
Network Switches and Routers
LOGIC DIAGRAM (POSITIVE LOGIC)
•
SN65MLVD080, SN65MLVD082
Channel 1
1DE
•
•
•
1A
1D
1B
1R
RE
DESCRIPTION
The SN65MLVD080 and SN65MLVD082 provide
eight half-duplex transceivers for transmitting and
receiving Multipoint-Low-Voltage Differential Signals
in full compliance with the TIA/EIA-899 (M-LVDS)
standard, which are optimized to operate at signaling
rates up to 250 Mbps. The driver outputs have been
designed to support multipoint buses presenting
loads as low as 30-Ω and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.
7
2DE - 8DE
2A - 8A
2B - 8B
7
2D - 8D
2R - 8R
Channels 2 - 8
7
(1) The signaling rate of a line, is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65MLVD080
SN65MLVD082
www.ti.com
SLLS581B–SEPTEMBER 2003–REVISED SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
SN65MLVD080DGG
SM65MLVD080DGGR
SN65MLVD082DGG
SM65MLVD082DGGR
RECEIVER TYPE
Type 1
PACKAGE MARKING
MLVD080
PACKAGE/CARRIER
64-Pin TSSOP/Tube
Type 1
MLVD080
64-Pin TSSOP/Tape and Reeled
64-Pin TSSOP/Tube
Type 2
MLVD082
Type 2
MLVD082
64-Pin TSSOP/Tape and Reeled
PACKAGE DISSIPATION RATINGS
T
A ≤ 25°C
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
PCB JEDEC STANDARD
POWER RATING
DGG
DGG
Low-K(2)
High-K(3)
1204.7 mW
10.5 mW/°C
576 mW
880 mw
1839.4 mW
16.0 mW/°C
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
41.08
6.78
MAX UNIT
θJB Junction-to-board thermal resistance
θJC Junction-to-case thermal resistance
°C/W
°C/W
VCC = 3.3 V, DE = VCC, RE = GND, CL = 15 pF,
RL = 50 Ω, 250 Mbps random data on each input
477
Device power dissipation
mW
VCC = 3.6 V, DE = VCC, RE = GND, CL = 15 pF,
RL = 50 Ω, 250 Mbps data on one input and 125 MHz
clock on the others
854(1)
(1) When all channels are running at a 125-MHz clock frequency, a 250 lfm is required for a low-K board, and 150 lfm is required for a
high-K board. In such applications, a TI 1:8 or dual 1:4 M-LVDS buffer is highly recommended, SN65MLVD128 or SN65MLVD129, to
fan out clock signals in multiple paths.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN65MLVD080, 082
Supply voltage range(2), VCC
–0.5 V to 4 V
–0.5 V to 4 V
–1.8 V to 4 V
–0.3 V to 4 V
–1.8 V to 4 V
±8 kV
D, DE, RE
Input voltage range
Output voltage range
A, B
R
A, or B
A, B
Human Body Model(3)
Electrostatic discharge
All pins
All pins
±2 kV
Charged-Device Model(4)
±1500 V
Continuous power dissipation
Storage temperature range
See Dissipation Rating Table
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
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SN65MLVD082
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SLLS581B–SEPTEMBER 2003–REVISED SEPTEMBER 2005
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VCC Supply voltage
3
2
3.3
3.6
VCC
0.8
V
V
V
V
V
VIH
VIL
High-level input voltage
Low-level input voltage
GND
–1.4
0.05
–40
Voltage at any bus terminal VA or VB
Magnitude of differential input voltage
Operating free-air temperature
Maximum junction temperature
3.8
|VID
|
VCC
TA
85 °C
140 °C
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
Driver only
Both disabled RE at VCC, DE at 0 V, RL = No Load, All others open
Both enabled RE at 0 V, DE at VCC, RL = 50 Ω, CL = 15 pF, All others open
Receiver only RE at 0 V, DE at 0 V, CL = 15 pF, All others open
TEST CONDITIONS
MIN TYP(1) MAX UNIT
RE and DE at VCC, RL = 50 Ω, All others open
110 140
5
8
ICC Supply current
mA
140 180
38 50
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(1) TYP(2)
MAX UNIT
|VAB
|
Differential output voltage magnitude (A, B)
480
–50
0.8
650
mV
mV
V
See Figure 2
Change in differential output voltage magnitude
between logic states (A, B)
∆|VAB
|
50
VOS(SS)
Steady-state common-mode output voltage (A, B)
1.2
50
Change in steady-state common-mode output voltage
between logic states (A, B)
∆VOS(SS)
See Figure 3
–50
mV
VOS(PP)
VA(OC)
VB(OC)
Peak-to-peak common-mode output voltage (A, B)
Maximum steady-state open-circuit output voltage (A, B)
Maximum steady-state open-circuit output voltage (A, B)
150
2.4
2.4
mV
V
0
0
See Figure 7
See Figure 5
V
1.2
VSS
VP(H)
VP(L)
Voltage overshoot, low-to-high level output (A, B)
Voltage overshoot, high-to-low level output (A, B)
V
V
–0.2
VSS
IIH
IIL
High-level input current (D, DE)
VIH = 2 V to VCC
10
10
24
µA
µA
mA
pF
Low-level input current (D, DE)
VIL = GND to 0.8 V
See Figure 4
|IOS
Ci
|
Differential short-circuit output current magnitude (A, B)
Input capacitance (D, DE)
(3)
VI = 0.4 sin(30E6πt) + 0.5 V
5
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) All typical values are at 25°C and with a 3.3-V supply voltage.
(3) HP4194A impedance analyzer (or equivalent)
3
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SN65MLVD082
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SLLS581B–SEPTEMBER 2003–REVISED SEPTEMBER 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
Type 1
50
mV
150
VIT+ Positive-going differential input voltage threshold (A, B)
VIT– Negative-going differential input voltage threshold (A, B)
Type 2
Type 1
Type 2
Type 1
Type 2
–50
50
25
0
See Figure 9, Table 1 and
Table 2
mV
VHYS Differential input voltage hysteresis, (VIT+– VIT–) (A, B)
VOH High-level output voltage (R)
mV
V
IOH = –8 mA
2.4
VOL
IIH
Low-level output voltage (R)
High-level input current (RE)
Low-level input current (RE)
High-impedance output current (R)
IOL = 8 mA
0.4
15
V
VIH = 2 V to VCC
VIL = GND to 0.8 V
VO = 0 V or VCC
–10
–10
–10
µA
µA
µA
IIL
IOZ
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
VA = 3.8 V,
VB = 1.2 V
0
–20
–32
0
32
20
0
Receiver or transceiver with driver
disabled input current
IA
VA = 0 V or 2.4 V, VB = 1.2 V
µA
VA = –1.4 V,
VB = 3.8 V,
VB = 1.2 V
VA = 1.2 V
32
20
0
Receiver or transceiver with driver
disabled input current
IB
VB = 0 V or 2.4 V, VA = 1.2 V
–20
–32
µA
µA
µA
VB = –1.4 V,
VA = VB
VA = 3.8 V,
VA = 1.2 V
Receiver or transceiver with driver
disabled differential input current
(IA– IB)
IAB
,
1.4 ≤ VA ≤ 3.8 V
–4
4
VB = 1.2 V,
0 V ≤ VCC≤ 1.5 V
0 V ≤ VCC≤ 1.5 V
0 V ≤ VCC≤ 1.5 V
0 V ≤ VCC≤ 1.5 V
0 V ≤ VCC≤ 1.5 V
0 V ≤ VCC≤ 1.5 V
0
–20
–32
0
32
20
0
Receiver or transceiver power-off input
current
IA(OFF)
VA = 0 V or 2.4 V, VB = 1.2 V,
VA = –1.4 V,
VB = 3.8 V,
VB= 1.2 V,
VA = 1.2 V,
32
20
0
Receiver or transceiver power-off input
current
IB(OFF)
VB = 0 V or 2.4 V, VA = 1.2 V,
VB = –1.4 V, VA = 1.2 V,
–20
–32
µA
µA
Receiver input or transceiver power-off
differential input current
IAB(OF
VA = VB, 0 V ≤ VCC ≤ 1.5 V, –1.4 ≤ VA ≤ 3.8 V
–4
4
F)
(IA(off)– IB(off)
)
Transceiver with driver disabled
input capacitance
CA
VA = 0.4 sin (30E6πt) + 0.5 V(2)
VB = 0.4 sin (30E6πt) + 0.5 V(2)
VAB = 0.4 sin (30E6πt)V(2)
,
VB = 1.2 V
VA = 1.2 V
5
5
pF
pF
pF
Transceiver with driver disabled
input capacitance
CB
,
Transceiver with driver disabled
differential input capacitance
CAB
CA/B
3
Transceiver with driver disabled
input capacitance balance, (CA/CB)
0.99
1.01
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) HP4194A impedance analyzer (or equivalent)
4
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SN65MLVD082
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SLLS581B–SEPTEMBER 2003–REVISED SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX
UNIT
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
tpLH
tpHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Differential output signal rise time
Differential output signal fall time
Output skew
1
1
1
1
1.5
1.5
2.4
2.4
2
tf
See Figure 5
2
tsk(o)
tsk(p)
tsk(pp)
tjit(per)
tjit(c-c)
tjit(det)
tjit(pp)
tPZH
tPZL
tPHZ
tPLZ
350
150
600
4
Pulse skew (|tPHL– tPLH|)
0
(2)
Part-to-part skew
Period jitter, rms (1 standard deviation)(3)
100 MHz clock input(4)
Cycle-to-cycle jitter, rms
45
150
190
7
Deterministic jitter
Peak-to-peak jitter(2)(6)
200 Mbps 215–1 PRBS input(5)
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
7
See Figure 6
7
7
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(5) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
(6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
5
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SN65MLVD082
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RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
tpLH
tpHL
tr
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Output signal rise time
2
2
1
1
4
4
6
6
ns
ns
ns
ns
ps
ps
ns
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
2.3
2.3
350
350
1
tf
Output signal fall time
CL = 15 pF, See Figure 10
tsk(o)
tsk(p)
tsk(pp)
tjit(per)
tjit(c-c)
Output skew
Pulse skew (|tPHL– tPLH|)
Part-to-part skew(2)
50
)
(3)
Period jitter, rms (1 standard deviation) (
7
100 MHz clock input(4)
Cycle-to-cycle jitter, rms
110
550
480
720
660
30
Type 1
Type 2
Type 1
Type 2
tjit(det)
Deterministic jitter
200 Mbps 215–1 PRBS input(5)
(3)(6)
tjit(pp)
Peak-to-peak jitter
tPZH
tPZL
tPHZ
tPLZ
Enable time, high-impedance-to-high-level output
Enable time, high-impedance-to-low-level output
Disable time, high-level-to-high-impedance output
Disable time, low-level-to-high-impedance output
30
CL = 15 pF, See Figure 11
18
28
(1) All typical values are at 25°C and with a 3.3-V supply voltage.
(2) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers.
(4) VID = 200 mVpp ('080), VID = 400 mVpp ('082), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples.
(5) VID = 200 mVpp ('080), VID = 400 mVpp ('082), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples.
(6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).
6
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SN65MLVD082
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PARAMETER MEASUREMENT INFORMATION
V
CC
I
A
A
B
I
I
D
V
AB
I
B
V
A
V
I
V
OS
V
B
V
A
+ V
2
B
Figure 1. Driver Voltage and Current Definitions
3.32 kΩ
A
+
-1 V ≤ V
≤ 3.4 V
V
AB
49.9 Ω
D
test
_
B
3.32 kΩ
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
A
B
R1
≈ 1.3 V
≈ 0.7 V
24.9 Ω
A
B
C1
1 pF
D
V
∆V
OS(SS)
OS(PP)
V
OS
C3
2.5 pF
R2
24.9 Ω
V
OS(SS)
C2
1 pF
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse frequency = 1
MHz, duty cycle = 50 ±5%.
B. C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D. The measurement of VOS(PP) is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
I
OS
A
B
0 V or V
CC
+
V
-
-1 V or 3.4 V
Test
Figure 4. Driver Short-Circuit Test Circuit
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PARAMETER MEASUREMENT INFORMATION (continued)
A
C1
1 pF
C3
0.5 pF
R1
50 Ω
Output
D
B
C2
1 pF
V
V
CC
/2
CC
Input
0 V
t
t
pHL
pLH
V
SS
0.9V
SS
V
P(H)
Output
0 V
V
P(L)
0.1V
SS
0 V
SS
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ±5%.
B. C1, C2, and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A
C1
1 pF
D
C4
0.5 pF
0 V or V
Output
CC
C3
2.5 pF
C2
1 pF
B
R2
24.9 Ω
DE
V
V
CC
/2
CC
DE
0 V
t
t
t
pZH
pHZ
0.6 V
0.1 V
Output With
D at V
0 V
CC
t
pZL
pLZ
Output With
D at 0 V
0 V
-0.1 V
-0.6 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ±5%.
B. C1, C2, C3, and C4 includes instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C. R1 and R2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the D.U.T.
D. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
8
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PARAMETER MEASUREMENT INFORMATION (continued)
A
0 V or V
CC
B
V
A
or V
B
1.62 kΩ , ±1%
Figure 7. Maximum Steady State Output Voltage
V
V
CC
CLOCK
INPUT
/2
CC
0 V
1/f0
Period Jitter
IDEAL
OUTPUT
V
V
CC
0 V
PRBS INPUT
/2
CC
V
A
-V
B
1/f0
0 V
ACTUAL
OUTPUT
Peak to Peak Jitter
0 V
V
-V
-V
A
B
V
-V
B
A
OUTPUT 0 V
t
c(n)
V
A
t
=
t
-1/f0
B
jit(per)
c(n)
t
jit(pp)
Cycle to Cycle Jitter
OUTPUT
0 V
- V
V
A
B
t
t
c(n+1)
c(n)
t
= | t
- t
|
jit(cc)
c(n) c(n+1)
A. All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 215–1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
I
A
A
B
I
O
R
V
ID
V
O
V
CM
V
A
I
B
(V + V )/2
V
B
A
B
Figure 9. Receiver Voltage and Current Definitions
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Table 1. Type-1 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER
OUTPUT(1)
INPUT VOLTAGE
VIA
VIB
VID
VIC
2.400
0.000
3.400
3.350
–1.350
–1.400
0.000
2.400
3.350
3.400
–1.400
–1.350
2.400
1.200
1.200
3.375
3.375
–1.375
–1.375
H
L
–2.400
0.050
H
L
–0.050
0.050
H
L
–0.050
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)
Table 2. Type-2 Receiver Input Threshold Test Voltages
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMON-
MODE INPUT VOLTAGE
APPLIED VOLTAGES
RECEIVER
OUTPUT(1)
VIA
VIB
VID
VIC
2.400
0.000
3.400
3.400
–1.250
–1.350
0.000
2.400
3.250
3.350
–1.400
–1.400
2.400
–2.400
0.150
0.050
0.150
0.050
1.200
1.200
3.325
3.375
–1.325
–1.375
H
L
H
L
H
L
(1) H= high level, L = low level, output state assumes receiver is enabled (RE = L)
V
ID
V
A
C
L
V
O
15 pF
V
B
V
1.2 V
1.0 V
A
V
B
V
ID
0.2 V
0 V
-0.2 V
t
t
pLH
pHL
V
OH
V
O
90%
10%
V
V
/2
CC
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ±5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture
capacitance within 2 cm of the D.U.T.
B. The measurement is made on test equipment with a –3 dB bandwidth of at least 1 GHz.
Figure 10. Receiver Timing Test Circuit and Waveforms
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R
L
B
A
1.2 V
499 Ω
+
C
L
V
TEST
_
V
O
Inputs
RE
15 pF
V
CC
V
TEST
1 V
A
V
V
CC
RE
/2
/2
CC
0 V
t
t
pLZ
pZL
V
CC
V
CC
V
O
V
OL
V
OL
+0.5 V
V
TEST
0 V
1.4 V
A
V
V
CC
RE
/2
CC
0 V
t
t
pHZ
pZH
V
V
V
OH
-0.5 V
OH
V
O
/2
CC
0 V
A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T.
C. CL is the instrumentation and fixture capacitance within 2 cm of the DUT and ±20%. The measurement is made on
test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 11. Receiver Enable/Disable Time Test Circuit and Waveforms
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INPUTS
- V
CLOCK INPUT
V
A
V
CM
B
0.2 V (’080) 1 V
0.4 V (’082)
V
A
-V
B
1/f0
Period Jitter
V
OH
IDEAL
OUTPUT
V
A
V /2
CC
PRBS INPUT
V
OL
1/f0
V
B
V
OH
ACTUAL
OUTPUT
Peak to Peak Jitter
V
/2
CC
V
OH
V
OL
OUTPUT
V
/2
t
CC
c(n)
t
=
t
-1/f0
V
OL
jit(per)
c(n)
t
jit(pp)
Cycle to Cycle Jitter
V
OH
OUTPUT
V /2
CC
V
OL
t
t
c(n+1)
c(n)
t
= | t
- t
|
jit(cc)
c(n) c(n+1)
A. All input pulses are supplied by an Agilent 8304A Stimulus System with plug-in TBD.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter and deterministic jitter are measured using a 200 Mbps 215–1 PRBS input.
Figure 12. Receiver Jitter Measurement Waveforms
Table 3. Terminal Functions
PIN
TYPE
DESCRIPTION
NAME
1D–8D
1R–8R
1A–8A
1B–8B
NO.
58, 57, 52, 51, 46, 45, 40, 39
59, 56, 53, 50, 47, 44, 41, 38
6, 8, 12, 14, 18, 20, 24, 26
7, 9, 13, 15, 19, 21, 25, 27
Input
Data inputs for drivers
Output
Bus I/O
Bus I/O
Data output for receivers
M-LVDS bus noninverting input/output
M-LVDS bus inverting input/output
10, 16, 22, 28, 36, 37, 43, 49, 55, 62, 63,
64
GND
Power
Circuit ground
VCC
RE
5, 11, 17, 23, 34, 35, 42, 48, 54, 60, 61
Power
Input
Input
Supply voltage
33
Receiver enable, active low, enables all receivers
Driver enable, active high, individual enables
1DE–8DE
1, 2, 3, 4, 29, 30, 31, 32
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PIN ASSIGNMENTS
DGG PACKAGE
(TOP VIEW)
64
63
62
61
60
1DE
2DE
3DE
4DE
VCC
1A
1
2
3
4
5
6
7
8
9
GND
GND
GND
VCC
VCC
1R
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1B
1D
2A
2B
GND
VCC
3A
2D
2R
GND
VCC
3R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
3B
3D
4A
4D
4B
4R
GND
VCC
5A
GND
VCC
5R
5B
6A
6B
GND
VCC
7A
7B
8A
8B
GND
5DE
6DE
7DE
8DE
5D
6D
6R
GND
VCC
7R
7D
8D
8R
GND
GND
VCC
VCC
RE
DEVICE FUNCTION TABLE
RECEIVER (082)
INPUTS
RECEIVER (080)
INPUTS
OUTPUT
OUTPUT
R
RE
RE
V
ID
= V - V
A B
R
V
= V - V
ID A B
L
L
H
?
L
Z
Z
L
L
H
?
L
Z
Z
V
≥ 50 mV
V
≥ 150 mV
ID
ID
-50 mV < V < 50 mV
50 mV < V < 150 mV
ID
ID
V
ID
≤ -50 mV
L
V
≤ 50 mV
L
ID
X
X
H
X
X
H
Open
Open
Open Circuit
?
Open Circuit
L
L
L
DRIVERS
INPUT ENABLE OUTPUTS
A OR Y B OR Z
D
DE
L
H
H
H
OPEN
L
L
H
L
Z
Z
H
L
H
Z
Z
H
OPEN
X
X
H = high level, L = low level, Z = high impedance, X = Don’t care, ? = indeterminate
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
DRIVER OUTPUT
DRIVER INPUT AND DRIVER ENABLE
RECEIVER ENABLE
V
CC
V
CC
V
CC
360 kΩ
400 Ω
400 Ω
D or DE
7 V
Y or Z
RE
7 V
360 kΩ
RECEIVER INPUT
RECEIVER OUTPUT
V
CC
V
CC
100 kΩ
250 kΩ
100 kΩ
250 kΩ
10 Ω
10 Ω
R
A
B
200 kΩ
200 kΩ
7 V
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREQUENCY
180
150
120
90
180
V
= 3.3 V
CC
V
= 3.3 V,
CC
T = 25°C
A
T = 25°C,
A
f = 100 MHz
150
120
90
Tx
Tx
Rx
Rx
60
60
30
30
0
0
10
30
50
70
90
110
130
−50
−30
−10
10
30
50
70
90
f − Frequency − MHz
T − Free-Air Temperature − °C
A
Figure 13.
Figure 14.
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
FREQUENCY
OUTPUT RESISTANCE
550
530
510
490
470
1500
V
= 3.3 V
CC
V
= 3.3 V,
CC
T = 25°C
A
T = 25°C
A
1200
900
600
300
0
450
0
20
40
60
80
100
120
140
0
50
100
150
200
f − Frequency − MHz
Output Resistance − Ω
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE
DRIVER PROPAGATION DELAY
vs
vs
FREQUENTRACE LENGTH
FREE-AIR TEMPERATURE
2.5
2
600
V
T
= 3.3 V,
= 25°C,
V
T
A
= 3.3 V
CC
= 25°C
CC
A
f = 1 MHz,
550
500
t
PLH
t
1.5
1
PHL
450
400
0.5
0
350
300
−50
−30
−10
10
30
50
70
90
0
10
20
30
40
50
60
70
80
Trace Length − Inches
T
A
− Free-Air Temperature − °C
Figure 17.
Figure 18.
RECEIVER TYPE-1 PROPAGATION DELAY
RECEIVER TYPE-2 PROPAGATION DELAY
vs
vs
FREE-AIR TEMPERTURE
FREE-AIR TEMPERATURE
4
3.6
3.2
2.8
4
3.6
3.2
2.8
V
V
= 3.3 V,
= 1 V,
CC
V
V
= 3.3 V,
= 1 V,
CC
IC
IC
|V | = 400 mV,
ID
f = 1 MHz
|V | = 200 mV,
ID
f = 1 MHz
t
PLH
t
PLH
t
PHL
t
PHL
2.4
2
2.4
2
−50
−30
−10
10
30
50
70
90
−50
−30
−10
10
30
50
70
90
T − Free-Air Temperature − °C
A
T
A
− Free-Air Temperature − °C
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
DRIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
TYPE-1 RECEIVER TRANSITION TIME
vs
FREE-AIR TEMPERATURE
2.5
2.5
2.1
1.7
1.3
0.9
0.5
V
= 3.3 V,
CC
V
V
= 3.3 V,
= 1 V,
CC
f = 1 MHz,
T
A
IC
= 25°C
|V | = 200 mV,
ID
f = 1 MHz
2.1
1.7
t
t
r
r
t
f
t
f
1.3
0.9
0.5
−50
−30
T
−10
10
30
50
70
90
−50
−30
−10
10
30
50
70
90
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
A
Figure 21.
Figure 22.
TYPE-2 RECEIVER TRANSITION TIME
ADDED RECEIVER TYPE-1 PERIOD JITTER
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
2.5
2.1
1.7
1.3
18
15
12
V
V
= 3.3 V,
= 1 V,
CC
V
V
= 3.3 V
= 1 V,
CC
IC
IC
|V | = 400 mV,
ID
f = 1 MHz
|V | = 200 mV,
ID
Input = Clock
t
r
9
t
f
6
3
0
0.9
0.5
−50
−30
−10
10
30
50
70
90
15
25
35
45
55
65
75
85
95 105
T
A
− Free-Air Temperature − °C
f − Frequency − MHz
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
ADDED RECEIVER TYPE-2 PERIOD JITTER
ADDED DRIVER PERIOD JITTER
vs
vs
FREQUENCY
FREQUENCY
18
15
12
18
15
V
= 3.3 V
CC
V
V
= 3.3 V
= 1 V,
CC
Input = Clock
IC
|V | = 400 mV,
ID
Input = Clock
12
9
6
9
6
3
0
3
0
15 25
35 45
55 65
75 85
95 105
15
25 35
45
55
65
75
85
95 105
f − Frequency − MHz
f − Frequency − MHz
Figure 25.
Figure 26.
ADDED RECEIVER TYPE-1 CYCLE-TO-CYCLE JITTER
ADDED RECEIVER TYPE-2 CYCLE-TO-CYCLE JITTER
vs
vs
FREQUENCY
FREQUENCY
60
60
50
40
30
20
V
V
= 3.3 V
= 1 V,
CC
V
V
= 3.3 V
= 1 V,
CC
IC
IC
|V | = 400 mV,
ID
Input = Clock
50
40
30
20
|V | = 200 mV,
ID
Input = Clock
10
0
10
0
15
25 35
45 55
65 75
85 95 105
15
25
35
45
55
65 75
85
95 105
f − Frequency − MHz
f − Frequency − MHz
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
ADDED DRIVER CYCLE-TO-CYCLE JITTER
ADDED RECEIVER TYPE-1 DETERMINISTIC JITTER
vs
vs
FREQUENCY
DATA RATE
350
300
250
200
150
100
60
50
V
= 3.3 V,
= 25°C,
= Varying,
CC
V
= 3.3 V
CC
T
A
Input = Clock
V
IC
15
Input = PRBS 2 −1
40
30
20
10
0
50
0
30
50 70
90 110 130 150 170 190 210
15
25
35
45
55 65
75
85
95 105
Data Rate − Mbps
f − Frequency − MHz
Figure 29.
Figure 30.
ADDED RECEIVER TYPE-2 DETERMINISTIC JITTER
ADDED RECEIVER TYPE-1 PEAK-TO-PEAK JITTER
vs
vs
DATA RATE
DATA RATE
350
300
250
200
150
450
360
270
180
V
= 3.3 V,
CC
V
= 3.3 V,
= 25°C,
= Varying,
CC
|V | = 200 mV,
ID
T
A
V
IC
= 1 V
V
IC
15
15
Input = PRBS 2 −1
Input = PRBS 2 −1
100
50
0
90
0
30 50 70 90 110 130 150 170 190 210
30 50
70 90 110 130 150 170 190 210
Data Rate − Mbps
Data Rate − Mbps
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
ADDED RECEIVER TYPE-2 PEAK-TO-PEAK JITTER
ADDED DRIVER PEAK-TO-PEAK JITTER
vs
vs
DATA RATE
DATA RATE
120
100
450
360
270
180
V
T
= 3.3 V
= 25°C
V
= 3.3 V,
CC
CC
|V | = 400 mV,
A
ID
15
Input = PRBS 2 −1
V
IC
= 1 V
15
Input = PRBS 2 −1
80
60
40
90
0
20
0
30 50 70
90 110 130 150 170 190 210
30
50
70 90 110 130 150 170 190 210
Data Rate − Mbps
Data Rate − Mbps
Figure 33.
Figure 34.
DRIVER OUTPUT EYE PATTERN
200 Mbps, 215–1 PRBS, VCC = 3.3 V
RECEIVER OUTPUT EYE PATTERN
200 Mbps, 215–1 PRBS, VCC = 3.3 V
|VID| = 200 mV, VIC = 1 V
Horizontal Scale = 1 ns/div
Horizontal Scale = 1 ns/div
Figure 35.
Figure 36.
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APPLICATION INFORMATION
Source Synchronous System Clock (SSSC)
There are two approaches to transmit data in a synchronous system: centralized synchronous system clock
(CSSC) and source synchronous system clock (SSSC). CSSC systems synchronize data transmission between
different modules using a clock signal from a centralized source. The key requirement for a CSSC system is for
data transmission and reception to complete during a single clock cycle. The maximum operating frequency is
the inverse of the shortest clock cycle for which valid data transmission and reception can be ensured. SSSC
systems achieve higher operating frequencies by sending clock and data signals together to eliminate the flight
time on the transmission media, backplane, or cables. In SSSC systems, the maximum operating frequency is
limited by the cumulated skews that can exist between clock and data. The absolute flight time of data on the
backplane does not provide a limitation on the operating frequency as it does with CSSC.
The SN65MLVD082 can be designed for interfacing the data and clock to support source synchronous system
clock (SSSC) operation. It is specified for transmitting data up to 250 Mbps and clock frequencies up to 125
MHz. The figure below shows an example of a SSSC architecture supported by M-LVDS transceivers. The
SN65MLVD206, a single channel transceiver, transmits the main system clock between modules. A retiming unit
is then applied to the main system clock to generate a local clock for subsystem synchronization processing.
System operating data (or control) and subsystem clock signals are generated from the data processing unit,
such as a microprocessor, FPGA, or ASIC, on module 1, and sent to slave modules through the SN65MLVD082.
Such design configurations are common while transmitting parallel control data over the backplane with a higher
SSSC subsystem clock frequency. The subsystem clock frequency is aligned with the operating frequencies of
the data processing unit to synchronize data transmission between different units.
Main System Clock
MLVD206
1Tx 1Rx
Modules 1
Modules N
Data Process Unit
ASIC/FPGA
Data Process Unit
ASIC/FPGA
Timing
Process
Unit
Timing
Process
Unit
uController
uController
tsk(o)Source
1 Data Width 15
1
Data Width 15
Subsystem
Clock
Subsystem
Clock
Number of Modules
tsk(p-p)RCVR
MLVD206
1Tx 1Rx
MLVD206
1Tx 1Rx
MLVD080/082 (x2)
8Tx 8Rx
MLVD080/082 (x2)
8Tx 8Rx
tsk(p-p)DRVR
Centralized - Synchronous Main System Clock M - LVDS Differential Bus
80~100 Ω
R
T
80~100 Ω
R
T
Data/Control M - LVDS Differential Bus #1 ~ #15
tsk(flight)BP
80~100 Ω
80~100 Ω
R
T
80~100 Ω
R
T
Source - Synchronous Subsystem Clock M - LVDS Differential Bus
80~100 Ω
R
T
R
T
M- LVDS Backplane
Figure 37. Using Differential M-LVDS to Perform Source Synchronous System Clock Distribution
The maximum SSSC frequencies in a transparent mode can be calculated with the following equation:
fmax(clk) < 1/[ tsk(o)Source + tsk(p-p)DRVR + tsk(flight)BP + tsk(p-p)RCVR
Setup time and hold time on the receiver side are decided by the data processing unit, FPGA, or ASIC in this
example. By considering data passes through the transceiver only, the general calculation result is 238 MHz
when using the following data:
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APPLICATION INFORMATION (continued)
tsk(o)Source = 2.0 ns – Output skew of data processing unit; any skew between data bits, or clock and data bits
tsk(p-p)DRVR = 0.6 ns – Driver part-to-part skew of the SN65MLVD082
tsk(flight)BP = 0.4 ns – Skew of propagation delay on the backplane between data and clock
tsk(p-p)RCVR = 1.0 ns – Receiver part-to-part skew of the SN65MLVD082
The 238-MHz maximum operating speed calculated above was determined based on data and clock skews only.
Another important consideration when calculating the maximum operating speed is output transition time.
Transition-time-limited operating speed can be calculated from the following formula:
1
f + 45%
2 ttransition
(1)
Using the typical transition time of the SN65MLVD082 of 1.4 ns, a transition-time-limited operating frequency of
170 MHz can be supported.
In addition to the high operating frequencies of SSSC that can be ensured, the SN65MLVD082 presents other
benefits as other M-LVDS bus transceivers can provide:
•
•
•
•
Robust system operation due to common mode noise cancellation using a low voltage differential receiver
Low EMI radiation noise due to differential signaling improves signal integrity through the backplane
A singly terminated transmission line is easy to design and implement
Low power consumption in both active and idle modes minimizes thermal concerns on each module
In dense backplane design, these benefits are important for improving the performance of the whole system.
A similar result can be achieved with the SN65MLVD080.
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APPLICATION INFORMATION (continued)
LIVE INSERTION/GLITCH-FREE POWER UP/DOWN
The SN65MLVD080/082 family of products offered by Texas Instruments provides a glitch-free powerup/down
feature that prevents the M-LVDS outputs of the device from turning on during a powerup or powerdown event.
This is especially important in live insertion applications, when a device is physically connected to an M-LVDS
multipoint bus and VCC is ramping.
While the M-LVDS interface for these devices is glitch free on powerup/down, the receiver output structure is not.
Figure 38 shows the performance of the receiver output pin, R (CHANNEL 2), as Vcc (CHANNEL 1) is ramped.
Figure 38. M-LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
The glitch on the R pin is independent of the RE voltage. Any complications or issues from this glitch are easily
resolved in power sequencing or system requirements that suspend operation until VCC has reached a steady
state value.
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PACKAGING INFORMATION
Orderable Device
SN65MLVD080DGG
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
64
64
64
64
64
64
64
64
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN65MLVD080DGGG4
SN65MLVD080DGGR
SN65MLVD080DGGRG4
SN65MLVD082DGG
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
DGG
DGG
DGG
DGG
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SN65MLVD082DGGG4
SN65MLVD082DGGR
SN65MLVD082DGGRG4
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
24
SN65MLVD080DGGR
SN65MLVD082DGGR
DGG
DGG
64
64
TAI
TAI
8.4
8.4
17.3
17.3
1.7
1.7
12
12
24
24
Q1
Q1
330
24
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN65MLVD080DGGR
SN65MLVD082DGGR
DGG
DGG
64
64
TAI
TAI
0.0
0.0
0.0
0.0
0.0
0.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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