SN74221NE4 [TI]
DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS; 施密特触发器输入双单稳态触发器
| 型号： | SN74221NE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS |
| 文件： | 总23页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
SN54221, SN54LS221 . . . J PACKAGE
SN74221 . . . N PACKAGE
SN74LS221 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
D
D
Dual Versions of Highly Stable SN54121
and SN74121 One Shots
SN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121
and SN74121 One Shots
1A
1B
1CLR
1Q
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
1R /C
ext ext
1C
1Q
2Q
2CLR
2B
D
D
Pinout Is Identical to the SN54123,
SN74123, SN54LS123, and SN74LS123
ext
2Q
Overriding Clear Terminates Output Pulse
2C
ext
MAXIMUM
OUTPUT
PULSE
2R /C
ext ext
GND
2A
TYPE
LENGTH(S)
SN54221
21
28
49
70
SN54LS221 . . . FK PACKAGE
(TOP VIEW)
SN74221
SN54LS221
SN74LS221
description/ordering information
3
2
1
20 19
18
1C
1Q
1CLR
1Q
4
5
6
7
8
ext
The ’221 and ’LS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the ’121 devices.
Each multivibrator features a negative-transition-
triggered input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.
17
16
15
14
NC
NC
2Q
2Q
2CLR
2C
ext
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
SN74221N
SN74221N
PDIP − N
SOIC − D
Tube
SN74LS221N
SN74LS221D
SN74LS221DR
SN74LS221NSR
SN74LS221DBR
SNJ54221J
SN74LS221N
Tube
0°C to 70°C
LS221
Tape and reel
Tape and reel
Tape and reel
SOP − NS
74LS221
SSOP − DB
LS221
SNJ54221J
SNJ54LS221J
CDIP − J
Tube
Tube
SNJ54LS221J
SNJ54LS221FK
−55°C to 125°C
LCCC − FK
SNJ54LS221FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢍ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢌꢑ ꢇꢗ ꢙꢓ ꢰ ꢗꢱꢲꢂ ꢱꢂꢆ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢆ ꢀꢁ ꢂ ꢃꢇ ꢀꢄ ꢄ ꢅꢆ ꢀ ꢁꢈ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢈ ꢃ ꢇ ꢀꢄ ꢄ ꢅ
ꢉ ꢊꢋꢇ ꢌ ꢍꢁꢍ ꢀꢎꢋꢏ ꢇꢐ ꢌꢊ ꢇꢎꢑ ꢒ ꢑ ꢏ ꢓꢋꢎꢍ ꢓꢀ
ꢔꢑ ꢎ ꢕ ꢀꢖ ꢕ ꢌꢑ ꢎ ꢎꢗꢎ ꢓꢑ ꢘ ꢘꢐ ꢓ ꢑ ꢁꢙ ꢊꢎ ꢀ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to V
noise, typically of 1.5 V, also is provided by internal latching circuitry.
CC
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With R = 2 kΩ and C = 0, an output pulse typically of 30 ns is achieved
ext
ext
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of V
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
and
CC
Jitter-free operation is maintained over the full temperature and V ranges for more than six decades of timing
CC
capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,
2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: t (out) = C
R
In2 ≈ 0.7 C
R
. In
w
ext ext
ext ext
circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ
can be used. Also, the range of jitter-free output pulse widths is extended if V is held to 5 V and free-air
CC
temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended R . Higher
T
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than 0.5% for given external timing
components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of R and/or C ; however, the polarity of the capacitor must be changed.
ext
ext
FUNCTION TABLE
(each monostable multivibrator)
INPUTS
OUTPUTS
CLR
L
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
X
X
†
†
†
†
†
†
H
↑
H
↓
L
H
H
‡
↑
†
‡
Pulsed-output patterns are tested during
AC switching at 25°C with R = 2 kΩ, and
ext
C
= 80 pF.
ext
This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢔ ꢑꢎ ꢕ ꢀꢖꢕ ꢌꢑ ꢎꢎꢗꢎ ꢓꢑꢘ ꢘ ꢐꢓ ꢑ ꢁꢙ ꢊ ꢎ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
timing component connections
V
CC
R
ext
To C
ext
Terminal
To R /C
ext ext
Terminal
NOTE: Due to the internal circuit, the R /C
ext ext
terminal never is more positive than the C terminal.
ext
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢆ ꢀꢁ ꢂ ꢃꢇ ꢀꢄ ꢄ ꢅꢆ ꢀ ꢁꢈ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢈ ꢃ ꢇ ꢀꢄ ꢄ ꢅ
ꢉ ꢊꢋꢇ ꢌ ꢍꢁꢍ ꢀꢎꢋꢏ ꢇꢐ ꢌꢊ ꢇꢎꢑ ꢒ ꢑ ꢏ ꢓꢋꢎꢍ ꢓꢀ
ꢔꢑ ꢎ ꢕ ꢀꢖ ꢕ ꢌꢑ ꢎ ꢎꢗꢎ ꢓꢑ ꢘ ꢘꢐ ꢓ ꢑ ꢁꢙ ꢊꢎ ꢀ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
schematics of inputs and outputs
SN54/74221
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
V
CC
V
CC
100 Ω NOM
R
eq
Input
Output
A Input: R = 4 kΩ NOM
eq
B, CLR Input: R = 2 kΩ NOM
eq
SN54/74LS221
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
V
V
CC
CC
R
120 Ω NOM
eq
Input
Output
A Input: R = 25 kΩ NOM
eq
B Input: R = 15.4 kΩ NOM
eq
CLR: R = 12.5 kΩ NOM
eq
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage range, V (see Note 1): ’LS221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
’221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54221
SN74221
UNIT
MIN NOM
MAX
5.5
MIN NOM
MAX
5.25
−800
16
V
Supply voltage
4.5
5
4.75
5
V
µA
CC
OH
OL
I
I
High-level output current
Low-level output current
−800
16
mA
V/s
V/µs
°C
B input
A input
1*
1*
1
1
0
∆v/∆t
Rise or fall of input pulse rate
Operating free-air temperature
T
A
−55
125
70
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢆ ꢀꢁ ꢂ ꢃꢇ ꢀꢄ ꢄ ꢅꢆ ꢀ ꢁꢈ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢈ ꢃ ꢇ ꢀꢄ ꢄ ꢅ
ꢉ ꢊꢋꢇ ꢌ ꢍꢁꢍ ꢀꢎꢋꢏ ꢇꢐ ꢌꢊ ꢇꢎꢑ ꢒ ꢑ ꢏ ꢓꢋꢎꢍ ꢓꢀ
ꢔꢑ ꢎ ꢕ ꢀꢖ ꢕ ꢌꢑ ꢎ ꢎꢗꢎ ꢓꢑ ꢘ ꢘꢐ ꢓ ꢑ ꢁꢙ ꢊꢎ ꢀ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54221
SN74221
†
PARAMETER
UNIT
V
TEST CONDITIONS
‡
‡
MIN TYP
MAX
MIN TYP
MAX
Positive-going threshold voltage,
B input
V
V
V
V
= MIN
1.55
1.35
2*
1.55
1.35
2
T+
CC
Negative-going threshold voltage,
B input
= MIN
0.8*
2.4
0.8
2.4
V
T−
CC
V
V
V
V
CC
V
CC
V
CC
V
CC
= MIN,
= MIN,
= MIN,
= MAX,
I = −12 mA
−1.5
−1.5
V
V
IK
I
I
= −800 µA
3.4
0.2
3.4
0.2
OH
OL
OH
OL
I
= 16 mA
0.4
1
0.4
1
V
I
I
V = 5.5 V
I
mA
A input
40
40
I
V
= MAX,
V = 2.4 V
I
µA
IH
CC
CLR, B input
A input
80
80
−1.6
−3.2
−55
50*
80*
−1.6
−3.2
−55
50
V
CC
V
CC
V
CC
= MAX,
= MAX
= MAX
V = 0.4 V
I
mA
mA
mA
I
I
I
IL
CLR, B input
§
−20
−18
OS
CC
Quiescent
Triggered
26
46
26
46
80
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
CC
A
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54221
SN74221
UNIT
MIN
50
MAX
MIN
50
20
15
1.4
0
MAX
A or B input
CLR
t
t
Pulse duration
ns
w
20
CLR
15
ns
kΩ
µF
Setup time, inactive-state¶
External timing resistance
External timing capacitance
su
R
C
1.4*
30*
40
1000
67%
90%
ext
ext
0* 1000*
67%
R
R
= 2 kΩ
ext
ext
Output duty cycle
= MAX R
90%
ext
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶
Inactive-state setup time also is referred to as recovery time.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀ
ꢀ
ꢔ ꢑꢎ ꢕ ꢀꢖꢕ ꢌꢑ ꢎꢎꢗꢎ ꢓꢑꢘ ꢘ ꢐꢓ ꢑ ꢁꢙ ꢊ ꢎ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
switching characteristics V
= 5 V, R = 400 Ω, T = 25_C (see Figures 1 and 2)
CC
L
A
SN54221
TYP
45
SN74221
TYP
45
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
ns
MIN
MAX
70
MIN
MAX
70
A
B
A
B
Q
t
PLH
PHL
35
55
35
55
C
C
= 80 pF,
R
= 2 kΩ
= 2 kΩ
ext
ext
ext
ext
50
80
50
80
Q
t
40
65
40
65
t
t
27
27
Q
Q
PHL
CLR
= 80 pF,
R
ns
40
40
PLH
70
17
110
30
150
50
70
17
110
30
150
50
C
C
C
C
= 80 pF,
= 0,
R
R
R
R
= 2 kΩ
= 2 kΩ
= 10 kΩ
= 10 kΩ
ext
ext
ext
ext
ext
ext
ext
ext
ns
t
w
A or B
Q or Q
650
6.5*
700
7
750
7.5*
650
6.5
700
7
750
7.5
= 100 pF,
= 1 µF,
ms
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
recommended operating conditions (see Note 4)
SN54LS221
MIN NOM
SN74LS221
MIN NOM
UNIT
MAX
5.5
MAX
5.25
−400
8
V
Supply voltage
4.5
5
4.75
5
V
µA
CC
OH
OL
I
I
High-level output current
Low-level output current
−400
4
mA
V/s
V/µs
°C
*
*
B input
A input
1
1
1
0
∆v/∆t
Rise or fall of input pulse rate
Operating free-air temperature
1
T
A
−55
125
70
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 4: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢆ ꢀꢁ ꢂ ꢃꢇ ꢀꢄ ꢄ ꢅꢆ ꢀ ꢁꢈ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢈ ꢃ ꢇ ꢀꢄ ꢄ ꢅ
ꢉ ꢊꢋꢇ ꢌ ꢍꢁꢍ ꢀꢎꢋꢏ ꢇꢐ ꢌꢊ ꢇꢎꢑ ꢒ ꢑ ꢏ ꢓꢋꢎꢍ ꢓꢀ
ꢔꢑ ꢎ ꢕ ꢀꢖ ꢕ ꢌꢑ ꢎ ꢎꢗꢎ ꢓꢑ ꢘ ꢘꢐ ꢓ ꢑ ꢁꢙ ꢊꢎ ꢀ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS221
SN74LS221
†
PARAMETER
UNIT
V
TEST CONDITIONS
‡
‡
MIN TYP
MAX
MIN TYP
MAX
Positive-going threshold voltage,
B input
V
V
V
V
= MIN
1
2*
1
2
T+
CC
Negative-going threshold voltage,
B input
= MIN
0.7*
2.5
0.9
0.8
2.7
0.9
V
T−
CC
V
V
V
V
= MIN,
= MIN,
I = −18 mA
−1.5
0.4
−1.5
V
V
IK
CC
I
I
I
I
= −400 µA
= 4 mA
3.4
3.4
0.25
0.35
OH
CC
OH
OL
OL
0.25
0.4
0.5
V
OL
V
CC
= MIN
V
= 8 mA
I
I
V
V
= MAX,
= MAX,
V = 7 V
I
0.1
20
0.1
mA
I
CC
V = 2.7 V
I
20
µA
CC
IH
A input
−0.4
−0.8
−100
11
−0.4
−0.8
−100
11
V
CC
V
CC
V
CC
= MAX,
= MAX
= MAX
V = 0.4 V
I
mA
mA
mA
I
I
I
IL
CLR, B input
§
−20
−20
OS
CC
Quiescent
Triggered
4.7
19
4.7
19
27*
27
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at V = 5 V, T = 25°C.
CC
A
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54LS221
SN74LS221
UNIT
MIN
50
MAX
MIN
50
40
15
1.4
0
MAX
A or B
CLR
t
t
Pulse duration
ns
w
40
¶
CLR
15
ns
kΩ
µF
Setup time, inactive state
su
R
C
1.4*
70*
100
1000
50%
90%
External timing resistance
External timing capacitance
ext
ext
0* 1000*
50%
R
R
= 2 kΩ
T
Output duty cycle
= MAX R
90%
T
ext
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶
Inactive-state setup time also is referred to as recovery time.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢇ
ꢀ
ꢄ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢈ
ꢃ
ꢄ
ꢄ
ꢉꢊꢋ ꢇ ꢌ ꢍꢁ ꢍꢀ ꢎꢋꢏꢇ ꢐ ꢌ ꢊꢇꢎ ꢑꢒ ꢑ ꢏꢓ ꢋꢎꢍ ꢓ
ꢅ
ꢆ
ꢀ
ꢁ
ꢈ
ꢃ
ꢇ
ꢀ
ꢄ
ꢄ
ꢅ
ꢀ
ꢀ
ꢔ ꢑꢎ ꢕ ꢀꢖꢕ ꢌꢑ ꢎꢎꢗꢎ ꢓꢑꢘ ꢘ ꢐꢓ ꢑ ꢁꢙ ꢊ ꢎ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
switching characteristics V
= 5 V, R = 2 kΩ, T = 25_C (see Figures 1 and 2)
CC
L
A
SN54LS221
SN74LS221
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
ns
MIN
TYP
45
MAX
70
MIN
TYP
45
MAX
70
A
B
A
B
Q
t
PLH
PHL
35
55
35
55
C
C
= 80 pF,
R
= 2 kΩ
= 2 kΩ
ext
ext
ext
ext
50
80
50
80
Q
t
40
65
40
65
t
t
35
55
35
55
Q
Q
PHL
CLR
= 80 pF,
R
ns
44
65
44
65
PLH
70
20
120
47
150
70
70
20
120
47
150
70
C
C
C
C
= 80 pF,
= 0,
R
R
R
R
= 2 kΩ
= 2 kΩ
= 10 kΩ
= 10 kΩ
ext
ext
ext
ext
ext
ext
ext
ext
ns
t
w
A or B
Q or Q
670
6*
740
6.9
810
7.5*
670
6
740
6.9
810
7.5
= 100 pF,
= 1 µF,
ms
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢆ ꢀꢁ ꢂ ꢃꢇ ꢀꢄ ꢄ ꢅꢆ ꢀ ꢁꢈ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢈ ꢃ ꢇ ꢀꢄ ꢄ ꢅ
ꢉ ꢊꢋꢇ ꢌ ꢍꢁꢍ ꢀꢎꢋꢏ ꢇꢐ ꢌꢊ ꢇꢎꢑ ꢒ ꢑ ꢏ ꢓꢋꢎꢍ ꢓꢀ
ꢔꢑ ꢎ ꢕ ꢀꢖ ꢕ ꢌꢑ ꢎ ꢎꢗꢎ ꢓꢑ ꢘ ꢘꢐ ꢓ ꢑ ꢁꢙ ꢊꢎ ꢀ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
t
w
3 V
0 V
3 V
0 V
†
B
≥ 60 ns
CLR
Q
t
t
PHL
PLH
V
OH
V
OL
V
OH
V
OL
t
t
PLH
PHL
Q
CONDITION 1: TRIGGER FROM B, THEN CLR
3 V
0 V
3 V
0 V
†
B
≥ 60 ns
CLR
Q
V
V
OH
OL
CONDITION 2: TRIGGER FROM B, THEN CLR
3 V
0 V
3 V
0 V
†
B
t
su
≥ 50 ns
≥ 0
CLR
Q
t
w
Triggered
V
V
OH
OL
Not Triggered
CONDITION 3: CLR OVERRIDING B, THEN TRIGGER FROM B
†
A is low.
Figure 1. Switching Characteristics
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢇ
ꢀ
ꢄ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢈ
ꢃ
ꢄ
ꢄ
ꢉꢊꢋ ꢇ ꢌ ꢍꢁ ꢍꢀ ꢎꢋꢏꢇ ꢐ ꢌ ꢊꢇꢎ ꢑꢒ ꢑ ꢏꢓ ꢋꢎꢍ ꢓ
ꢅ
ꢆ
ꢀ
ꢁ
ꢈ
ꢃ
ꢇ
ꢀ
ꢄ
ꢄ
ꢅ
ꢀ
ꢀ
ꢔ ꢑꢎ ꢕ ꢀꢖꢕ ꢌꢑ ꢎꢎꢗꢎ ꢓꢑꢘ ꢘ ꢐꢓ ꢑ ꢁꢙ ꢊ ꢎ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
3 V
0 V
†
B
≥ 50 ns
≥ 50 ns
CLR
Q
V
V
OH
OL
CONDITION 4: TRIGGERING FROM POSITIVE TRANSITION OF CLR
t
w
3 V
0 V
3 V
0 V
‡
A
≥ 60 ns
CLR
Q
t
t
PHL
PLH
V
OH
V
OL
V
OH
V
OL
t
t
PLH
PHL
Q
CONDITION 5: TRIGGER FROM A, THEN CLR
3 V
0 V
‡
A
t
w
V
OH
V
OL
V
OH
V
OL
Q
Q
t
w
CONDITION 6: TRIGGER FROM A
†
‡
A is low.
B and CLR are high.
NOTES: A. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50Ω; for SN54/74221, t ≤ 7 ns,
O
r
t ≤ 7 ns, for SN54/74LS221, t ≤ 15 ns, t ≤ 6 ns.
f
r
f
B. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.
Figure 1. Switching Characteristics (Continued)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢆ ꢀꢁ ꢂ ꢃꢇ ꢀꢄ ꢄ ꢅꢆ ꢀ ꢁꢈ ꢃ ꢄꢄ ꢅ ꢆ ꢀ ꢁꢈ ꢃ ꢇ ꢀꢄ ꢄ ꢅ
ꢉ ꢊꢋꢇ ꢌ ꢍꢁꢍ ꢀꢎꢋꢏ ꢇꢐ ꢌꢊ ꢇꢎꢑ ꢒ ꢑ ꢏ ꢓꢋꢎꢍ ꢓꢀ
ꢔꢑ ꢎ ꢕ ꢀꢖ ꢕ ꢌꢑ ꢎ ꢎꢗꢎ ꢓꢑ ꢘ ꢘꢐ ꢓ ꢑ ꢁꢙ ꢊꢎ ꢀ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Test
Point
R
L
From Output
Under Test
(see Note B)
High-Level
Pulse
C
= 15 pF
L
(see Note A)
t
w
Low-Level
Pulse
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
0 V
Input
t
PHL
t
PLH
3 V
0 V
V
OH
OL
In-Phase
Output
Timing
Input
V
t
t
PLH
h
t
su
t
PHL
3 V
0 V
V
Data
Input
OH
OL
Out-of-Phase
Output
V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
B. All diodes are 1N3064 or equivalent.
C. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω and, for SN54/74221,
C includes probe and jig capacitance.
L
O
t ≤ 7 ns, t ≤ 7 ns, for SN54/74LS221, t ≤ 15 ns, t ≤ 6 ns.
r
f
r
f
E. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.
Figure 2. Load Circuits and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢂ
ꢃ
ꢇ
ꢀ
ꢄ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢈ
ꢃ
ꢄ
ꢄ
ꢉꢊꢋ ꢇ ꢌ ꢍꢁ ꢍꢀ ꢎꢋꢏꢇ ꢐ ꢌ ꢊꢇꢎ ꢑꢒ ꢑ ꢏꢓ ꢋꢎꢍ ꢓ
ꢅ
ꢆ
ꢀ
ꢁ
ꢈ
ꢃ
ꢇ
ꢀ
ꢄ
ꢄ
ꢅ
ꢀ
ꢀ
ꢔ ꢑꢎ ꢕ ꢀꢖꢕ ꢌꢑ ꢎꢎꢗꢎ ꢓꢑꢘ ꢘ ꢐꢓ ꢑ ꢁꢙ ꢊ ꢎ
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
†
TYPICAL CHARACTERISTICS (SN54/74221 ONLY)
VARIATION IN OUTPUT PULSE
DISTRIBUTION OF UNITS
FOR
vs
SUPPLY VOLTAGE
OUTPUT PULSE
1
C
R
T
A
= 60 pF
= 10 kΩ
= 25°C
ext
ext
V
T
A
= 5 V
CC
= 25°C
0.5
t
≈ 420 ns
CC
w
0
at V = 5 V
− 0.5
Median
+0.5%
Median
+0.5%
−1
4.5
4.75
5
5.25
5.5
Median
− Output Pulse
V
CC
− Supply Voltage − V
t
w
Figure 3
Figure 4
VARIATION IN OUTPUT PULSE
vs
OUTPUT PULSE
vs
FREE-AIR TEMPERATURE
TIMING RESISTOR VALUE
1
10 ms
1 ms
C
ext
= 1µ F
V
C
R
= 5 V
= 60 pF
= 10 kΩ
CC
ext
ext
C
= 0.1 µ F
ext
0.5
100 µs
10 µs
C
= 0.01µ F
ext
t
≈ 420 ns
A
w
at T = 25°C
0
C
= 1000 pF
= 100 pF
ext
1 µs
100 ns
10 ns
C
V
ext
− 0.5
C
= 10 pF
ext
= 5 V
= 25°C
See Note A
20 40 70 100
CC
T
A
−1
1
2
4
7
10
0
25
50
75 100 125
−75 −50 −25
T
A
− Free-Air Temperature − °C
R
− Timing Resistor Value − kΩ
ext
Figure 5
Figure 6
†
Data for temperatures below 0°C and above 70°C, and for supply voltages below 4.75 V and above 5.25 V are applicable for the SN54221 only.
NOTE A: These values of resistance exceed the maximum recommended for use over the full military temperature range of the SN54221.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
LCCC
CDIP
CFP
Drawing
5962-8771101EA
76042012A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
FK
J
16
20
16
16
20
16
16
16
16
16
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
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Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
7604201EA
1
7604201FA
W
FK
J
1
JM38510/31402B2A
JM38510/31402BEA
JM38510/31402BFA
SN54221J
LCCC
CDIP
CFP
1
1
W
J
1
CDIP
CDIP
PDIP
1
SN54LS221J
J
1
SN74221N
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74221NE4
SN74LS221D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
N
D
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS221DBR
SN74LS221DBRE4
SN74LS221DE4
SN74LS221DR
SN74LS221DRE4
SN74LS221N
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS221N3
SN74LS221NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
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Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS221NSR
ACTIVE
ACTIVE
SO
SO
NS
NS
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS221NSRE4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54221J
SNJ54LS221FK
SNJ54LS221J
SNJ54LS221W
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
LCCC
CDIP
CFP
J
FK
J
16
20
16
16
1
1
1
1
TBD
TBD
TBD
TBD
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Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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