SN74ABT162601DGGR [TI]
18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN74ABT162601DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 信息通信管理 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：127K) |
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SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
SN54ABT162601 . . . WD PACKAGE
SN74ABT162601 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
CLKENAB
CLKAB
B1
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
3
4
GND
A2
GND
B2
5
UBT (Universal Bus Transceiver)
6
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
A3
B3
7
V
V
B4
CC
A4
CC
8
9
A5
A6
B5
B6
Latch-Up Performance Exceeds 500 mA Per
JESD 17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
A7
A8
GND
B7
B8
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 5 V, T = 25°C
CC
A
High-Impedance State During Power Up
and Power Down
A9
B9
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
A16
A17
GND
A18
OEBA
LEBA
B16
B17
GND
B18
CLKBA
CLKENBA
description
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA)inputs. The clock can be controlled by the
clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the
A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLKAB. Output-enable OEAB is active-low. When OEAB is low,
the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A
is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.
The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25-Ω series resistors
to reduce overshoot and undershoot.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
description (continued)
The SN54ABT162601 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT162601 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
CLKENAB OEAB LEAB CLKAB
A
X
L
X
X
X
H
H
L
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
X
X
X
↑
Z
L
H
X
X
L
H
‡
‡
B
B
0
0
L
L
↑
H
X
X
H
‡
§
L
L
B
0
0
L
H
B
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Output level before the indicated steady-state input conditions
were established
Output level before the indicated steady-state input conditions
were established, provided that CLKAB was low before LEAB
went low
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
logic diagram (positive logic)
1
OEAB
56
CLKENAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
29
CLKENBA
27
OEBA
CE
3
A1
54
1D
LE
B1
CLK
CE
1D
LE
CLK
To 17 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT162601 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT162601 (A port) . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
recommended operating conditions (see Note 3)
SN54ABT162601 SN74ABT162601
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
CC
V
IH
V
IL
V
I
Supply voltage
5.5
5.5
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0
V
CC
0
V
CC
A port
–24
–12
48
–32
–12
64
I
High-level output current
Low-level output current
mA
mA
OH
OL
B port
A port
I
B port
12
12
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused inputs of the devices must be held at V
or GND to ensure proper device operation. Refer to the TI application note,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT162601 SN74ABT162601
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= –1 mA
= –1 mA
= –3 mA
= –12 mA
= 48 mA
= 64 mA
= 12 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
A port
B port
2
2
V
CC
= 4.5 V
2*
2
3.35
3.85
3.1
V
OH
V
V
V
= 4.5 V,
= 5 V,
3.35
3.85
3.1
2.6
3.3
3.8
3
CC
CC
V
CC
= 4.5 V
2.6
0.55
0.55*
0.8
0.55
0.8
A port
B port
V
V
= 4.5 V
= 4.5 V,
CC
V
V
0.55
0.8
V
OL
CC
100
mV
hys
Control
inputs
V
V
= 0 to 5.5 V, V = V
I
or GND
CC
±1
±20
±50
±50
10
±1
±20
±1
±20
±50
±50
10
CC
I
µA
I
= 2.1 V to 5.5 V,
CC
A or B ports
V = V
I
or GND
CC
= 0 to 2.1 V,
V
V
CC
O
±50**
±50**
10
µA
µA
µA
I
I
I
OZPU
= 0.5 V to 2.7 V, OE = X
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
OZPD
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V
CC
O
‡
OZH
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V
CC
O
‡
–10
±100*
50
–10
–10
±100
50
µA
µA
µA
I
I
I
OZL
V
CC
= 0,
V or V ≤ 4.5 V
I O
off
V
V
= 5.5 V,
= 5.5 V
CC
O
Outputs high
50
CEX
A port
B port
–50
–25
–100
–55
–180
–100
3
–50
–25
–180
–100
3
–50
–25
–180
–100
3
§
V
= 5.5 V,
V
= 2.5 V
mA
I
CC
O
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
36
36
36
mA
CC
V = V
or GND
I
CC
Outputs disabled
3
3
3
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
50
50
50
µA
∆I
CC
or GND
CC
Control
inputs
C
C
V = 2.5 V or 0.5 V
3
9
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
and I
The parameters I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)(see Figure 1)
SN54ABT162601 SN74ABT162601
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
0
150
0
150
MHz
ns
clock
LEAB or LEBA high
2.5
3.3
4.8
2.5
1.2
2.7
0.5
2
2.5
3
w
CLKAB or CLKBA high or low
A before CLKAB↑ or B before CLKBA↑
4.3
2.5
1
CLK high
CLK low
t
Setup time
Hold time
ns
ns
A before LEAB↓ or B before LEBA↓
su
h
CLKEN before CLK↑
2.7
0
A after CLKAB↑ or B after CLKBA↑
A after LEAB↓ or B after LEBA↓
CLKEN after CLK↑
t
0.5
0
0.5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT162601 SN74ABT162601
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1.5
2
TYP
MAX
MIN
150
1.5
2
MAX
MIN
150
1.5
2
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
2.8
3.7
2.5
3.3
3.3
3.6
3.4
3.8
3.1
3.1
3.3
3.5
3.5
3.7
3.8
3.6
3.6
3.2
3.4
3.2
4
5.2
3.6
4.5
4.5
4.7
4.8
5.2
4.7
4.3
4.7
4.8
4.6
4.7
5.3
5.1
5.4
4.7
4.8
4.5
5.1
6.1
4.5
5.1
5.6
5.4
6.1
6.4
5.4
5.2
6
4.8
5.7
4
A
B
A
A
B
A
B
A
B
A
B
1
1
1
B
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
4.9
5
2
2
2
LEBA
LEAB
CLKBA
CLKAB
2
2
2
5
2
2
2
5.6
5.9
5.3
5
2
2
2
1.5
1.5
1.5
1.5
2
1.5
1.5
1.5
1.5
2
1.5
1.5
1.5
1.5
2
5.5
5.3
5.1
5.4
6.1
5.7
6.2
5.4
5.4
5.2
5.8
5.5
5.8
6.6
6.2
6.6
5.8
5.6
5.7
OEBA
OEAB
OEBA
OEAB
2
2
2
2
1.5
2
2
2
2
2
1.4
1.5
1.4
1.5
2
1.5
2
1.5
2
1.5
1.5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT162601, SN74ABT162601
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS247G – AUGUST 1992 – REVISED JULY 1998
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
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Copyright 1998, Texas Instruments Incorporated
相关型号：
SN74ABT162601DLG4
ABT SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
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