SN74ABT5402ADWG4 [TI]
12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN74ABT5402ADWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 驱动 输出元件 |
| 文件： | 总6页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
SN54ABT5402A . . . JT PACKAGE
SN74ABT5402A . . . DW PACKAGE
(TOP VIEW)
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Y1
Y2
Y3
Y4
Y5
Y6
GND
Y7
D1
D2
D3
D4
D5
1
2
3
4
5
6
7
8
9
28
27
26
25
24
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
(Output Ground Bounce) < 1 V
OLP
at V
= 5 V, T = 25°C
23 D6
CC
A
D7
V
22
21
20
Typical V
(Output Undershoot) < 0.5 V at
OLV
V
= 5 V, T = 25°C
CC
CC
A
Y8
D8
Package Options Include Plastic
Small-Outline (DW) Package and Ceramic
Chip Carriers (FK) and DIPs (JT)
Y9 10
19 D9
Y10
Y11
D10
D11
11
12
18
17
Y12 13
OE1 14
16 D12
15 OE2
description
These 12-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
SN54ABT5402A . . . FK PACKAGE
(TOP VIEW)
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1or OE2)inputishigh, all12outputsareinthe
high-impedance state.
4
3
2
1
28 27 26
25
D3
D2
D1
Y1
Y2
Y3
Y4
D10
D11
D12
OE2
OE1
Y12
Y11
5
24
23
22
21
20
19
6
7
The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
8
9
10
11
To ensure the high-impedance state during power
12 13 14 15 16 17 18
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN54ABT5402A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT5402A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE1
L
OE2
L
D
L
L
H
Z
Z
L
L
H
X
X
H
X
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
†
logic symbol
logic diagram (positive logic)
14
OE1
&
14
15
OE1
EN
OE2
15
OE2
28
1
D1
Y1
28
27
26
25
24
23
22
20
19
18
17
16
1
2
D1
D2
Y1
1
Y2
3
D3
Y3
To Eleven Other Channels
4
D4
Y4
5
D5
Y5
6
D6
Y6
8
D7
Y7
9
D8
Y8
10
11
12
13
D9
Y9
D10
D11
D12
Y10
Y11
Y12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DW and JT packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT5402A SN74ABT5402A
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–12
12
–12
12
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT5402A SN74ABT5402A
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –1 mA
= –1 mA
= –3 mA
= –12 mA
= 8 mA
3.35
3.85
3.7
4.2
3.3
3.8
3
3.35
3.85
3.1
OH
OH
OH
OH
OL
OL
V
OH
V
= 4.5 V
= 4.5 V
CC
CC
2.6
2.6
0.8
0.65
0.8
V
V
V
V
OL
= 12 mA
100
mV
µA
µA
µA
µA
hys
I
I
I
I
V
V
V
V
= 5.5 V, V = V
I
or GND
±1
10
±1
10
±1
10
I
CC
CC
CC
CC
CC
CC
= 5.5 V,
= 5.5 V,
= 0,
V
O
= 2.7 V
OZH
OZL
off
V
O
= 0.5 V
–10
±100
–10
–10
±100
V or V ≤ 4.5 V
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
50
50
50
µA
CEX
O
I
I
V
= 5.5 V,
= 5.5 V,
V
V
= 2.5 V
= 0
–25
–50
–45
–100
–200
50
–25
–50
–100
–200
50
–25
–50
–100
–200
50
mA
mA
µA
O
CC
CC
O
‡
V
OS
O
Outputs high
Outputs low
5
39
1
V
I
= 5.5 V,
= 0,
CC
O
I
48
48
48
mA
µA
CC
V = V
I
or GND
CC
Outputs disabled
50
50
50
V
= 5.5 V, One
CC
Outputs enabled
Outputs disabled
1.5
0.05
1.5
1.5
0.05
1.5
1.5
0.05
1.5
input at 3.4 V,
Other inputs at
Data inputs
§
mA
∆I
CC
V
CC
or GND
Control
inputs
V
CC
= 5.5 V, One input at 3.4 V,
or GND
Other inputs at V
CC
V = 2.5 V or 0.5 V
C
C
3
8
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT5402A SN74ABT5402A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2
TYP
4.5
3.7
5.7
4.4
3.6
4.2
MAX
5.2
5
MIN
2
MAX
6.3
5.7
8.8
7.6
5.5
7.4
MIN
2
MAX
6.2
5.6
8.7
7.5
5.2
6.9
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Y
Y
Y
ns
ns
ns
1.5
2.5
2
1.5
2.5
2
1.5
2.5
2
7.6
6.3
4.4
5.4
OE
OE
1.5
1.5
1.5
1.5
1.5
1.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT5402A, SN74ABT5402A
12-BIT LINE/MEMORY DRIVERS
WITH 3-STATE OUTPUTS
SCBS660B – FEBRUARY 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
S1
500 Ω
Open
GND
From Output
Under Test
TEST
S1
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
(see Note A)
/t
Open
PHZ PZH
LOAD CIRCUIT
Timing Input
3 V
0 V
1.5 V
t
t
h
su
3 V
0 V
Data Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
t
Input
1.5 V
1.5 V
0 V
t
PZL
t
t
PHL
PLH
Output
Waveform 1
S1 at 7 V
PLZ
1.5 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
(see Note B)
OL
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明