SN74ABTH16245DLG4 [TI]
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 16位总线收发器具有三态输出
| 型号： | SN74ABTH16245DLG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABTH16245, SN74ABTH16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS662I – MARCH 1996 – REVISED MARCH 1999
SN54ABTH16245 . . . WD PACKAGE
SN74ABTH16245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
Typical V
(Output Ground Bounce) < 1 V
2
OLP
at V
= 5 V, T = 25°C
3
CC
A
4
High-Impedance State During Power Up
and Power Down
5
6
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
Flow-Through Architecture Optimizes PCB
Layout
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
2DIR
description
The ’ABTH16245 devices are 16-bit noninverting
3-state transceivers that provide synchronous
two-way communication between data buses.
The control-function implementation minimizes
external timing requirements.
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the devices so that the buses are effectively
isolated.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH16245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16245 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH16245, SN74ABTH16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS662I – MARCH 1996 – REVISED MARCH 1999
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
DIR
L
OE
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
†
logic symbol
48
1
G3
1OE
1DIR
3 EN1 [BA]
3 EN2 [AB]
25
24
G6
2OE
2DIR
6 EN4 [BA]
6 EN5 [AB]
47
2
1
1A1
1B1
2
46
44
43
41
40
38
37
36
3
5
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
6
8
9
11
12
13
4
5
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH16245, SN74ABTH16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS662I – MARCH 1996 – REVISED MARCH 1999
logic diagram (positive logic)
24
36
1
2DIR
2A1
1DIR
48
25
1OE
1B1
2OE
47
1A1
13
2
2B1
To Seven Other Channels
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABTH16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54ABTH16245 SN74ABTH16245
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
10
10
T
–55
125
–40
85
A
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH16245, SN74ABTH16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS662I – MARCH 1996 – REVISED MARCH 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABTH16245 SN74ABTH16245
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
hys
Control
inputs
±1
±1
±1
I
V
V
= 5.5 V,
= 4.5 V
V = V
or GND
µA
I
CC
I
CC
A or B ports
±100
±100
±100
V = 0.8 V
I
100
100
100
I
I
µA
µA
µA
I(hold)
CC
V = 2 V
I
–100
–100
–100
V
V
V
V
V
= 0 to 1.9 V
= 0 to 2.1 V
= 1.9 V to 0
= 2.1 V to 0
= 0,
±50**
±50
±50**
±50**
CC
CC
CC
CC
CC
CC
V
= 0.5 V to 2.7 V,
O
OZPU
OE = X
±50
±50**
±50
V
= 0.5 V to 2.7 V,
O
I
I
I
I
OZPD
OE = X
±50
V or V ≤ 4.5 V
I
±100
±100
µA
µA
off
O
V
V
= 5.5 V,
= 5.5 V
Outputs high
= 2.5 V
50
50
50
CEX
O
‡
V
CC
= 5.5 V,
V
O
–50
–100
–180
2
–50
–180
2
–50
–180
2
mA
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
32
2
32
2
32
2
mA
mA
CC
V = V
I
or GND
CC
Outputs disabled
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
§
1.5
1.5
1.5
∆I
CC
or GND
CC
Control
inputs
C
C
V = 2.5 V or 0.5 V
3
6
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH16245, SN74ABTH16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS662I – MARCH 1996 – REVISED MARCH 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABTH16245
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
2.2
MIN
MAX
MIN
1
MAX
3.6
3.8
5.2
6.1
6.7
4.7
t
t
t
t
t
t
0.5
0.5
0.8
0.9
1.3
1.4
4.1
4.4
6.4
6.5
7.9
5.6
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
OE
B or A
B or A
B or A
ns
ns
ns
1
2.3
1
3.6
1
3.7
2
4.4
OE
1.5
3.3
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABTH16245
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
2.2
MIN
MAX
MIN
1
MAX
3.4
3.7
5.2
5.4
5.8
4.7
t
t
t
t
t
t
1
1
3.9
4.2
6.3
6.4
6.3
5.2
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
B or A
B or A
B or A
ns
ns
ns
1
2.3
1
3.6
1
OE
OE
1
3.7
1
2
4.4
2
1.5
3.3
1.5
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH16245, SN74ABTH16245
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS662I – MARCH 1996 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
PLZ
PLH
PHL
PHL
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
Output
1.5 V
1.5 V
1.5 V
t
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PHZ
PLH
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9762501QXA
ACTIVE
ACTIVE
CFP
WD
48
48
1
TBD
A42 SNPB
N / A for Pkg Type
74ABTH16245DGGRE4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74ABTH16245DGVRE4
74ABTH16245DLRG4
SN74ABTH16245DGGR
SN74ABTH16245DGVR
SN74ABTH16245DL
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TVSOP
SSOP
TSSOP
TVSOP
SSOP
SSOP
SSOP
CFP
DGV
DL
48
48
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ABTH16245DLG4
SN74ABTH16245DLR
SNJ54ABTH16245WD
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WD
1
TBD
A42 SNPB
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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