SN74AC245DWRG4 [TI]

Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85;
SN74AC245DWRG4
型号: SN74AC245DWRG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Octal Bus Transceivers With 3-State Outputs 20-SOIC -40 to 85

光电二极管 逻辑集成电路
文件: 总18页 (文件大小:702K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢉ ꢅꢊꢄꢋ ꢌꢍꢀ ꢊ ꢎꢄꢁꢀꢅ ꢏ ꢐꢑ ꢏ ꢎ  
ꢒ ꢐꢊ ꢓ ꢔ ꢕꢀꢊꢄꢊ ꢏ ꢉ ꢍꢊ ꢖ ꢍꢊ  
SCAS461F − FEBRUARY 1995 − REVISED OCTOBER 2003  
SN54AC245 . . . J OR W PACKAGE  
SN74AC245 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
2-V to 6-V V  
Operation  
CC  
Inputs Accept Voltages to 6 V  
Max t of 7 ns at 5 V  
pd  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
V
CC  
19 OE  
1
2
3
4
5
6
7
8
9
10  
20  
description/ordering information  
18  
17  
16  
15  
14  
13  
12  
11  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
The ’AC245 octal bus transceivers are designed  
for asynchronous two-way communication  
between data buses. The control-function  
implementation minimizes external timing  
requirements.  
When the output-enable (OE) is low, the device  
passes noninverted data from the A bus to the B  
bus or from the B bus to the A bus, depending on  
the logic level at the direction control (DIR) input.  
A high on OE disables the device so that the buses  
are effectively isolated.  
A8  
GND  
SN54AC245 . . . FK PACKAGE  
(TOP VIEW)  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
3
2
1
20 19  
18  
B1  
B2  
B3  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15 B4  
14 B5  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AC245N  
SN74AC245N  
Tube  
SN74AC245DW  
SN74AC245DWR  
SN74AC245NSR  
SN74AC245DBR  
SN74AC245PW  
SN74AC245PWR  
SNJ54AC245J  
SOIC − DW  
AC245  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AC245  
AC245  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
AC245  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AC245J  
SNJ54AC245W  
SNJ54AC245FK  
Tube  
SNJ54AC245W  
SNJ54AC245FK  
−55°C to 125°C  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢉ ꢙ ꢤ ꢜ ꢛꢧ ꢢꢡ ꢟꢠ ꢡꢛ ꢝꢤ ꢦꢘ ꢞꢙ ꢟ ꢟꢛ ꢮꢐ ꢋꢕ ꢖꢎ ꢯ ꢕꢔꢰꢂ ꢔꢂꢇ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢙꢦ ꢣꢠꢠ ꢛ ꢟꢩꢣ ꢜ ꢫꢘ ꢠꢣ ꢙ ꢛꢟꢣ ꢧꢨ ꢉ ꢙ ꢞꢦ ꢦ ꢛ ꢟꢩꢣ ꢜ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢠ ꢇ ꢤꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛ ꢙ  
ꢛꢟ  
ꢦꢬ  
ꢙꢡ  
ꢧꢣ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢃ ꢂꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢆ ꢃ ꢂ  
ꢉꢅ ꢊꢄ ꢋ ꢌ ꢍ ꢀ ꢊ ꢎꢄ ꢁꢀ ꢅꢏ ꢐ ꢑꢏ ꢎꢀ  
ꢒꢐ ꢊ ꢓ ꢔ ꢕꢀꢊꢄꢊ ꢏ ꢉꢍꢊ ꢖꢍ ꢊꢀ  
SCAS461F − FEBRUARY 1995 − REVISED OCTOBER 2003  
FUNCTION TABLE  
INPUTS  
OPERATION  
DIR  
OE  
L
L
H
L
H
X
B data to A bus  
A data to B bus  
Isolation  
logic diagram (positive logic)  
1
DIR  
19  
18  
OE  
B1  
2
A1  
To Seven Other Channels  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
+ 0.5 V  
I
CC  
CC  
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
IK  
I
I
CC  
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous current through V  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA  
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W  
JA  
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W  
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
2
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ꢉ ꢅꢊꢄꢋ ꢌꢍꢀ ꢊ ꢎꢄꢁꢀꢅ ꢏ ꢐꢑ ꢏ ꢎ  
ꢒ ꢐꢊ ꢓ ꢔ ꢕꢀꢊꢄꢊ ꢏ ꢉ ꢍꢊ ꢖ ꢍꢊ  
SCAS461F − FEBRUARY 1995 − REVISED OCTOBER 2003  
recommended operating conditions (see Note 3)  
SN54AC245  
SN74AC245  
UNIT  
MIN  
2
MAX  
MIN  
2
MAX  
V
V
Supply voltage  
6
6
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 3 V  
2.1  
2.1  
= 4.5 V  
= 5.5 V  
= 3 V  
3.15  
3.85  
3.15  
3.85  
High-level input voltage  
V
V
IH  
0.9  
1.35  
1.65  
0.9  
1.35  
1.65  
= 4.5 V  
= 5.5 V  
V
IL  
Low-level input voltage  
V
V
Input voltage  
0
0
V
V
0
0
V
V
V
V
I
CC  
CC  
Output voltage  
O
CC  
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 3 V  
−12  
−24  
−24  
12  
−12  
−24  
−24  
12  
= 4.5 V  
= 5.5 V  
= 3 V  
I
High-level output current  
Low-level output current  
mA  
mA  
OH  
= 4.5 V  
= 5.5 V  
24  
24  
I
OL  
24  
24  
Dt/Dv  
Input transition rise or fall rate  
Operating free-air temperature  
8
8
ns/V  
T
A
−55  
125  
−40  
85  
°C  
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢃ ꢂꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢆ ꢃ ꢂ  
ꢉꢅ ꢊꢄ ꢋ ꢌ ꢍ ꢀ ꢊ ꢎꢄ ꢁꢀ ꢅꢏ ꢐ ꢑꢏ ꢎꢀ  
ꢒꢐ ꢊ ꢓ ꢔ ꢕꢀꢊꢄꢊ ꢏ ꢉꢍꢊ ꢖꢍ ꢊꢀ  
SCAS461F − FEBRUARY 1995 − REVISED OCTOBER 2003  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
SN54AC245  
SN74AC245  
PARAMETER  
TEST CONDITIONS  
V
UNIT  
CC  
MIN  
2.9  
TYP  
MAX  
MIN  
2.9  
4.4  
5.4  
2.4  
3.7  
4.7  
3.85  
MAX  
MIN  
2.9  
MAX  
3 V  
4.5 V  
5.5 V  
3 V  
4.4  
4.4  
I
= −50 mA  
OH  
5.4  
5.4  
I
I
= −12 mA  
= −24 mA  
2.56  
3.86  
4.86  
2.46  
3.76  
4.76  
OH  
V
OH  
V
4.5 V  
5.5 V  
5.5 V  
5.5 V  
3 V  
OH  
I
I
= −50 mA  
OH  
= −75 mA  
3.85  
OH  
0.002  
0.001  
0.001  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
4.5 V  
5.5 V  
3 V  
I
= 50 mA  
OL  
0.1  
0.1  
0.1  
I
I
= 12 mA  
= 24 mA  
0.36  
0.36  
0.36  
0.5  
0.44  
0.44  
0.44  
OL  
V
OL  
V
4.5 V  
5.5 V  
5.5 V  
5.5 V  
0.5  
OL  
0.5  
I
I
= 50 mA  
1.65  
OL  
= 75 mA  
1.65  
1
OL  
A or B ports  
0.1  
0.1  
1
1
I
V = V  
CC  
or GND  
or GND,  
5.5 V  
5.5 V  
mA  
mA  
I
I
OE or DIR  
1
V
= V  
CC  
V (OE) = V or V  
IL IH  
O
I
I
I
0.5  
4
10  
80  
5
OZ  
V = V  
or GND,  
or GND  
I = 0  
O
5.5 V  
5 V  
40  
mA  
pF  
pF  
CC  
I
CC  
C
C
V = V  
4.5  
15  
i
I
CC  
V
= V  
or GND  
5 V  
io  
O CC  
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.  
For I/O ports, the parameter I includes the input leakage current.  
OZ  
switching characteristics over recommended operating free-air temperature range,  
= 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1)  
V
CC  
T = 25°C  
A
SN54AC245  
SN74AC245  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
ns  
MIN  
1.5  
1.5  
2.5  
2.5  
2
TYP  
5
MAX  
8.5  
MIN  
1
MAX  
11.5  
10  
MIN  
1
MAX  
9
t
t
PLH  
PHL  
PZH  
A or B  
OE  
B or A  
A or B  
A or B  
5
8.5  
1
1
9
t
7
11.5  
12  
1
13.5  
14.5  
13.5  
14  
2
12.5  
13.5  
12.5  
13  
ns  
t
7.5  
6.5  
7
1
2
PZL  
t
12  
1
1
PHZ  
ns  
OE  
t
2
11.5  
1
1.5  
PLZ  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢉ ꢅꢊꢄꢋ ꢌꢍꢀ ꢊ ꢎꢄꢁꢀꢅ ꢏ ꢐꢑ ꢏ ꢎ  
SCAS461F − FEBRUARY 1995 − REVISED OCTOBER 2003  
switching characteristics over recommended operating free-air temperature range,  
= 5 V " 5 V (unless otherwise noted) (see Figure 1)  
V
CC  
T
A
= 25°C  
TYP  
3.5  
SN54AC245  
SN74AC245  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
ns  
MIN  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
MAX  
6.5  
6
MIN  
1
MAX  
8.5  
MIN  
1
MAX  
7
t
t
PLH  
PHL  
PZH  
A or B  
OE  
B or A  
A or B  
A or B  
3.5  
1
7.5  
1
7
t
5
8.5  
9
1
10  
1
9
ns  
t
5.5  
1
10.5  
10.5  
10.5  
1
9.5  
10  
10  
PZL  
t
5.5  
9
1
1
PHZ  
ns  
OE  
t
5.5  
9
1
1
PLZ  
operating characteristics, V  
= 5 V, T = 25°C  
A
CC  
PARAMETER  
TEST CONDITIONS  
TYP  
UNIT  
C
Power dissipation capacitance per transceiver  
C
= 50 pF,  
L
f = 1 MHz  
45  
pF  
pd  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
TEST  
S1  
S1  
t
/t  
Open  
500 Ω  
Open  
PLH PHL  
From Output  
Under Test  
t
/t  
2 × V  
CC  
PLZ PZL  
t
/t  
Open  
PHZ PZH  
C
= 50 pF  
L
500 Ω  
(see Note A)  
LOAD CIRCUIT  
50%  
Output  
Control  
(low-level  
enabling)  
V
CC  
V
50% V  
CC  
50% V  
CC  
CC  
Input  
50%  
0 V  
0 V  
PHL  
t
t
PLZ  
PZL  
t
t
PLH  
Output  
Waveform 1  
V  
CC  
V
OH  
50% V  
CC  
In-Phase  
Output  
V
OL  
+ 0.3 V  
S1 at 2 × V  
(see Note B)  
50% V  
CC  
50% V  
CC  
CC  
V
OL  
V
OL  
t
t
PZH  
PHZ  
− 0.3 V  
t
t
PLH  
PHL  
Output  
Waveform 2  
S1 at Open  
(see Note B)  
V
OH  
V
OH  
V
OH  
Out-of-Phase  
Output  
50% V  
CC  
50% V  
CC  
50% V  
CC  
0 V  
V
OL  
VOLTAGE WAVEFORMS  
VOLTAGE WAVEFORMS  
C includes probe and jig capacitance.  
L
NOTES: A.  
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z = 50 , t v 2.5 ns, t v 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-87758012A  
5962-8775801RA  
5962-8775801SA  
5962-8775801VRA  
5962-8775801VSA  
SN74AC245DBLE  
SN74AC245DBR  
ACTIVE  
ACTIVE  
FK  
J
20  
20  
20  
20  
20  
20  
20  
1
1
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
ACTIVE  
W
J
Call TI  
A42  
ACTIVE  
CDIP  
CFP  
ACTIVE  
W
DB  
DB  
Call TI  
Call TI  
OBSOLETE  
ACTIVE  
SSOP  
SSOP  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AC245DBRE4  
SN74AC245DBRG4  
SN74AC245DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SO  
DB  
DB  
DW  
DW  
DW  
DW  
DW  
DW  
N
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AC245DWE4  
SN74AC245DWG4  
SN74AC245DWR  
SN74AC245DWRE4  
SN74AC245DWRG4  
SN74AC245N  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN74AC245NE4  
N
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN74AC245NSR  
SN74AC245NSRE4  
SN74AC245NSRG4  
SN74AC245PW  
NS  
NS  
NS  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AC245PWE4  
SN74AC245PWG4  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AC245PWLE  
SN74AC245PWR  
OBSOLETE TSSOP  
PW  
PW  
20  
20  
TBD  
Call TI  
Call TI  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
LCCC  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AC245PWRE4  
SN74AC245PWRG4  
SNJ54AC245FK  
PW  
PW  
FK  
20  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
1
TBD  
POST-PLATE N / A for Pkg Type  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
15-Oct-2009  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CFP  
Drawing  
SNJ54AC245J  
SNJ54AC245W  
ACTIVE  
ACTIVE  
J
20  
20  
1
1
TBD  
TBD  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SN54AC245, SN54AC245-SP, SN74AC245 :  
Enhanced Product: SN74AC245-EP  
NOTE: Qualified Version Definitions:  
Enhanced Product - Supports Defense, Aerospace and Medical Applications  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Aug-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
SN74AC245DBR  
SN74AC245DWR  
SN74AC245NSR  
SN74AC245PWR  
SSOP  
SOIC  
SO  
DB  
DW  
NS  
20  
20  
20  
20  
2000  
2000  
2000  
2000  
330.0  
330.0  
330.0  
330.0  
16.4  
24.4  
24.4  
16.4  
8.2  
10.8  
8.2  
7.5  
13.0  
13.0  
7.1  
2.5  
2.7  
2.5  
1.6  
12.0  
12.0  
12.0  
8.0  
16.0  
24.0  
24.0  
16.0  
Q1  
Q1  
Q1  
Q1  
TSSOP  
PW  
6.95  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Aug-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74AC245DBR  
SN74AC245DWR  
SN74AC245NSR  
SN74AC245PWR  
SSOP  
SOIC  
SO  
DB  
DW  
NS  
20  
20  
20  
20  
2000  
2000  
2000  
2000  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
33.0  
41.0  
41.0  
33.0  
TSSOP  
PW  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
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