SN74ACT1284PW [TI]

7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS; 具有三态输出的7位总线接口


型号：	SN74ACT1284PW
厂家：	TEXAS INSTRUMENTS
描述：	7-BIT BUS INTERFACES WITH 3-STATE OUTPUTS 具有三态输出的7位总线接口输出元件
文件：	总5页 (文件大小：96K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN54ACT1284, SN74ACT1284

7-BIT BUS INTERFACES

WITH 3-STATE OUTPUTS

SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996

SN54ACT1284 . . . J OR W PACKAGE

SN74ACT1284 . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

3-State Outputs Directly Drive Bus Lines

Flow-Through Architecture Optimizes PCB

Layout

Center-Pin V

Minimize High-Speed Switching Noise

and GND Configurations

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

GND

Designed for the IEEE 1284-I (Level 1 Type)

and IEEE 1284-II (Level 2 Type) Electrical

Specifications

13 B6

12 B7

Package Options Include Plastic

DIR

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW), and

DIP (N) Packages, Ceramic Chip Carriers

(FK), Flat (W), and DIP (J) Packages

FK PACKAGE

(TOP VIEW)

description

1 20 19

The ’ACT1284 are designed for asynchronous

two-way communication between data buses.

The control function minimizes external timing

requirements.

GND

The devices allow data transmission in either the

A-to-B or the B-to-A direction for bits 1, 2, 3, and

4, depending on the logic level at the

direction-control (DIR) input. Bits 5, 6, and 7,

however, always transmit in the A-to-B direction.

9 10 11 12 13

The output drive for each mode is determined by the high drive (HD) control pin. When HD is high, the high drive

is delivered by the totem-pole configuration, and when HD is low, the outputs are open drain. This meets the

drive requirements as specified in the IEEE 1284-I (level 1 type) and the IEEE 1284-II (level 2 type) parallel

peripheral-interface specification.

The SN54ACT1284 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ACT1284 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUT

MODE

DIR

Open drain

Totem pole

Open drain

Totem pole

A to B: Bits 5, 6, 7

B to A: Bits 1, 2, 3, 4

B to A: Bits 1, 2, 3, 4 and A to B: Bits 5, 6, 7

A to B: Bits 1, 2, 3, 4, 5, 6, 7

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT1284, SN74ACT1284

7-BIT BUS INTERFACES

WITH 3-STATE OUTPUTS

SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996

logic diagram (positive logic)

DIR

A1, A2, A3, A4

B1, B2, B3, B4

B5, B6, B7

A5, A6, A7

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

B-port input and output voltage range, V and V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . –2 V to 7 V

A-port input and output voltage range, V and V (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V

Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Output clamp current, I

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA

Continuous current through V

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The ac input voltage pulsewidth is limited to 20 ns if the input voltage goes more negative than –0.5 V.

3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT1284, SN74ACT1284

7-BIT BUS INTERFACES

WITH 3-STATE OUTPUTS

SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996

recommended operating conditions

SN54ACT1284 SN74ACT1284

UNIT

MIN

4.7

MAX

MIN

4.7

MAX

Supply voltage

5.5

High-level input voltage

Low-level input voltage

Input voltage

0.8

5.5

Open drain output voltage

HD low

B port, HD high

A port

–14

–4

–14

–4

High-level output current

B port

Low-level output current

A port

Operating free-air temperature

–55

125

°C

electrical characteristics over recommended ranges of operating free-air temperature and supply

voltage (unless otherwise noted)

SN54ACT1284

SN74ACT1284

†

PARAMETER

TEST CONDITIONS

UNIT

MIN

0.4

0.2

2.4

TYP

MAX

MIN

0.4

0.2

2.4

TYP

MAX

5 V

Input

hysteresis

– V for all inputs

IT–

hys

IT+

4.7 V

B port

= –14 mA

MIN

to MAX

= –50 µA

–0.2

3.7

–0.2

3.7

A port

= –4 mA

=14 mA

= 50 µA

= 4 mA

4.7 V

B port

A port

0.4

0.2

0.4

0.2

4.7 V

0.4

V = V

or GND

5.5 V

0 V

±1

µA

Ω

= V or GND

‡

A or B ports

B port

±20

±100

1.5

±20

±100

1.5

V or V ≤ 7 V

OFF

V = V

or GND,

or GND

= 0

5.5 V

5 V

Control inputs V = V

A or B ports

B port

= V

or GND

5 V

= –20 mA,

I = –50 mA

5 V

†

‡

For I/O ports, the parameter I

includes the input leakage current I .

For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted) (see Figure 1)

SN54ACT1284 SN74ACT1284

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

MAX

MIN

MAX

PLH

Totem pole

A or B

B or A

V/ns

PHL

Totem pole

Open drain

B output

0.05

0.4

0.05

0.4

(EN)

(DIS)

t , t

r f

120

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ACT1284, SN74ACT1284

7-BIT BUS INTERFACES

WITH 3-STATE OUTPUTS

SCAS459B – NOVEMBER 1994 – REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION

From B Output

Under Test

3 V

0 V

Input

(see Note C)

62 Ω

= 50 pF

1.5 V

(see Note A)

TP1

Output

(see Note D)

PHL

Sink Load

PLH

PHL

33 Ω

+ 1.4 V

– 1.4 V

Source Load

PLH

62 Ω

VOLTAGE WAVEFORMS MEASURED AT TP1

PROPAGATION DELAY TIMES (A to B)

= 50 pF

(see Note A)

A-TO-B LOAD (totem pole)

3 V

0 V

Input

(see Note F)

1.5 V

2 V

0.8 V

2 V

0.8 V

TP1

500 Ω

(see Note E)

From B Output

VOLTAGE WAVEFORMS MEASURED AT TP1 (B SIDE)

= 50 pF

(see Note A)

A-TO-B LOAD (open drain)

3 V

0 V

Input

(see Note F)

1.5 V

From A Output

Under Test

PHL

PLH

= 50 pF

500 Ω

Output

50% V

(see Note A)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (B to A)

B-TO-A LOAD (totem pole)

NOTES: A. CL includes probe and jig capacitance.

B. The outputs are measured one at a time with one transition per measurement.

C. Input rise and fall times are 3 ns, 150 ns < pulsewidth <10 µs for both low-to-high and high-to-low transitions.

D. Slew rate is defined as 10% and 90% of the transition times.

E. Rise and fall times, open drain, are <120 ns.

F. Input rise and fall times are 3 ns.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

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safeguards must be provided by the customer to minimize inherent or procedural hazards.

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semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

SN74ACT1284PW [TI]

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