SN74ACT2229DWR [TI]
256 x 1 x 2 dual independent synchronous FIFO memories 28-SOIC -40 to 85;
| 型号： | SN74ACT2229DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 256 x 1 x 2 dual independent synchronous FIFO memories 28-SOIC -40 to 85 |
| 文件： | 总13页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
DW PACKAGE
(TOP VIEW)
Dual Independent FIFOs Organized as:
64 Words by 1 Bit Each – SN74ACT2227
256 Words by 1 Bit Each – SN74ACT2229
1HF
1AF/AE
1WRTCLK
1WRTEN
1IR
1OE
1RDCLK
1
28
27
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident on Each
FIFO
2
3
26 1RDEN
25 1OR
24 1Q
4
Input-Ready Flags Synchronized to Write
Clocks
5
6
23
22
21
20
19
18
17
16
15
1D
GND
GND
2RESET
Output-Ready Flags Synchronized to Read
Clocks
7
V
V
CC
CC
8
9
1RESET
2Q
2D
2IR
2WRTEN
2WRTCLK
2AF/AE
2HF
Half-Full and Almost-Full/Almost-Empty
Flags
10
11
12
13
14
2OR
Support Clock Frequencies up to 60 MHz
Access Times of 9 ns
2RDEN
2RDCLK
2OE
3-State Data Outputs
Low-Power Advanced CMOS Technology
Packaged in 28-Pin SOIC Package
description
The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering
applicationsincluding elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip
is arranged as 64 × 1 (SN74ACT2227) or 256 × 1 (SN74ACT2229) and has control signals and status flags for
independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),
half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).
Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input
when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.
Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when
the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read
and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the
high-impedance state when its output-enable (1OE or 2OE) input is low.
Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or
2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock
(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written
and read asynchronously.
A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half
the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits
are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data
output is not stored in the FIFO.
The SN74ACT2227 and SN74ACT2229 are characterized for operation from –40°C to 85°C.
For more information on this device family, see the application report FIFOs With a Word Width of One Bit
(literature number SCAA006).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
†
logic symbols
Φ
FIFO 64 × 1
SN74ACT2227
9
1RESET
3
RESET
5
1
IN RDY
1IR
1WRTCLK
WRTCLK
HALF FULL
ALMOST FULL/EMPTY
OUT RDY
1HF
4
1WRTEN
WRTEN
RDCLK
2
1AF/AE
1OR
27
25
1RDCLK
28
1OE
EN1
26
1RDEN
RDEN
6
24
1
1D
1Q
23
2RESET
RESET
17
19
15
16
11
2WRTCLK
WRTCLK
WRTEN
2IR
IN RDY
HALF FULL
18
2WRTEN
2HF
13
2RDCLK
RDCLK
EN2
2AF/AE
2OR
ALMOST FULL/EMPTY
OUT RDY
14
2OE
12
2RDEN
RDEN
20
10
2D
2Q
2
Φ
FIFO 256 × 1
SN74ACT2229
9
1RESET
3
RESET
5
1
IN RDY
HALF FULL
1IR
1WRTCLK
WRTCLK
WRTEN
RDCLK
1HF
4
1WRTEN
2
ALMOST FULL/EMPTY
OUT RDY
1AF/AE
1OR
27
25
1RDCLK
28
1OE
EN1
26
1RDEN
RDEN
6
24
1
1D
1Q
23
2RESET
RESET
17
19
15
16
11
2WRTCLK
WRTCLK
WRTEN
2IR
IN RDY
HALF FULL
18
2WRTEN
2HF
13
2RDCLK
RDCLK
EN2
2AF/AE
2OR
ALMOST FULL/EMPTY
OUT RDY
14
2OE
12
2RDEN
RDEN
20
10
2D
2
2Q
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
SN74ACT2227 functional block diagram (each FIFO)
OE
D
Location 1
Location 2
RDCLK
RDEN
Synchronous
Read Control
Read
Pointer
Dual-Port
SRAM
64 × 1
WRTCLK
WRTEN
Synchronous
Write Control
Write
Pointer
Location 63
Location 64
Register
Q
AF/AE
HF
Status
Reset Logic
IR
RESET
OR
SN74ACT2229 functional block diagram (each FIFO)
OE
D
Location 1
Location 2
RDCLK
RDEN
Synchronous
Read Control
Read
Pointer
Dual-Port
SRAM
256 × 1
WRTCLK
WRTEN
Synchronous
Write Control
Write
Pointer
Location 255
Location 256
Register
Q
AF/AE
HF
Status
Reset Logic
IR
RESET
OR
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1AF/AE
2AF/AE
2
16
Almost-full/almost-empty flag. AF/AE is high when the memory is eight locations or fewer from a full or empty
state. AF/AE is set high after reset.
O
I
1D
2D
6
20
Data input
Ground
GND
7, 8
1HF
2HF
1
15
Half-fullflag. HFishighwhenthenumberofbitsstoredinmemoryisgreaterthanorequaltohalftheFIFOdepth.
HF is set low after reset.
O
O
I
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full
and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of
WRTCLK after reset.
1IR
2IR
5
19
1OE
2OE
28
14
Output enable. The data output of a FIFO is active when OE is high and in the high-impedance state when OE
is low.
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is
empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during
reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory.
1OR
2OR
25
11
O
O
I
1Q
2Q
24
10
Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK.
OR for the FIFO is asserted high to indicate ready data.
Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-high transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is
synchronous with the low-to-high transition of RDCLK.
1RDCLK
2RDCLK
27
13
1RDEN
2RDEN
26
12
Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-to-high
transition of RDCLK.
I
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK
must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must
be reset after power up.
1RESET
2RESET
9
23
I
V
CC
21, 22
Supply voltage
Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A
low-to-hightransition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous with
the low-to-high transition of WRTCLK.
1WRTCLK
2WRTCLK
3
17
I
I
1WRTEN
2WRTEN
4
18
Writeenable. When WRTEN and IR are high, data is written to the FIFO on a low-to-high transition of WRTCLK.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
RESET
WRTCLK
WRTEN
D
1
2
3
4
1
2
Don’t Care
Don’t Care
RDCLK
RDEN
OE
1
2
3
4
Don’t Care
Don’t Care
Q
OR
Don’t Care
AF/AE
HF
Don’t Care
Don’t Care
IR
Don’t Care
Figure 1. FIFO Reset
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
1
0
RESET
WRTCLK
1
0
WRTEN
D
B1
B2
1
B3
2
B4
3
B10
A
B
C
RDCLK
RDEN
1
0
1
0
OE
Q
B1
OR
AF/AE
HF
IR
DATA BIT NUMBER BASED ON FIFO DEPTH
DATA BIT
DEVICE
A
B
C
SN74ACT2227
SN74ACT2229
B33
B57
B65
B129 B249 B257
Figure 2. FIFO Write
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
1
0
RESET
WRTCLK
1
2
WRTEN
D
F
RDCLK
RDEN
OE
1
0
B1
B2
B3
B9
B10
A
B
C
D
E
F
Q
OR
AF/AE
HF
IR
DATA BIT NUMBER BASED ON FIFO DEPTH
DATA BIT
DEVICE
A
B
C
D
E
F
SN74ACT2227
SN74ACT2229
B33
B34
B56
B57
B64
B65
B129 B130 B248 B249 B256 B257
Figure 3. FIFO Read
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
OK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
CC
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded provided that the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
V
IH
0.8
–8
16
8
V
IL
I
Q outputs, flags
Q outputs
Flags
mA
OH
I
Low-level output current
mA
OL
T
A
Operating free-air temperature
–40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
= – 8 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
I
2.4
V
OH
CC
CC
CC
CC
CC
OH
OL
OL
Flags
= 8 mA
0.5
0.5
±5
±5
400
1
V
OL
Q outputs
= 16 mA
I
I
I
V = V
or 0
µA
µA
µA
mA
pF
pF
I
I
CC
= V or 0
CC
V
OZ
CC
O
V = V
I
– 0.2 V or 0
CC
= 5.5 V,
§
∆I
CC
V
One input at 3.4 V,
f = 1 MHz
Other inputs at V or GND
CC
CC
V = 0,
C
C
4
8
i
I
V
O
= 0,
f = 1 MHz
o
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 1 through 4)
MIN
MAX
UNIT
f
t
Clock frequency
Pulse duration
60
MHz
clock
1WRTCLK, 2WRTCLK high or low
5
5
ns
ns
w
1RDCLK, 2RDCLK high or low
1D before 1WRTCLK↑ and 2D before 2WRTCLK↑
1WRTEN before 1WRTCLK↑ and 2WRTEN before 2WRTCLK↑
1RDEN before 1RDCLK↑ and 2RDEN before 2RDCLK↑
1RESET low before 1WRTCLK↑ and 2RESET low before 2WRTCLK↑
4.5
4.5
4
t
su
Setup time
Hold time
†
6
†
1RESET low before 1RDCLK↑ and 2RESET low before 2RDCLK↑
1D after 1WRTCLK↑ and 2D after 2WRTCLK↑
6
0
1WRTEN after 1WRTCLK↑ and 2WRTEN after 2WRTCLK↑
1RDEN after 1RDCLK↑ and 2RDEN after 2RDCLK↑
0
t
h
0
ns
†
1RESET low after 1WRTCLK↑ and 2RESET low after 2WRTCLK↑
6
†
1RESET low after 1RDCLK↑ and 2RESET low after 2RDCLK↑
Requirement to count the clock edge as one of at least four needed to reset a FIFO
6
†
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 4)
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
1WRTCLK, 2WRTCLK,
or 1RDCLK, 2RDCLK
f
60
MHz
max
t
t
t
1RDCLK↑, 2RDCLK↑
1WRTCLK↑, 2WRTCLK↑
1RDCLK↑, 2RDCLK↑
1WRTCLK↑, 2WRTCLK↑
1RDCLK↑, 2RDCLK↑
1WRTCLK↑, 2WRTCLK↑
1RDCLK↑, 2RDCLK↑
1Q, 2Q
1IR, 2IR
2
1
1
3
3
2
3
1
1
0
0
9
8
ns
ns
ns
pd
pd
pd
1OR, 2OR
8
14
14
12
14
17
18
8
t
pd
1AF/AE, 2AF/AE
1HF, 2HF
ns
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
PLH
PHL
PLH
PHL
en
1AF/AE, 2AF/AE
1HF, 2HF
1Q, 2Q
1RESET, 2RESET low
1OE, 2OE
1OE, 2OE
1Q, 2Q
8
dis
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
7 V
PARAMETER
S1
S1
t
Open
Closed
Open
Closed
Open
Open
PZH
t
t
t
en
dis
pd
t
500 Ω
PZL
t
PHZ
From Output
Under Test
Test
Point
t
PLZ
PLH
PHL
t
t
C
= 50 pF
500 Ω
L
(see Note A)
LOAD CIRCUIT
t
w
3 V
0 V
Input
1.5 V
1.5 V
3 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
≈ 3.5 V
Output
Waveform 1
S1 at 7 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OH
t
PHZ
t
PLH
t
PZH
t
PHL
V
Output
Waveform 2
S1 at Open
V
OH
V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTE A: C includes probe and jig capacitance.
L
Figure 4. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
TYPICAL CHARACTERISTICS
SINGLE FIFO SUPPLY CURRENT
vs
CLOCK FREQUENCY
40
35
30
25
20
15
10
5
V
CC
= 5.5 V
V
CC
= 5 V
V
CC
= 4.5 V
f = 1/2 f
I
clock
= 75°C
= 0 pF
T
A
C
L
0
0
10
20
30
40
50
60
f
– Clock Frequency – MHz
clock
Figure 5
calculating power dissipation
Data for Figure 5 is taken with one FIFO active and one FIFO idle on the device. The active FIFO has both writes
and reads enabled with its read clock (RDCLK) and write clock (WRTCLK) operating at the rate specified by
f
. The data input rate and data output rate are half the f
rate, and the data output is disconnected. A
clock
clock
close approximation to the total device power can be found by Figure 5, determining the capacitive load on the
data output and determining the number of SN74ACT2227/2229 inputs driven by TTL high levels.
With I
taken from Figure 5, the maximum power dissipation (P ) of one FIFO on the SN74ACT2227 or
T
CC(f)
SN74ACT2229 can be calculated by:
2
P = V
× [I
+ (N × ∆I
× dc)] + (C × V
× f )
T
CC
CC(f)
CC
L
CC o
where:
N
∆I
dc
=
=
=
=
=
number of inputs driven by TTL levels
increase in power-supply current for each input at a TTL high level
duty cycle of inputs at a TTL high level of 3.4 V
output capacitive load
CC
C
L
f
switching frequency of an output
o
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT2227, SN74ACT2229
DUAL 64 × 1, DUAL 256 × 1
FIRST-IN, FIRST-OUT MEMORIES
SCAS220C – JUNE 1992 – REVISED OCTOBER 1997
APPLICATION INFORMATION
An example of concentrating two independent serial-data signals into a single composite data signal with the use of
anSN74ACT2227orSN74ACT2229deviceisshowninFigure6. TheinputdatatotheFIFOssharethesameaverage
(mean) frequency and the mean frequency of the SYS_CLOCK is greater than or equal to the sum of the individual
mean input rates. A single-bit FIFO is needed for each additional input data signal that is time-division multiplexed
into the composite signal.
The FIFO memories provide a buffer to absorb clock jitter generated by the transmission systems of incoming signals
and synchronize the phase-independent inputs to one another. FIFO half-full (HF) flags are used to signal the
multiplexer to start fetching data from the buffers. The state of the flags also can be used to indicate when a FIFO
read should be suppressed to regulate the output flow (pulse-stuffing control). The FIFO almost-full/almost-empty
(AF/AE) flags can be used in place of the half-full flags to reduce transmission delay.
SN74ACT2227
or
SN74ACT2229
SYS_CLOCK
+5 V
1HF
1WRTCLK 1RDCLK
READY_1
Serial
Data
Stream
1WRTEN
1D
1RDEN
1Q
SELECT_1
DATA_1
Composite
Data Stream
Time-Division
Multiplexer
Serial
Data
Stream
2WRTCLK 2RDCLK
2WRTEN
2D
2RDEN
2Q
SELECT_2
DATA_2
2HF
READY_2
Figure 6. Time-Division Multiplexing Using the SN74ACT2227 or SN74ACT2229
12
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