SN74ACT32PWRG4 [TI]
Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85;
| 型号： | SN74ACT32PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总16页 (文件大小：975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀꢁꢊ ꢃꢄ ꢅꢆ ꢇꢈ
ꢋ ꢌꢄꢍꢎ ꢌꢏꢐ ꢑ ꢈ ꢒꢓꢁ ꢏꢌꢆ ꢏꢔ ꢀꢓ ꢆ ꢓꢕꢑ ꢒꢔꢎ ꢖ ꢄꢆꢑ ꢀ
SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003
D
D
4.5-V to 5.5-V V
Operation
D Max t of 10 ns at 5 V
CC
pd
Inputs Accept Voltages to 5.5 V
D Inputs Are TTL-Voltage Compatible
SN54ACT32 . . . J OR W PACKAGE
SN74ACT32 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54ACT32 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2A
2B
V
CC
3
2
1
20 19
18
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
4A
4
5
6
7
8
NC
17
16 4Y
15
NC
2B
NC
3B
2Y
GND
14
8
9 10 11 12 13
NC − No internal connection
description/ordering information
The ’ACT32 devices are quadruple 2-input positive-OR gates. The devices perform the Boolean function
Y = A + B or Y = A • B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74ACT32N
SN74ACT32N
Tube
SN74ACT32D
ACT32
Tape and reel
Tape and reel
Tape and reel
Tube
SN74ACT32DR
SN74ACT32NSR
SN74ACT32DBR
SN74ACT32PW
SN74ACT32PWR
SNJ54ACT32J
SNJ54ACT32W
SNJ54ACT32FK
SOP − NS
ACT32
AD32
−40°C to 85°C
SSOP − DB
TSSOP − PW
AD32
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54ACT32J
SNJ54ACT32W
SNJ54ACT32FK
Tube
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋꢌ ꢄ ꢍꢎ ꢌ ꢏꢐ ꢑ ꢈ ꢒꢓ ꢁ ꢏꢌ ꢆ ꢏ ꢔꢀ ꢓ ꢆꢓ ꢕ ꢑꢒ ꢔꢎ ꢖ ꢄꢆ ꢑꢀ
SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003
logic diagram, each gate (positive logic)
A
B
Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ACT32
SN74ACT32
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
−24
24
−24
24
8
mA
mA
ns/V
°C
OH
OL
∆t/∆v
8
T
−55
125
−40
85
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋ ꢌꢄꢍꢎ ꢌꢏꢐ ꢑ ꢈ ꢒꢓꢁ ꢏꢌꢆ ꢏꢔ ꢀꢓ ꢆ ꢓꢕꢑ ꢒꢔꢎ ꢖ ꢄꢆꢑ ꢀ
SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54ACT32
SN74ACT32
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
I
= −50 µA
OH
5.4
5.4
5.4
3.86
4.86
3.7
3.76
4.76
V
OH
= −24 mA
V
OH
4.7
†
†
I
I
= −50 mA
3.86
OH
= −75 mA
3.85
OH
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
OL
0.36
0.36
0.5
0.44
0.44
V
OL
I
= 24 mA
V
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
1
OL
I
I
V = V
or GND
or GND,
0.1
2
1
µA
µA
I
I
CC
V = V
I = 0
O
40
20
CC
I
CC
One input at 3.4 V,
Other inputs at V
‡
nI
CC
5.5 V
5 V
0.6
2.6
1.6
1.5
mA
pF
or GND
CC
or GND
C
V = V
I CC
i
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range,
= 5 V " 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
6.5
SN54ACT32
MIN MAX
SN74ACT32
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
MAX
MIN
1
MAX
10
t
t
9
9
PLH
A or B
Y
ns
1
6.5
1
10
PHL
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
C
40
pF
pd
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉ ꢀꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋꢌ ꢄ ꢍꢎ ꢌ ꢏꢐ ꢑ ꢈ ꢒꢓ ꢁ ꢏꢌ ꢆ ꢏ ꢔꢀ ꢓ ꢆꢓ ꢕ ꢑꢒ ꢔꢎ ꢖ ꢄꢆ ꢑꢀ
SCAS530C − AUGUST 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
TEST
/t
S1
Input
(see Note B)
1.5 V
1.5 V
t
Open
PLH PHL
t
t
t
PHL
PLH
PHL
2 × V
CC
V
OH
In-Phase
Output
50% V
50% V
S1
50% V
CC
CC
500 Ω
Open
From Output
Under Test
V
OL
t
PLH
C
= 50 pF
L
500 Ω
V
OH
(see Note A)
Out-of-Phase
Output
50% V
CC
CC
V
OL
LOAD CIRCUIT
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74ACT32D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ACT32
SN74ACT32DBLE
SN74ACT32DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AD32
SN74ACT32DG4
SN74ACT32DR
SN74ACT32DRE4
SN74ACT32DRG4
SN74ACT32N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ACT32
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
ACT32
D
Green (RoHS
& no Sb/Br)
ACT32
D
Green (RoHS
& no Sb/Br)
ACT32
N
Pb-Free
(RoHS)
SN74ACT32N
SN74ACT32N
ACT32
SN74ACT32NE4
SN74ACT32NSR
SN74ACT32PW
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
NS
PW
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TSSOP
Green (RoHS
& no Sb/Br)
AD32
SN74ACT32PWLE
SN74ACT32PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AD32
AD32
SN74ACT32PWRG4
ACTIVE
TSSOP
PW
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ACT32DBR
SN74ACT32DR
SN74ACT32NSR
SN74ACT32PWR
SSOP
SOIC
SO
DB
D
14
14
14
14
2000
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
12.4
8.2
6.5
8.2
6.9
6.6
9.0
2.5
2.1
2.5
1.6
12.0
8.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
NS
PW
10.5
5.6
12.0
8.0
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ACT32DBR
SN74ACT32DR
SN74ACT32NSR
SN74ACT32PWR
SSOP
SOIC
SO
DB
D
14
14
14
14
2000
2500
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
35.0
NS
PW
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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