SN74ACT7801FN_技术文档

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SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

• Member of the Texas Instruments

Widebus Family

• Input-Ready, Output-Ready, and Half-Full

Flags

• Independent Asynchronous Inputs and

• Cascadable in Word Width and/or Word

Outputs

Depth

• 1024 Words × 18 Bits

• Fast Access Times of 15 ns With a 50-pF

Load

• Read and Write Operations Can Be

Synchronized to Independent System

Clocks

• High-Output Drive for Direct Bus Interface

• 3-State Outputs

• Programmable Almost-Full/Almost-Empty

• Available in 68-Pin PLCC (FN) or

Space-Saving 80-Pin Shrink Quad Flat

Package (PN)

Flag

FN PACKAGE

(TOP VIEW)

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

60

D14

D13

D12

D11

D10

D9

V

CC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Q14

Q13

GND

Q12

Q11

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

V

CC

D8

GND

D7

D6

D5

D4

D3

D2

D1

Q10

Q9

GND

Q8

Q7

V

CC

Q6

Q5

GND

Q4

D0

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Widebus is a trademark of Texas Instruments Incorporated.

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Copyright  1991, Texas Instruments Incorporated

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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢃ ꢋ ×ꢋ ꢉ ꢇꢋ ꢅ ꢌꢍ ꢅꢎ ꢏꢐ ꢋ ꢑꢒ ꢓ ꢀꢆꢔꢒ ꢁꢕ ꢋ ꢑ ꢒ ꢓꢀ ꢆꢔꢍ ꢖꢆ ꢋꢗ ꢏꢗ ꢍꢓꢘ

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

PN PACKAGE

(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

60

1

NC

GND

Q16

V

NC

Q3

Q2

GND

Q1

Q0

V

HF

CC

2

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

3

4

5

Q17

6

V

CC

7

OR

GND

8

9

V

CC

10

11

12

13

14

15

16

17

18

19

20

RESET

OE

IR

RDEN2

RDEN1

RDCLK

GND

D17

GND

AF/AE

V

CC

WRTEN2

WRTEN1

WRTCLK

GND

D16

D15

NC

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NC − No internal connection

description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent

data rates. The SN74ACT7801 is a 1024- × 18-bit FIFO for high speed and fast access times. It processes data

at rates up to 40 MHz and access times of 15 ns in a bit-parallel format. Data outputs are noninverting with

respect to the data inputs. Expansion is easily accomplished in both word width and word depth.

The SN74ACT7801 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry

adds the ability to synchronize independent read and write (interrupts, requests) to their respective system

clock.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

†

logic symbol

Φ

FIFO 1024 × 18

SN74ACT7801

1

RESET

WRTCLK

RESET

29

30

31

5

WRTCLK

35

WRTEN1

WRTEN2

RDCLK

RDEN1

&

IN RDY

HALF FULL

IR

WRTEN

36

HF

33

RDCLK

ALMOSTFULL/EMPTY

OUT RDY,1

AF/AE

66

4

&

OR

2

OE

EN1

RDEN

3

RDEN2

27

DEF ALMOST FULL

DAF

26

25

24

23

22

21

20

19

17

15

14

13

12

11

10

9

38

D0

D1

0

Q0

39

Q1

41

D2

Q2

42

D3

Q3

44

D4

Q4

46

D5

Q5

47

D6

Q6

49

D7

Q7

50

D8

Q8

52

1

Data

D9

Q9

53

D10

D11

D12

D13

D14

D15

D16

D17

Q10

55

Q11

56

Q12

58

Q13

59

Q14

61

Q15

63

8

Q16

64

7

17

Q17

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the FN package.

3

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ꢃ ꢋ ×ꢋ ꢉ ꢇꢋ ꢅ ꢌꢍ ꢅꢎ ꢏꢐ ꢋ ꢑꢒ ꢓ ꢀꢆꢔꢒ ꢁꢕ ꢋ ꢑ ꢒ ꢓꢀ ꢆꢔꢍ ꢖꢆ ꢋꢗ ꢏꢗ ꢍꢓꢘ

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

functional block diagram

OE

D0 − D17

Location 1

Location 2

Synchronous

RDCLK

Read

Pointer

RDEN1

Control

RDEN2

1024 × 18 RAM

WRTCLK

Synchronous

Write

Pointer

WRTEN1

WRTEN2

Write

Control

Location 1023

Location 1024

Q0 − Q17

OR

Reset

Logic

Register

RESET

DAF

Status

Flag

Logic

IR

HF

AF/AE

functional description

inputs

data in (D0−D17)

Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0−D8 also carry the

almost-full/almost-empty offset value (X) on a high-to-low transition of the define almost-full (DAF) input.

reset (RESET)

A reset is accomplished by taking reset (RESET) low and generating a minimum of four read-clock (RDCLK)

and write-clock (WRTCLK) cycles. This ensures that the internal read and write pointers are reset and that the

output-ready flag (OR), the half-full flag (HF), and the input-ready flag (IR) are low; the almost-full/almost-empty

flag (AF/AE) is high. The FIFO must be reset upon power up. With the define almost-full (DAF) input at a low

level, a low pulse on RESET defines the AF/AE status flag using the almost-full/almost-empty offset value (X),

where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the AF/AE

flag using the default value of X = 256.

write enables (WRTEN1, WRTEN2)

The write enables (WRTEN1, WRTEN2) must be high before the rising edge of write clock (WRTCLK) for a word

to be written into memory. The write enables do not affect the storage of the almost-full/almost-empty offset

value (X).

4

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SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

functional description (continued)

write clock (WRTCLK)

Data is written into memory on a low-to-high transition of the write clock (WRTCLK) if the input-ready flag

output (IR) and the write-enable control inputs (WRTEN1, WRTEN2) are high. WRTCLK is a free-running clock

and functions as the synchronizing clock for all data transfers into the FIFO. The IR flag output is also driven

synchronously with respect to the WRTCLK signal.

read enables (RDEN1, RDEN2)

Both read enables (RDEN1, RDEN2) must be high before the rising edge of read clock (RDCLK) to read a word

out of memory. The read enables are not used to read the first word stored in memory.

read clock (RDCLK)

Data is read out of memory on a low-to-high transition at the read-clock (RDCLK) input if the output-ready flag

output (OR) and the output-enable (OE) and read-enable (RDEN1, RDEN2) control inputs are high. RDCLK is

a free-running clock and functions as the synchronizing clock for all data transfers out of the FIFO. The OR flag

is also driven synchronously with respect to the RDCLK signal.

define almost-full (DAF)

The high-to-low transition of the define almost-full (DAF) input stores the binary value of data inputs D0−D8 as

the almost-full/almost-empty offset value (X). With DAF held low, a low pulse on the reset (RESET) input defines

the almost-full/almost-empty flag (AF/AE) using X.

output enable (OE)

The data-out (Q0−Q17) outputs and the output-ready flag (OR) are in the high-impedance state when the output

enable (OE) input is low. OE must be high before the rising edge of read clock (RDCLK) to read a word from

memory.

outputs

data out (Q0−Q17)

The first data word to be loaded into the FIFO is moved to the data out (Q0− Q17) register on the rising edge

of the third read clock (RDCLK) pulse to occur after the first valid write. The read-enable (RDEN1, RDEN2)

inputs do not affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1,

RDEN2, and the output-ready flag (OR) are high.

input-ready flag (IR)

The input-ready flag (IR) is high when the FIFO is not full and low when the device is full. During reset, the IR

flag is driven low on the rising edge of the second write clock (WRTCLK) pulse. The IR flag is driven high on

the rising edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven

low, IR is driven high on the second WRTCLK pulse after the first valid read.

output-ready flag (OR)

The output-ready flag (OR) is high when the FIFO is not empty and low when it is empty. During reset, the OR

flag is set low on the rising edge of the third read clock (RDCLK) pulse. The OR flag is set high on the rising edge

of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge

of the first RDCLK pulse after the last word is read.

half-full status flag (HF)

The half-full flag (HF) is high when the FIFO contains 513 or more words and is low when it contains 512 or less

words.

5

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SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

functional description (continued)

almost-full/almost-empty status flag (AF/AE)

The almost-full/almost-empty flag (AF/AE) is defined by the almost-full/almost-empty offset value (X). The

AF/AE flag is high when the FIFO contains (X + 1) or less words or (1025 − X) or more words. The AF/AE flag

is low when the FIFO contains between (X + 2) and (1024 − X) words.

programming procedure for AF/AE

The almost-full/almost-empty flag (AF/AE) is programmed during each reset cycle. The almost-full/almost-

empty offset value (X) is either a user-defined value or the default value of X = 256. Below are instructions to

program AF/AE using both methods.

user-defined X:

1. Take DAF from high to low.

2. If RESET is not already low, take RESET low.

3. With DAF held low, take RESET high. This defines the AF/AE flag using X.

4. To retain the current offset for the next reset, keep DAF low.

default X:

To redefine the AF/AE flag using the default value of X = 256, hold DAF high during the reset cycle.

6

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SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

timing diagrams

RESET

Don’t Care

1

DAF

WRTCLK

2

3

4

1

2

Don’t Care

WRTEN1

WRTEN2

D0 − D17

RDCLK

RDEN1

RDEN2

OE

Don’t Care

†

X

Don’t Care

1

2

Don’t Care

3

4

Q0 − Q17

OR

Invalid

Don’t Care

AF/AE

HF

Don’t Care

Store the Value of D0−D8 as X

IR

Define the AF/AE Flag Using the Value of X

†

X is the binary value of D0−D8 only.

Figure 1. Reset Cycle: Define AF/AE Using the Value of X

7

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×

ꢋ

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SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

RESET

DAF

Don’t Care

1

WRTCLK

WRTEN1

WRTEN2

D0 − D17

RDCLK

RDEN1

RDEN2

OE

2

3

4

1

2

Don’t Care

3

1

2

4

Don’t Care

Q0 − Q17

OR

Invalid

Don’t Care

AF/AE

HF

Don’t Care

IR

Define the AF/AE Flag Using

the Default Value of X=256

Figure 2. Reset Cycle: Define AF/AE Using the Default Value

8

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ꢃ ꢋꢉ ꢇ ꢋ ꢅꢌ ꢍꢅ ꢎꢏꢐꢋ ꢑ ꢒꢓꢀ ꢆꢔꢒ ꢁꢕꢋ ꢑꢒ ꢓꢀꢆꢔꢍ ꢖꢆ ꢋ ꢗꢏ ꢗ ꢍ ꢓꢘ

ꢙ

ꢉ

ꢈ

ꢊ

ꢋ×

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

RESET

DAF

Don’t Care

WRTCLK

WRTEN1

WRTEN2

D0−D17

RDCLK

RDEN1

RDEN2

OE

W1

W2

1

W3

2

W4

WX+2

W513

W1025−X

W1025

3

Q0 − Q17

OR

W1

Invalid

AF/AE

HF

IR

Figure 3. Write

9

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ꢆꢔ

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ꢍꢓꢘ

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

RESET

DAF

Don’t Care

WRTCLK

WRTEN1

WRTEN2

D0 − D17

RDCLK

RDEN1

RDEN2

OE

1

2

W1025

Q0 − Q17

OR

W1

W2

W3

WX+1

WX+2

W513

W514 W1024−X W1025−X

W1024

W1025

AF/AE

HF

IR

Figure 4. Read

10

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ꢃ ꢋꢉ ꢇ ꢋ ꢅꢌ ꢍꢅ ꢎꢏꢐꢋ ꢑ ꢒꢓꢀ ꢆꢔꢒ ꢁꢕꢋ ꢑꢒ ꢓꢀꢆꢔꢍ ꢖꢆ ꢋ ꢗꢏ ꢗ ꢍ ꢓꢘ

ꢙ

ꢉ

ꢈ

ꢊ

ꢋ×

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

I

Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

′ACT7801-15

′ACT7801-18

′ACT7801-20

UNIT

MIN

4.5

2

MAX

MIN

4.5

2

MAX

MIN

4.5

2

MAX

V

Supply voltage

5.5

V

CC

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Clock frequency

IH

0.8

−8

16

0.8

−8

16

0.8

−8

16

V

IL

I

f

mA

MHz

OH

OL

clock

40

10

7

35

12

8.5

15

8.5

15

10

5

28.5

14

10

15

10

15

10

5

Data in (D0−D17) high or low

WRTCLK high

WRTCLK low

15

7

RDCLK high

t

w

t

su

t

h

Pulse duration

Setup time

Hold time

ns

RDCLK low

15

10

5

DAF high

WRTEN1, WRTEN2 high or low

OE, RDEN1, RDEN2 high or low

Data in (D0−D17) before WRTCLK↑

WRTEN1, WRTEN2 before WRTCLK↑

OE, RDEN1, RDEN2 before RDCLK↑

5

Reset: RESET low before first WRTCLK and

RDCLK↑

7

ns

Define AF/AE: D0−D8 before DAF↓

Define AF/AE: DAF↓ before RESET↑

Define AF/AE (default): DAF high before RESET↑

Data in (D0−D17) after WRTCLK↑

5

7

5

1

5

7

5

1

5

7

5

1

WRTEN1, WRTEN2 after WRTCLK↑

OE, RDEN1, RDEN2 after RDCLK↑

Reset: RESET low after fourth WRTCLK and

RDCLK↑

0

ns

Define AF/AE: D0−D8 after DAF↓

1

0

1

0

1

0

1

0

1

0

1

0

Define AF/AE: DAF low after RESET↑

Define AF/AE (default): DAF high after RESET↑

T

A

Operating free-air temperature

70

°C

11

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ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢂꢇꢈ ꢉ

ꢉ

ꢙ

ꢈꢊ

ꢃ ꢋ ×ꢋ ꢉ ꢇꢋ ꢅ ꢌꢍ ꢅꢎ ꢏꢐ ꢋ ꢑꢒ ꢓ ꢀꢆꢔꢒ ꢁꢕ ꢋ ꢑ ꢒ ꢓꢀ ꢆꢔꢍ ꢖꢆ ꢋꢗ ꢏꢗ ꢍꢓꢘ

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

= 4.5 V,

= 5.5 V,

I

= − 8 mA

= 16 mA

2.4

OH

CC

OH

0.5

5

V

OL

CC

OL

I

V = V

I CC

or 0

µA

mA

µA

pF

I

CC

V = V

O CC

5

OZ

CC

‡

§

Supply current

f

= 25 MHz

200

20

230

25

400

CC1

CC2

CC3

clock

Standby current

Power-down current

V

= WRTCLK,

V = V or V

I IH IL

IH

V = V

− 0.2 V or 0

I

CC

C

V = 0,

I

f = 1 MHz

4

8

i

V

O

= 0,

o

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C = 50 pF (see Figures 9 and 10)

L

′ACT7801-15

′ACT7801-18

′ACT7801-20

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

UNIT

†

MIN TYP

MAX

MIN

35

5

MAX

MIN

28.5

5

MAX

f

t

WRTCLK or RDCLK

40

MHz

max

5

12

15

18

20

pd

RDCLK↑

Any Q

ns

¶

10.5

pd

WRTCLK↑

RDCLK↑

IR

4

7

6

4

2

10

20

19

21

11

14

4

7

6

4

2

12

22

21

23

11

14

4

7

6

4

2

14

24

23

25

11

14

ns

pd

OR

WRTCLK↑

RDCLK↑

t

pd

AF/AE

HF

ns

t

WRTCLK↑

RDCLK↑

PLH

PHL

PLH

PHL

en

AF/AE

HF

RESET↓

OE

Any Q, OR

dis

†

‡

§

¶

All typical values are at V

CC

= 5 V, T = 25°C.

A

I

tested with outputs open.

CC

For frequencies greater than 25 MHz, I

= 230 mA + (6 mA × [f − 25 MHz]).

CC

This parameter is measured with C = 30 pF (see Figure 5).

L

12

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ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢂꢇ ꢈꢉ

ꢃ ꢋꢉ ꢇ ꢋ ꢅꢌ ꢍꢅ ꢎꢏꢐꢋ ꢑ ꢒꢓꢀ ꢆꢔꢒ ꢁꢕꢋ ꢑꢒ ꢓꢀꢆꢔꢍ ꢖꢆ ꢋ ꢗꢏ ꢗ ꢍ ꢓꢘ

ꢙ

ꢉ

ꢈ

ꢊ

ꢋ×

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME

vs

LOAD CAPACITANCE

18

17

16

15

V

= 5 V

= 25°C

= 500 Ω

CC

T

A

R

L

14

13

12

11

10

0

30 50

100

150

200

250

300

C

− Load Capacitance − pF

L

Figure 5

POWER DISSIPATION CAPACITANCE

vs

SUPPLY VOLTAGE

68

f = 5 MHz

i

T

= 25°C

= 50 pF

A

C

67

66

65

64

63

62

L

4.5 4.6 4.7 4.8 4.9

5

5.1 5.2 5.3 5.4 5.5

V

CC

- Supply Voltage - V

Figure 6

13

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ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢂꢇꢈ ꢉ

ꢉ

ꢙ

ꢈꢊ

ꢃ ꢋ ×ꢋ ꢉ ꢇꢋ ꢅ ꢌꢍ ꢅꢎ ꢏꢐ ꢋ ꢑꢒ ꢓ ꢀꢆꢔꢒ ꢁꢕ ꢋ ꢑ ꢒ ꢓꢀ ꢆꢔꢍ ꢖꢆ ꢋꢗ ꢏꢗ ꢍꢓꢘ

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

calculating power dissipation

With I

taken from Figure 6, the maximum power dissipation based on all data outputs changing states on

CCF

each read may be calculated using:

P = V × [I + (N × ∆I × dc)] + Σ(C × V × fo)

CC

2

t

CC

CCF

CC

L

A more accurate power calculation based on device use and average number of data outputs switching can be

found using:

2

P = V

× [I

+ (N × ∆I

× dc)] + Σ(C × V

× fi) + Σ(C × V

× fo)

t

CC

pd

CC

L

CC

where:

I

N

∆ I

dc

C

= power-down I

= number of inputs driven by a TTL device

= increase in supply current

= duty cycle of inputs at a TTL high level of 3.4 V

= power dissipation capacitance

= output capacitive load

maximum

CC

pd

L

f

= data input frequency

= data output frequency

i

o

14

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ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢂꢇ ꢈꢉ

ꢃ ꢋꢉ ꢇ ꢋ ꢅꢌ ꢍꢅ ꢎꢏꢐꢋ ꢑ ꢒꢓꢀ ꢆꢔꢒ ꢁꢕꢋ ꢑꢒ ꢓꢀꢆꢔꢍ ꢖꢆ ꢋ ꢗꢏ ꢗ ꢍ ꢓꢘ

ꢙ

ꢉ

ꢈ

ꢊ

ꢋ×

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

APPLICATION INFORMATION

expanding the SN74ACT7801

The SN74ACT7801 is expandable in width and depth. Expanding in word depth offers special timing

considerations:

1. After the first data word is loaded into the FIFO, the word is unloaded, and the output-ready flag output (OR)

goes high after (N × 3) read clock (RDCLK) cycles, where N is the number of devices used in depth

expansion.

2. After the FIFO is filled, the input-ready flag output (IR) goes low, the first word is unloaded, and the IR flag

output is driven high after (N × 2) write clock cycles, where N is the number of devices used in depth

expansion.

CLOCK

’ACT7801

WRTCLK

RDCLK

OR

WRTCLK

WRTEN1

WRTEN2

IR

WRTCLK

WRTEN1

WRTEN2

IR

RDCLK

RDEN1

RDEN2

OR

RDCLK

RDEN1

RDEN2

OR

WRTEN1

RDEN1

RDEN2

OE

WRTEN2

IR

5 V

OE

Q0−Q17

D0 − D17

Q0 − Q17

Figure 7. Word-Depth Expansion: 2048 Words × 18 Bits, N = 2

’ACT7801

WRTCLK

WRTEN

WRTCLK

WRTEN1

WRTEN2

IR

RDCLK

RDEN1

RDEN2

OR

RDCLK

RDEN

OE

D0 − D17

Q0 − Q17

D18 − D35

IR

Q18 − Q35

OR

’ACT7801

WRTCLK

WRTEN1

WRTEN2

IR

RDCLK

RDEN1

RDEN2

OR

OE

D0 − D17

Q0 − Q17

Figure 8. Word-Width Expansion: 1024 Words × 36 Bits

15

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ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢂꢇꢈ ꢉ

ꢉ

ꢙ

ꢈꢊ

ꢃ ꢋ ×ꢋ ꢉ ꢇꢋ ꢅ ꢌꢍ ꢅꢎ ꢏꢐ ꢋ ꢑꢒ ꢓ ꢀꢆꢔꢒ ꢁꢕ ꢋ ꢑ ꢒ ꢓꢀ ꢆꢔꢍ ꢖꢆ ꢋꢗ ꢏꢗ ꢍꢓꢘ

SCAS111 − D3489, APRIL 1990 − REVISED MAY 1991

PARAMETER MEASUREMENT INFORMATION

3 V

Input

1.5 V

From Output

Under Test

GND

t

pd

t

R

L

= 500 Ω

C = 50 pF

L

pd

3 V

0 V

Output

1.5 V

LOAD CIRCUIT

TOTEM-POLE OUTPUTS

Figure 9. Standard CMOS Outputs (OR, Half Full, AF/AE)

3 V

0 V

1.5 V

Input

Output

V

CC

t

PZL

PLZ

≈ V

CC

S1

S2

0.3 V

1.5 V

R

L

From Output

Under Test

V

OL

t

PHZ

t

C

PZH

L

V

OH

1.5 V

0.3 V

≈ 0 V

LOAD CIRCUIT

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

†

PARAMETER

R

C

S1

S2

L

t

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

PZH

t

500 Ω

50 pF

en

t

PZL

t

PHZ

t

500 Ω

50 pF

dis

t

PLZ

t

or t

−

pd

t

†

Includes probe and test-fixture capacitance.

Figure 10. 3-State Outputs (Any Q, OR)

16

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PACKAGE OPTION ADDENDUM

www.ti.com

28-Aug-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

PLCC

Drawing

SN74ACT7801-18FN

SN74ACT7801-18FNR

SN74ACT7801-20FN

OBSOLETE

FN

68

TBD

Call TI

FN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN74ACT7801FN
厂家：	TEXAS INSTRUMENTS
描述：	IC,FIFO,1KX18,SYNCHRONOUS,ACT-CMOS,LDCC,68PIN,PLASTIC 存储
文件：	总19页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74ACT7801FN [TI]

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