SN74AHCT594PWR [TI]
8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS; 8位的移位寄存器与输出寄存器
| 型号： | SN74AHCT594PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS |
| 文件： | 总14页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
SN54AHCT594 . . . J OR W PACKAGE
SN74AHCT594 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
8-Bit Serial-In, Parallel-Out Shift
Registers With Storage
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
Independent Direct Overriding Clears
on Shift and Storage Registers
B
Q
C
D
A
Q
SER
Independent Clocks for Both Shift and
Storage Registers
Q
RCLR
E
Q
12 RCLK
F
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
11
10
9
Q
SRCLK
SRCLR
G
Q
H
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
GND
Q
H′
– 1000-V Charged-Device Model (C101)
SN54AHCT594 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
The ’AHCT594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (SRCLR, RCLR) inputs are
provided on both the shift and storage registers.
3
2
1
20 19
18
SER
RCLR
NC
Q
4
5
6
7
8
D
Q
17
16
E
NC
15 RCLK
14
9 10 11 12 13
Q
F
A serial (Q ) output is provided for cascading
H′
SRCLK
Q
G
purposes.
Both the shift register (SRCLK) and storage
register (RCLK) clocks are positive edge
triggered. If both clocks are connected together,
the shift register always is one count pulse ahead
of the storage register.
NC – No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
SOIC – D
Tube
SN74AHCT594N
SN74AHCT594N
Tube
SN74AHCT594D
AHCT594
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHCT594DR
SN74AHCT594NSR
SN74AHCT594DBR
SN74AHCT594PWR
SNJ54AHCT594J
SNJ54AHCT594W
SNJ54AHCT594FK
–40°C to 85°C
SOP – NS
SSOP – DB
TSSOP – PW
CDIP – J
AHCT594
HB594
HB594
SNJ54AHCT594J
SNJ54AHCT594W
SNJ54AHCT594FK
–55°C to 125°C
CFP – W
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
FUNCTION TABLE
INPUTS
FUNCTION
SER SRCLK SRCLR RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
L
X
X
X
↓
H
X
X
X
X
X
↑
X
L
Shift-register state is not changed.
Storage register is cleared.
X
X
X
H
H
Shift-register data is stored in the storage register.
Storage-register state is not changed.
↓
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
logic diagram (positive logic)
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
R
3D
14
15
SER
Q
1D
C1
R
Q
Q
Q
Q
Q
Q
Q
Q
A
B
C
D
C3
R
3D
1
2
2D
C2
R
Q
Q
C3
R
3D
2D
C2
R
C3
R
3D
3
4
5
2D
C2
R
Q
Q
C3
R
3D
2D
C2
R
Q
Q
Q
Q
E
F
C3
R
3D
2D
C2
R
Q
Q
Q
C3
R
3D
6
2D
C2
R
Q
Q
Q
G
C3
R
3D
7
9
Q
Q
2D
C2
R
H
C3
H′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
timing diagram
SRCLK
SER
RCLK
SRCLR
RCLR
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H’
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHCT594 SN74AHCT594
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
V
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–8
–8
mA
mA
ns/V
°C
OH
8
8
20
85
OL
t/ v
20
T
–55
125
–40
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT594 SN74AHCT594
PARAMETER
TEST CONDITIONS
= –50
V
UNIT
V
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
A
4.5
OH
OH
OL
OL
V
4.5 V
4.5 V
OH
OL
= –8 mA
= 50
= 8 mA
3.94
3.8
3.8
A
0.1
0.36
±0.1
2
0.1
0.44
±1*
20
0.1
0.44
±1
V
V
I
I
V = 5.5 V or GND
0 V to 5.5 V
5.5 V
A
A
I
I
V = V
or GND,
I = 0
O
20
CC
I
CC
One input at 3.4 V,
Other inputs at V
†
5.5 V
5 V
2
2.2
2.2
10
mA
pF
∆I
CC
or GND
CC
V = V or GND
CC
C
2
10
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
= 0 V.
CC
†
.
timing requirements over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
SN54AHCT594 SN74AHCT594
A
UNIT
MIN
5
MAX
MIN
5.5
5.5
3
MAX
MIN
5.5
5.5
3
MAX
RCLK or SRCLK high or low
RCLR or SRCLR low
t
w
Pulse duration
ns
5.2
3
SER before SRCLK↑
‡
SRCLK↑ before RCLK↑
5
5
5
t
t
SRCLR low before RCLK↑
5
5
5
ns
ns
Setup time
Hold time
su
SRCLR high (inactive) before SRCLK↑
RCLR high (inactive) before RCLK↑
SER after SRCLK↑
2.9
3.4
2
3.3
3.8
2
3.3
3.8
2
h
‡
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170*
140
3.3*
3.7*
3.7*
4.1*
4.5*
4.1*
4.9
SN54AHCT594 SN74AHCT594
UNIT
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
135*
120
MAX
MIN
115*
95
1*
1*
1*
1*
1*
1*
1
MAX
MIN
115
95
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
ns
max
t
t
t
t
t
t
t
t
t
t
t
t
6.2*
6.5*
6.8*
7.2*
7.6*
7.1*
7.8
6.5*
6.9*
7.2*
7.6*
8.2*
7.6*
8.3
6.5
6.9
PLH
PHL
PLH
PHL
PHL
PHL
PLH
PHL
PLH
PHL
PHL
PHL
C
C
= 15 pF
= 15 pF
RCLK
Q –Q
A
L
L
H
1
1
7.2
ns
SRCLK
Q
H′
1
7.6
C
C
= 15 pF
= 15 pF
1
8.2
ns
ns
RCLR
Q –Q
A
L
L
H
1
7.6
SRCLR
Q
H′
1
8.3
C
C
= 50 pF
= 50 pF
ns
ns
RCLK
Q –Q
A
L
L
H
5.8
8.9
1
9.7
1
9.7
5.5
8.6
1
9.1
1
9.1
SRCLK
Q
H′
6
9.2
1
10.1
10.7
10.1
1
10.1
10.7
10.1
C
C
= 50 pF
= 50 pF
6.6
10
1
1
ns
ns
RCLR
Q –Q
A
L
L
H
6
9.2
1
1
SRCLR
Q
H′
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT594
PARAMETER
UNIT
MIN
TYP
1
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.6
3.8
OL
OH
2
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
112
pF
pd
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT594, SN74AHCT594
8-BIT SHIFT REGISTERS
WITH OUTPUT REGISTERS
SCLS417F – JUNE 1998 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
0.775
0.920
1.060
A MAX
A
(19,69) (19,69) (23,37) (26,92)
16
9
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21,59) (23,88)
MS-100
VARIATION
0.260 (6,60)
0.240 (6,10)
AA
BB
AC
AD
C
1
8
0.070 (1,78)
0.045 (1,14)
D
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
D
0.030 (0,76)
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
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