SN74ALS1645ANSR [TI]
ALS SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20;![SN74ALS1645ANSR](http://pdffile.icpdf.com/pdf2/p00242/img/icpdf/SN74ALS1645A_1465246_icpdf.jpg)
型号: | SN74ALS1645ANSR |
厂家: | ![]() |
描述: | ALS SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20 光电二极管 输出元件 逻辑集成电路 |
文件: | 总11页 (文件大小:579K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
DW OR N PACKAGE
(TOP VIEW)
Bidirectional Bus Transceivers in
High-Density 20-Pin Packages
Lower-Power Versions of SN74ALS640B
and SN74ALS645A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic (N) 300-mil DIPs
description
These octal bus transceivers are designed for
asynchronous two-way communication between
data buses. These devices transmit data from the
A bus to the B bus or from the B bus to the A bus,
depending on the level at the direction-control
GND
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated. The SN74ALS1640A features inverting logic, while the SN74ALS1645A features noninverting logic.
The SN74ALS1640A and SN74ALS1645A are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
DIR
L
SN74ALS1640A
SN74ALS1645A
B data to A bus
A data to B bus
Isolation
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
†
logic symbols
SN74ALS1640A
G3
SN74ALS1645A
G3
19
19
OE
1
OE
1
DIR
3 EN1 [BA]
3 EN2 [AB]
DIR
3 EN1 [BA]
3 EN2 [AB]
2
18
2
18
A1
B1
1
A1
B1
1
2
2
3
17
16
15
14
13
12
11
3
4
5
6
7
8
9
17
16
15
14
13
12
11
A2
4
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
A3
5
A4
6
A5
7
A6
8
A7
9
A8
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
logic diagrams (positive logic)
SN74ALS1640A
SN74ALS1645A
19
19
1
OE
OE
1
DIR
DIR
2
18
2
18
B1
B1
A1
A1
To Seven Other Transceivers
To Seven Other Transceivers
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which
use a trace length of zero.
recommended operating conditions
SN74ALS1640A
SN74ALS1645A
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–15
16
V
IL
I
I
mA
mA
°C
OH
OL
T
A
0
70
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS1640A
SN74ALS1645A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= –0.4 mA
= –3 mA
= –15 mA
= 8 mA
V
CC
–2
CC
OH
OH
OH
OL
OL
2.4
2
3.2
V
OH
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 4.5 V
= 5.5 V
= 5.5 V,
= 5.5 V,
0.25
0.35
0.4
0.5
0.1
0.1
20
V
OL
V
= 16 mA
Control inputs
A or B ports
V = 7 V
I
I
I
mA
µA
I
V = 5.5 V
I
Control inputs
V = 2.7 V
I
IH
IL
‡
A or B ports
Control inputs
20
–0.1
–0.1
–112
32
I
I
I
V = 0.4 V
I
mA
mA
mA
‡
A or B ports
§
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V
= 5.5 V
V = 2.25 V
O
–30
O
SN74ALS1640A
SN74ALS1645A
18
25
CC
38
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
= 5 V, T = 25°C.
A
IH IL
CC
.
OS
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
¶
= MIN to MAX
SN74ALS1640A SN74ALS1645A
MIN
4
MAX
15
MIN
2
MAX
13
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
OE
ns
ns
ns
B or A
A or B
A or B
2
10
2
13
5
20
8
25
5
22
8
25
2
10
2
12
OE
5
13
3
18
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALS1640A, SN74ALS1645A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SDAS246B – DECEMBER 1982 – REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74ALS1640AN
SN74ALS1645AN
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
0 to 70
0 to 70
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74ALS1645AN
ALS1645A
SN74ALS1645ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ALS1645ANSR
SO
NS
20
2000
330.0
24.4
8.2
13.0
2.5
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO NS 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74ALS1645ANSR
2000
Pack Materials-Page 2
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