SN74ALS563BDWG4 [TI]
ALS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20;
| 型号： | SN74ALS563BDWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ALS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢂꢆ ꢇ ꢈꢉ ꢀꢁꢊ ꢃ ꢄ ꢅꢀ ꢂꢆ ꢇꢈ
ꢋ ꢌꢍꢄꢅ ꢎꢏꢍ ꢐꢑ ꢒ ꢍ ꢓꢄꢁꢀ ꢑꢄꢓꢒ ꢁꢍ ꢅꢄꢍꢌ ꢔ ꢒꢀ
ꢕ ꢖꢍ ꢔ ꢇ ꢏꢀꢍꢄꢍ ꢒ ꢋ ꢗꢍ ꢑꢗ ꢍꢀ
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004
SN54ALS563B . . . J OR W PACKAGE
SN74ALS563B . . . DW, N, OR NS PACKAGE
(TOP VIEW)
D 3-State Buffer-Type Outputs Drive Bus
Lines Directly
D Bus-Structured Pinout
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
19 1Q
1
2
3
4
5
6
7
8
9
10
20
description/ordering information
18 2Q
These 8-bit D-type transparent latches feature
3-state outputs designed specifically for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
17
16
15
14
13
12
11
3Q
4Q
5Q
6Q
7Q
8Q
LE
While the latch-enable (LE) input is high, the Q
outputs follow the complements of data (D) inputs.
When LE is taken low, the outputs are latched at
the inverse of the levels set up at the D inputs.
GND
SN54ALS563B . . . FK PACKAGE
(TOP VIEW)
A buffered output-enable (OE) input places the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased high logic
level provide the capability to drive bus lines
without interface or pullup components.
3
2
1
20 19
18
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
9 10 11 12 13
OE does not affect internal operations of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
†
T
A
PACKAGE
TOP-SIDE MARKING
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Tube of 20
Tube of 85
Tube of 55
SN74ALS563BN
SN74ALS563BN
SN74ALS563BDW
SN74ALS563BDWR
SN74ALS563BNSR
SNJ54ALS563BJ
SNJ54ALS563BW
SNJ54ALS563BFK
0°C to 70°C
SOIC − DW
ALS563B
SOP − NS
CDIP − J
ALS563B
SNJ54ALS563BJ
SNJ54ALS563BW
SNJ54ALS563BFK
−55°C to 125°C
CFP − W
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢀꢂ ꢆꢇ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢀ ꢂ ꢆ ꢇꢈ
ꢋꢌ ꢍꢄ ꢅ ꢎ ꢏꢍ ꢐꢑꢒ ꢍꢓ ꢄꢁ ꢀꢑꢄꢓ ꢒꢁ ꢍ ꢅꢄꢍꢌ ꢔ ꢒꢀ
ꢕꢖ ꢍ ꢔ ꢇ ꢏꢀꢍꢄꢍ ꢒ ꢋꢗꢍ ꢑꢗ ꢍꢀ
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
LE
H
H
L
D
H
L
L
L
L
H
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
11
LE
C1
1D
19
1Q
2
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Notes 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢂꢆ ꢇ ꢈꢉ ꢀꢁꢊ ꢃ ꢄ ꢅꢀ ꢂꢆ ꢇꢈ
ꢋ ꢌꢍꢄꢅ ꢎꢏꢍ ꢐꢑ ꢒ ꢍ ꢓꢄꢁꢀ ꢑꢄꢓꢒ ꢁꢍ ꢅꢄꢍꢌ ꢔ ꢒꢀ
ꢕ ꢖꢍ ꢔ ꢇ ꢏꢀꢍꢄꢍ ꢒ ꢋ ꢗꢍ ꢑꢗ ꢍꢀ
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004
recommended operating conditions (see Note 3)
SN54ALS563B
MIN NOM MAX
SN74ALS563B
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
Operating free-air temperature
IH
0.7
−1
12
0.8
−2.6
24
V
IL
I
I
t
t
t
mA
mA
ns
ns
ns
°C
OH
OL
w
15
20
15
10
10
0
su
h
12
T
A
−55
125
70
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS563B
SN74ALS563B
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
I = −18 mA
−1.2
−1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= −0.4 mA
= −1 mA
= −2.6 mA
= 12 mA
= 24 mA
= 2.7 V
V
−2
V
CC
−2
CC
OH
OH
OH
OL
OL
CC
2.4
3.3
V
OH
V
V
= 4.5 V
= 4.5 V
CC
CC
2.4
3.2
0.25
0.35
0.25
0.4
0.4
0.5
20
V
OL
V
V
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
20
−20
0.1
µA
µA
OZH
O
O
I
V
= 0.4 V
−20
0.1
20
OZL
I
V = 7 V
I
mA
µA
I
I
IH
V = 2.7 V
I
20
I
IL
V = 0.4 V
I
−0.1
−112
17
−0.1
−112
17
mA
mA
‡
I
O
V
O
= 2.25 V
−20
−30
Outputs high
Outputs low
10
16
17
10
16
17
I
V
CC
= 5.5 V
26
26
mA
CC
Outputs disabled
29
29
†
‡
All typical values are at V
= 5 V, T = 25°C.
CC
A
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢀꢂ ꢆꢇ ꢈꢉ ꢀ ꢁꢊ ꢃ ꢄꢅꢀ ꢂ ꢆ ꢇꢈ
ꢋꢌ ꢍꢄ ꢅ ꢎ ꢏꢍ ꢐꢑꢒ ꢍꢓ ꢄꢁ ꢀꢑꢄꢓ ꢒꢁ ꢍ ꢅꢄꢍꢌ ꢔ ꢒꢀ
ꢕꢖ ꢍ ꢔ ꢇ ꢏꢀꢍꢄꢍ ꢒ ꢋꢗꢍ ꢑꢗ ꢍꢀ
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V
= 50 pF
CC
L
R1 = 500 Ω
R2 = 500 Ω
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
†
= MIN to MAX
SN54ALS563B SN74ALS563B
MIN
3
MAX
26
MIN
3
MAX
18
t
t
t
t
PLH
PHL
PLH
PHL
PZH
D
ns
ns
ns
ns
Q
Q
Q
Q
3
15
3
14
8
29
6
22
LE
OE
OE
4
22
6
21
t
4
25
3
18
t
4
21
4
18
PZL
PHZ
t
2
12
1
10
t
3
22
1
15
PLZ
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢂꢆ ꢇ ꢈꢉ ꢀꢁꢊ ꢃ ꢄ ꢅꢀ ꢂꢆ ꢇꢈ
ꢋ ꢌꢍꢄꢅ ꢎꢏꢍ ꢐꢑ ꢒ ꢍ ꢓꢄꢁꢀ ꢑꢄꢓꢒ ꢁꢍ ꢅꢄꢍꢌ ꢔ ꢒꢀ
ꢕ ꢖꢍ ꢔ ꢇ ꢏꢀꢍꢄꢍ ꢒ ꢋ ꢗꢍ ꢑꢗ ꢍꢀ
SDAS163B − DECEMBER 1982 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
t
w
h
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
[3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
0.3 V
9 0 V
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-88700012A
5962-8870001RA
5962-8870001SA
SN54ALS563BJ
SN74ALS563BDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
Call TI
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
W
J
CDIP
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS563BDWE4
SN74ALS563BDWG4
SN74ALS563BDWR
SN74ALS563BDWRE4
SN74ALS563BDWRG4
SN74ALS563BN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DW
DW
DW
DW
DW
N
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS563BN3
SN74ALS563BNE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ALS563BNSR
SN74ALS563BNSRE4
SN74ALS563BNSRG4
ACTIVE
ACTIVE
ACTIVE
SO
SO
SO
NS
NS
NS
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ALS563BFK
SNJ54ALS563BJ
SNJ54ALS563BW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
W
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ALS563BDWR
SN74ALS563BNSR
SOIC
SO
DW
NS
20
20
2000
2000
330.0
330.0
24.4
24.4
10.8
8.2
13.0
13.0
2.7
2.5
12.0
12.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ALS563BDWR
SN74ALS563BNSR
SOIC
SO
DW
NS
20
20
2000
2000
346.0
346.0
346.0
346.0
41.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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