SN74ALVC126 [TI]
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS; 四路总线缓冲器闸具有三态输出
| 型号： | SN74ALVC126 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
D, DGV, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1OE
1A
V
CC
4OE
4A
1
2
3
4
5
6
7
14
13
12
11
1Y
Latch-Up Performance Exceeds 250 mA Per
JESD 17
2OE
2A
4Y
10 3OE
Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
2Y
9
8
3A
3Y
GND
description
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V
operation.
CC
The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.
The SN74ALVC126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
H
H
L
H
L
X
Z
†
logic symbol
1
1
1OE
1A
EN
3
6
1Y
2Y
3Y
4Y
2
4
2OE
5
2A
3OE
3A
10
9
8
13
12
4OE
11
4A
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
logic diagram (positive logic)
1
10
9
1OE
3OE
3A
2
3
6
8
1A
1Y
2Y
3Y
4Y
4
13
12
2OE
4OE
4A
5
11
2A
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
–4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–12
–12
–24
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
12
12
24
5
I
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–40
85
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –4 mA
= –6 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
2
V
OH
2.3 V
1.7
2.2
2.4
2
V
I
= –12 mA
2.7 V
OH
3 V
I
I
I
I
= –24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 6 mA
V
OL
V
2.3 V
0.7
I
= 12 mA
OL
2.7 V
0.4
I
= 24 mA
3 V
0.55
±5
OL
I
I
I
V = V
or GND
3.6 V
µA
µA
µA
µA
I
I
CC
CC
V
= V
or GND
3.6 V
±10
10
OZ
CC
O
CC
V = V
or GND,
– 0.6 V,
I
= 0
3.6 V
I
O
∆I
CC
One input at V
Other inputs at V
CC
or GND
3 V to 3.6 V
750
CC
Control inputs
Data inputs
Outputs
3.5
3.5
5.5
C
V = V or GND
CC
3.3 V
3.3 V
pF
pF
i
I
C
V
O
= V
or GND
o
CC
†
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
1.3
1
MAX
5.6
MIN
1
MAX
3.4
MIN
MAX
3.4
MIN
1.1
1
MAX
3.1
t
A
ns
ns
ns
Y
Y
Y
pd
t
en
OE
OE
5.9
1
3.8
3.8
3.3
t
1.8
5.6
1
3.3
4.4
1
3.7
dis
operating characteristics, T = 25°C
A
V
= 1.8V
CC
TYP
V
CC
= 2.5 V
V = 3.3 V
CC
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
15
2
17
2
19
3
Power dissipation
capacitance per gate
C = 0,
L
f = 10 MHz
C
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
GND
S1
1 kΩ
From Output
Under Test
TEST
S1
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Data
Input
V
CC
V
/2
V
CC
/2
CC
Output
Control
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
V
V
+ 0.15 V
V
S1 at 2 × V
(see Note B)
OL
CC
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
S1
500 Ω
From Output
Under Test
TEST
S1
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Data
Input
V
CC
V
/2
V
CC
/2
CC
Output
Control
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
V
V
+ 0.15 V
V
S1 at 2 × V
(see Note B)
OL
CC
0 V
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVC126
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES111E – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
6 V
Open
GND
TEST
S1
S1
500 Ω
t
Open
6 V
pd
/t
From Output
Under Test
t
PLZ PZL
/t
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
1.5 V
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
1.5 V
1.5 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
OH
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
– 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1999, Texas Instruments Incorporated
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