SN74ALVCH162344DGGR [TI]
1-Bit To 4-Bit Address Driver With 3-State Outputs 56-TSSOP -40 to 85;
| 型号： | SN74ALVCH162344DGGR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-Bit To 4-Bit Address Driver With 3-State Outputs 56-TSSOP -40 to 85 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
OE1
1B1
1B2
GND
1B3
1B4
OE4
8B1
8B2
GND
8B3
8B4
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
2
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
3
4
5
Latch-Up Performance Exceeds 250 mA Per
JESD 17
6
V
V
7
CC
CC
1A
2B1
2B2
GND
2B3
2B4
2A
8A
8
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
7B1
7B2
GND
7B3
7B4
7A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Package Options Include Plastic 300-mil
Shrink Small-Outline (DGG), Thin Shrink
Small-Outline (DL), and Thin Very
Small-Outline (DGV) Packages
NOTE: For tape and reel order entry:
3A
6A
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
3B1
3B2
GND
3B3
3B4
4A
6B1
6B2
GND
6B3
6B4
5A
description
This 1-bit to 4-bit address driver is designed for
1.65-V to 3.6-V V
operation.
CC
V
V
CC
CC
The SN74ALVCH162344 is used in applications
in which four separate memory locations must be
addressed by a single address.
4B1
4B2
GND
5B1
5B2
GND
The outputs, which are designed to sink up to
12 mA, include equivalent 26-Ω resistors to
reduce overshoot and undershoot.
4B3 26
31 5B3
4B4
5B4
27
28
30
29
OE2
OE3
To ensure the high-impedance state during power
up or power down, the output enable (OE) inputs
shouldbetiedtoV throughapullupresistor;the
CC
minimumvalueoftheresistorisdeterminedbythe
current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162344 is characterized for operation from –40°C to 85°C.
A-TO-B FUNCTION TABLE
INPUTS
OUTPUT
Bn
OE
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
logic diagram (positive logic)
56
OE4
29
OE3
28
OE2
1
OE1
2
3
34
33
31
30
41
40
38
37
48
47
45
44
55
54
52
51
1B1
1B2
1B3
1B4
2B1
2B2
2B3
2B4
3B1
3B2
3B3
3B4
4B1
4B2
4B3
4B4
5B1
5B2
5B3
5B4
6B1
6B2
6B3
6B4
7B1
7B2
7B3
7B4
8B1
8B2
8B3
8B4
8
36
42
43
49
1A
5A
6A
7A
8A
5
6
9
10
12
13
16
17
19
20
23
24
26
27
14
2A
15
3A
21
4A
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
–2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–6
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
2
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
6
I
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–40
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –2 mA
= –4 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
1.9
1.7
2.4
2
V
OH
2.3 V
V
I
= –6 mA
OH
3 V
I
I
I
I
I
= –8 mA
= –12 mA
= 100 µA
= 2 mA
2.7 V
OH
OH
OL
OL
OL
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 4 mA
V
OL
2.3 V
0.55
0.55
0.6
V
I
= 6 mA
OL
3 V
I
I
= 8 mA
2.7 V
OL
= 12 mA
3 V
0.8
OL
I
V = V
or GND
3.6 V
±5
µA
µA
I
I
CC
V = 0.58 V
I
1.65 V
1.65 V
2.3 V
25
–25
45
V = 1.07 V
I
V = 0.7 V
I
I
V = 1.7 V
I
2.3 V
–45
75
I(hold)
V = 0.8 V
I
3 V
V = 2 V
I
3 V
–75
‡
V = 0 to 3.6 V
3.6 V
±500
±10
40
I
I
I
V
O
= V
or GND
CC
or GND,
3.6 V
µA
µA
µA
OZ
V = V
I
I = 0
O
3.6 V
CC
CC
∆I
CC
One input at V
– 0.6 V,
Other inputs at V
or GND
CC
3 V to 3.6 V
750
CC
Control inputs
Data inputs
Outputs
2.5
3.5
4
C
V = V or GND
CC
3.3 V
3.3 V
pF
pF
i
I
C
V
O
= V
or GND
o
CC
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
CC
= 1.8 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
TYP
MIN
1
MAX
4.9
MIN
MAX
5.1
MIN
1.4
1.2
1.2
MAX
4.4
§
§
§
t
t
t
t
t
A
B
B
B
ns
ns
ns
ns
ns
pd
1
6.4
6.6
5.7
OE
OE
en
1
5.4
4.7
4.5
dis
¶
#
0.35
0.5
sk(o)
sk(o)
§
¶
#
This information was not available at the time of publication.
Skew between outputs of the same bank and same package (same transition)
Skew between outputs of all banks of same package (A1–A8 tied together)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V
= 3.3 V
CC
TYP
PARAMETER
TEST CONDITIONS
UNIT
†
†
Outputs enabled
Outputs disabled
68
12
82
14
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
Open
2 × V
GND
t
pd
/t
C
= 30 pF
t
L
PLZ PZL
CC
GND
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
6 V
Open
TEST
S1
S1
t
Open
6 V
pd
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
GND
t
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
2.7 V
0 V
Data
Input
Output
1.5 V
1.5 V
2.7 V
0 V
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
V
V
+ 0.3 V
1.5 V
OL
V
OL
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 3. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1999, Texas Instruments Incorporated
相关型号：
SN74ALVCH162344DLR
ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSOP-56
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