SN74ALVCH16952DL [TI]
16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS; 16位寄存收发器与3态输出
| 型号： | SN74ALVCH16952DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
1OEAB
1CLKAB
1CLKENAB
GND
1OEBA
1
56
2
55 1CLKBA
54 1CLKENBA
53 GND
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
3
4
1A1
5
52 1B1
Latch-Up Performance Exceeds 500 mA Per
JESD 17
1A2
6
51 1B2
V
7
50
V
CC
CC
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
8
49 1B3
48 1B4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This 16-bit registered transceiver is designed for
1.65-V to 3.6-V V operation.
CC
The SN74ALVCH16952 contains two sets of
D-type flip-flops for temporary storage of data
flowing in either direction. This device can be used
as two 8-bit transceivers or one 16-bit transceiver.
Data on the A or B bus is stored in the registers on
the low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB or CLKENBA) input is low. Taking the
output-enable (OEAB or OEBA) input low
accesses the data on either port.
V
V
CC
CC
2A7
2A8
GND
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
2CLKENAB
2CLKAB
2OEAB
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
The SN74ALVCH16952 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
†
FUNCTION TABLE
INPUTS
OUTPUT
B
A
X
X
L
CLKENAB CLKAB
OEAB
‡
B
0
‡
B
0
H
X
L
X
L
↑
L
L
L
L
H
L
H
Z
L
↑
H
X
X
X
†
‡
A-to-Bdataflowisshown;B-to-Adataflowissimilar, but
uses CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input
conditions were established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
†
logic symbol
56
1OEBA
EN3
G1
54
55
1
1CLKENBA
1CLKBA
1C5
EN4
G2
1OEAB
3
1CLKENAB
1CLKAB
2
2C6
29
EN9
G7
2OEBA
31
30
28
2CLKENBA
2CLKBA
7C11
2OEAB
EN10
G8
26
27
2CLKENAB
2CLKAB
8C12
5
52
1A1
3
5D
4
1B1
6D
6
51
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
49
8
1B3
48
9
1B4
47
10
12
13
14
15
1B5
45
1B6
44
1B7
43
1B8
42
9
11D
10
2B1
12D
16
17
19
20
21
23
24
41
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
40
2B3
38
2B4
37
2B5
36
2B6
34
2B7
33
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
logic diagram (positive logic)
3
54
1CLKENAB
1CLKENBA
1CLKBA
1OEAB
2
55
1
1CLKAB
56
1OEBA
One of Eight
Channels
C1
CE
1D
52
5
1B1
1A1
C1
CE
1D
To Seven Other Channels
26
31
30
28
2CLKENBA
2CLKBA
2CLKENAB
27
2CLKAB
29
2OEBA
2OEAB
One of Eight
Channels
C1
CE
1D
42
15
2B1
2A1
C1
CE
1D
To Seven Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V : Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed..
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
V
Supply voltage
3.6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
–4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–12
–12
–24
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
12
I
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
T
A
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
I
= –100 µA
= –4 mA
= –6 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
OH
OH
CC
1.2
2
V
OH
2.3 V
1.7
2.2
2.4
2
V
I
= –12 mA
2.7 V
OH
3 V
I
I
I
I
= –24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.4
= 6 mA
V
OL
V
2.3 V
0.7
I
= 12 mA
OL
2.7 V
0.4
I
= 24 mA
3 V
0.55
±5
OL
I
I
V = V
or GND
3.6 V
µA
I
CC
V = 0.58 V
1.65 V
1.65 V
2.3 V
25
–25
45
I
V = 1.07 V
I
V = 0.7 V
I
I
V = 1.7 V
2.3 V
–45
75
µA
I(hold)
I
V = 0.8 V
I
3 V
V = 2 V
I
3 V
–75
‡
V = 0 to 3.6 V
3.6 V
±500
±10
40
I
§
I
I
V
O
= V
or GND
CC
or GND,
3.6 V
µA
µA
µA
pF
pF
OZ
V = V
I
I = 0
O
3.6 V
CC
CC
∆I
CC
One input at V
– 0.6 V,
Other inputs at V
CC
or GND
3 V to 3.6 V
3.3 V
750
CC
or GND
C
C
Control inputs V = V
3.5
8.5
i
I
CC
= V
A or B ports
V
or GND
3.3 V
io
O
CC
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
For I/O ports, the parameter I
OZ
includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 1.8 V
V
CC
= 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
¶
f
t
Clock frequency
Pulse duration
150
150
150
MHz
ns
clock
¶
¶
¶
¶
¶
CLKEN high
3.3
3.3
1.7
1.2
0.6
3.3
3.3
1.9
1
3.3
3.3
1.5
1
w
CLK high or low
Data before CLK
CLKEN before CLK
Data after CLK
t
Setup time
Hold time
ns
ns
su
h
0.6
0.8
t
¶
CLKEN after CLK
1.1
0.9
1.1
¶
This information was not available at the time of publication.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
V
= 1.8 V
V
= 2.7 V
MAX
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
PARAMETER
UNIT
MIN
TYP
MIN
150
1
MAX
MIN
MIN
150
1
MAX
†
f
t
t
t
150
MHz
ns
max
†
†
†
CLK
A or B
A or B
A or B
4.1
5.4
5.3
4.6
5.3
4.4
3.9
4.4
4
pd
1
1
ns
OEBA or OEAB
OEBA or OEAB
en
1
1.1
ns
dis
†
This information was not available at the time of publication.
operating characteristics, T = 25°C
A
V
= 1.8 V
CC
TYP
V
= 2.5 V
CC
TYP
V = 3.3 V
CC
PARAMETER
TEST CONDITIONS
UNIT
TYP
†
†
Outputs enabled
Outputs disabled
53
34
71
40
Power dissipation
capacitance
C
C
= 0,
L
f = 10 MHz
pF
pd
†
This information was not available at the time of publication.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
CC
Open
S1
1 kΩ
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
1 kΩ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16952
16-BIT REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES011D – JULY 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
TEST
S1
S1
500 Ω
Open
GND
From Output
Under Test
t
Open
6 V
pd
/t
t
PLZ PZL
/t
C
= 50 pF
L
t
GND
PHZ PZH
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
Output
1.5 V
1.5 V
2.7 V
0 V
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
– 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
(see Note B)
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
dis
are the same as t
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
10
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