SN74ALVTH162245DGVR [TI]
IC,BUS TRANSCEIVER,DUAL,8-BIT,LVT/ALVT-BICMOS,TSSOP,48PIN,PLASTIC;
| 型号： | SN74ALVTH162245DGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,BUS TRANSCEIVER,DUAL,8-BIT,LVT/ALVT-BICMOS,TSSOP,48PIN,PLASTIC 信息通信管理 光电二极管 |
| 文件： | 总10页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
SN54ALVTH162245 . . . WD PACKAGE
SN74ALVTH162245 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
Support Mixed-Mode Signal Operation (5-V
2
Input and Output Voltages With 3.3-V V
)
CC
3
Typical V
<0.8 V at V
(Output Ground Bounce)
4
OLP
CC
= 3.3 V, T = 25°C
5
A
6
I
and Power-Up 3-State Support Hot
off
7
V
V
Insertion
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A-Port Outputs Have Equivalent 30-Ω
Series Resistors, So No External Resistors
Are Required
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
+ 0.5 V
CC
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
V
V
CC
CC
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
CC
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
2DIR
NOTE: For order entry:
The DGG package is abbreviated to G, and
the DGV package is abbreviated to V.
For tape and reel:
The DGGR package is abbreviated to GR,
the DGVR package is abbreviated to VR, and
the DLR package is abbreviated to LR.
description
The’ALVTH162245 devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for 2.5-V or 3.3-V
operation, but with the capability to provide a TTL interface to a 5-V system environment.
V
CC
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively
isolated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
description (continued)
The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 30-Ω series resistors
to reduce overshoot and undershoot.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
When V
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH162245 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH162245 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
logic diagram (positive logic)
1
24
1DIR
2DIR
48
25
13
1OE
1B1
2OE
2B1
47
36
1A1
2A1
2
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Output current in the low state, I : SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Output current in the high state, I : SN54ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –48 mA
O
SN74ALVTH162245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –64 mA
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions, V
= 2.5 V ± 0.2 V (see Note 3)
CC
SN54ALVTH162245
SN74ALVTH162245
MIN TYP MAX
UNIT
MIN
2.3
TYP
MAX
V
V
V
V
Supply voltage
2.7
2.3
1.7
2.7
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
1.7
IH
0.7
5.5
–6
6
0.7
5.5
–8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
mA
mA
OH
12
OL
Outputs
enabled
∆t/∆v
∆t/∆V
Input transition rise or fall rate
10
10
ns/V
Power-up ramp rate
200
–55
200
–40
µs/V
°C
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
recommended operating conditions, V
= 3.3 V ± 0.3 V (see Note 3)
CC
SN54ALVTH162245
SN74ALVTH162245
MIN TYP MAX
UNIT
MIN
3
TYP
MAX
V
V
V
V
Supply voltage
3.6
3
2
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
2
IH
0.8
5.5
–24
24
0.8
5.5
–12
12
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
mA
mA
OH
OL
Outputs
enabled
∆t/∆v
∆t/∆V
Input transition rise or fall rate
10
10
ns/V
Power-up ramp rate
200
–55
200
–40
µs/V
°C
CC
T
A
Operating free-air temperature
125
85
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
electrical characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted)
V
CC
SN54ALVTH162245
SN74ALVTH162245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 2.3 V to 2.7 V,
I
I
I
I
I
I
I
I
= –100 µA
= –6 mA
= –8 mA
= 100 µA
= 6 mA
V
–0.2
CC
1.7
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
CC
V
V
OH
V
V
= 2.3 V
CC
1.7
= 2.3 V to 2.7 V,
0.2
0.4
0.2
0.4
CC
V
OL
= 8 mA
V
CC
= 2.3 V
= 18 mA
= 24 mA
0.5
0.5
±1
V
V
= 2.7 V,
V = GND
I
±1
10
10
1
CC
Control inputs
A or B ports
= 0 or 2.7 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
10
µA
V
CC
= 2.7 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 2.3 V,
= 2.3 V,
= 2.7 V,
= 2.7 V,
= 2.3 V,
V = 0.7 V
I
115
–10
115
–10
BHL
§
V = 1.7 V
I
BHH
¶
V = 0 to V
300
–300
300
–300
BHLO
I
CC
CC
#
V = 0 to V
I
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.04
2.3
0.1
4.5
0.1
0.04
2.3
0.1
4.5
0.1
V
I
= 2.7 V,
= 0,
CC
O
I
mA
V = V
I
or GND
CC
Outputs disabled
0.04
0.04
C
C
V
V
= 2.5 V,
= 2.5 V,
V = 2.5 V or 0
pF
pF
i
CC
I
V
O
= 2.5 V or 0
io
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 2.5 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
¶
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
High-impedance state during power up or power down
O
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
electrical characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted)
CC
SN54ALVTH162245
SN74ALVTH162245
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 3 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 3 V to 3.6 V,
I
I
I
I
I
I
I
I
I
= –100 µA
= –24 mA
= –32 mA
= 100 µA
= 16 mA
= 24 mA
= 32 mA
= 48 mA
= 64 mA
V
CC
–0.2
2
V
CC
–0.2
2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
V
V
= 3 V
CC
= 3 V to 3.6 V,
0.2
0.5
0.2
0.4
CC
V
OL
V
CC
= 3 V
0.5
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
20
1
CC
CC
Control inputs
A or B ports
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
V
CC
= 3.6 V
V = V
I CC
1
V = 0
I
–5
–5
I
I
I
I
I
I
V
V
V
V
V
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
µA
µA
µA
µA
off
CC
CC
CC
CC
CC
CC
CC
I
O
‡
= 3 V,
= 3 V,
= 3.6 V,
= 3.6 V,
= 3 V,
V = 0.8 V
I
75
75
BHL
§
V = 2 V
I
–75
500
–75
500
BHH
¶
V = 0 to V
BHLO
I
CC
CC
#
V = 0 to V
I
–500
–500
BHHO
||
V
O
= 5.5 V
125
125
EX
≤ 1.2 V, V = 0.5 V to V
CC
,
O
CC
±100
±100
µA
mA
mA
I
OZ(PU/PD)
CC
V = GND or V , OE = don’t care
I
Outputs high
Outputs low
0.07
3.2
0.1
5
0.07
3.2
0.1
5
V
I
= 3.6 V,
= 0,
CC
O
I
V = V
I
or GND
CC
Outputs disabled
0.07
0.1
0.07
0.1
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
0.2
0.2
∆I
CC
or GND
CC
C
C
V
V
= 3.3 V,
= 3.3 V,
V = 3.3 V or 0
pF
pF
i
CC
I
V
O
= 3.3 V or 0
io
CC
†
‡
All typical values are at V
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
= 3.3 V, T = 25°C.
A
CC
should be measured after lowering V to GND and
BHL IN
IL
then raising it to V max.
IL
§
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
An external driver must source at least I
An external driver must sink at least I
BHHO
Current into an output in the high state when V > V
¶
#
||
to switch this node from low to high.
BHLO
to switch this node from high to low.
O
CC
High-impedance state during power up or power down
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
switching characteristics over recommended operating free-air temperature range, C = 30 pF,
L
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
SN54ALVTH162245
MIN MAX
SN74ALVTH162245
†
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP
MAX
t
t
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
en
dis
OE
†
All typical values are at V
= 2.5 V, T = 25°C.
A
CC
switching characteristics over recommended operating free-air temperature range, C = 50 pF,
L
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
CC
SN54ALVTH162245
MIN MAX
SN74ALVTH162245
‡
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP
MAX
t
t
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
en
dis
OE
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t
D. The outputs are measured one at a time with one transition per measurement.
2 ns, t
f
2 ns.
O
r
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALVTH162245, SN74ALVTH162245
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES331 – APRIL 2000
PARAMETER MEASUREMENT INFORMATION
V
= 3.3 V ± 0.3 V
CC
6 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
6 V
pd
/t
C
= 50 pF
t
L
PLZ PZL
500 Ω
(see Note A)
t
/t
GND
PHZ PZH
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
1.5 V
Input
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
1.5 V
1.5 V
Input
V
V
+ 0.3 V
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Allinput pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 Ω, t
D. The outputs are measured one at a time with one transition per measurement.
2.5 ns, t
f
2.5 ns.
O
r
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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Copyright 2000, Texas Instruments Incorporated
相关型号：
SN74ALVTH16240DLR
ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, SSOP-48
TI
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