SN74AS825ANTE4 [TI]
AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-24;
| 型号： | SN74AS825ANTE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-24 驱动 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢀ ꢅ ꢆ ꢂꢄ ꢇꢈ ꢀꢁꢉ ꢃꢄ ꢀ ꢅꢆ ꢂꢄ
ꢅ ꢊꢋꢌ ꢍꢈ ꢋꢎꢀ ꢊꢌꢁꢍ ꢏꢐꢑꢄꢒꢏ ꢈꢑ ꢓꢌ ꢔ ꢊꢑ ꢓꢕ ꢔ ꢀ
ꢖ ꢌꢍ ꢗꢈ ꢘ ꢊꢀꢍꢄꢍ ꢏꢈ ꢕ ꢎꢍ ꢔꢎ ꢍꢀ
SDAS020B − JUNE 1984 − REVISED AUGUST 1995
SN54AS825A . . . JT PACKAGE
SN74AS825A . . . DW OR NT PACKAGE
(TOP VIEW)
• Functionally Equivalent to AMD’s AM29825
Specifications
• Improved I
OH
• Multiple Output Enables Allow Multiuser
Control of the Interface
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
V
CC
1
2
3
4
5
6
7
8
9
24
23 OE3
22 1Q
21 2Q
20 3Q
19 4Q
18 5Q
17 6Q
16 7Q
15 8Q
14 CLKEN
13 CLK
• Outputs Have Undershoot-Protection
Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce dc
Loading Effects
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
8D 10
CLR 11
GND 12
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. These devices
are particularly suitable for implementing
multiuser registers, I/O ports, bidirectional bus
drivers, and working registers.
SN54AS825A . . . FK PACKAGE
(TOP VIEW)
4
3
2
1
28 27 26
25
2D
3D
4D
NC
5D
6D
7D
2Q
3Q
4Q
NC
5Q
6Q
7Q
5
With the clock-enable (CLKEN) input low, the
eight D-type edge-triggered flip-flops enter data
on the low-to-high transitions of the clock (CLK)
input. Taking CLKEN high disables the clock
buffer, latching the outputs. These devices have
noninverting data (D) inputs. Taking the clear
(CLR) input low causes the eight Q outputs to go
low independently of the clock.
24
23
22
21
20
19
6
7
8
9
10
11
12 13 14 15 16 17 18
Multiuser buffered output-enable (OE1, OE2, and
OE3) inputs can be used to place the eight outputs
in either a normal logic state (high or low logic
NC − No internal connection
level) or
a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-
impedance state and increased drive provide the
capability to drive bus lines without interface or
pullup components.
The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
The SN54AS825A is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74AS825A is characterized for operation from 0°C to 70°C.
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Copyright 1995, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢆꢂ ꢄꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅ ꢆ ꢂ ꢄ
ꢅ ꢊꢋ ꢌ ꢍ ꢈꢋ ꢎ ꢀꢊꢌ ꢁ ꢍꢏ ꢐꢑꢄꢒ ꢏꢈ ꢑ ꢓꢌ ꢔ ꢊꢑꢓ ꢕ ꢔꢀ
ꢖꢌ ꢍ ꢗ ꢈꢘ ꢊꢀ ꢍꢄꢍꢏ ꢈ ꢕ ꢎꢍ ꢔꢎꢍ ꢀ
SDAS020B − JUNE 1984 − REVISED AUGUST 1995
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
†
OE
CLR CLKEN CLK
D
X
H
L
L
L
L
L
H
L
H
H
H
X
X
L
X
↑
↑
X
X
L
H
L
L
H
X
X
X
Q
0
Z
†
OE = H if any of OE1, OE2, or OE3 are high.
OE = L if all of OE1, OE2, or OE3 are low.
‡
logic symbol
1
&
OE1
OE2
OE3
CLR
2
EN
23
11
R
14
13
G1
CLKEN
CLK
1C2
3
22
1D
2D
1Q
4
21
20
19
18
17
16
15
2D
3D
4D
5D
6D
7D
8D
2Q
3Q
4Q
5Q
6Q
7Q
8Q
5
6
7
8
9
10
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢀ ꢅ ꢆ ꢂꢄ ꢇꢈ ꢀꢁ ꢉꢃꢄ ꢀ ꢅꢆ ꢂꢄ
ꢅ ꢊꢋꢌ ꢍꢈ ꢋꢎꢀ ꢊꢌꢁꢍ ꢏꢐ ꢑꢄꢒꢏ ꢈꢑ ꢓ ꢌ ꢔꢊ ꢑꢓꢕ ꢔ ꢀ
ꢖ ꢌꢍ ꢗꢈ ꢘ ꢊꢀꢍꢄꢍ ꢏꢈ ꢕ ꢎꢍ ꢔꢎ ꢍꢀ
SDAS020B − JUNE 1984 − REVISED AUGUST 1995
logic diagram (positive logic)
1
OE1
2
OE2
23
OE3
11
CLR
14
CLKEN
R
13
CLK
22
C1
1D
1Q
3
1D
To Seven Other Channels
Pin numbers shown are for the DW, JT, and NT packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, T : SN54AS825A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
SN74AS825A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢆꢂ ꢄꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅ ꢆ ꢂ ꢄ
ꢅ ꢊꢋ ꢌ ꢍ ꢈꢋ ꢎ ꢀꢊꢌ ꢁ ꢍꢏ ꢐꢑꢄꢒ ꢏꢈ ꢑ ꢓꢌ ꢔ ꢊꢑꢓ ꢕ ꢔꢀ
ꢖꢌ ꢍ ꢗ ꢈꢘ ꢊꢀ ꢍꢄꢍꢏ ꢈ ꢕ ꢎꢍ ꢔꢎꢍ ꢀ
SDAS020B − JUNE 1984 − REVISED AUGUST 1995
recommended operating conditions
SN54AS825A
MIN NOM MAX
SN74AS825A
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
IH
0.7
−24
32
0.8
−24
48
V
IL
I
I
mA
mA
OH
OL
CLR low
7
9.5
8
4
8
8
6
6
0
0
t *
Pulse duration
ns
w
CLK high or low
CLR inactive
Data
7
t *
su
ns
Setup time before CLK↑
CLKEN high or low
CLKEN low or data
10
0
t *
h
Hold time after CLK↑
ns
T
A
Operating free-air temperature
−55
125
70
°C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS825A
SN74AS825A
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
IK
V
V
= 4.5 V,
−1.2
−1.2
V
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
= −2 mA
= −15 mA
= −24 mA
= 32 mA
= 48 mA
= 2.7 V
V
−2
V
−2
CC
OH
OH
OH
OL
OL
CC
2.4
CC
2.4
3.2
0.3
3.2
V
OH
V
V
= 4.5 V
= 4.5 V
CC
CC
2
2
0.5
V
OL
V
V
0.35
0.5
50
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
O
50
−50
0.1
µA
µA
OZH
OZL
I
V = 0.4 V
I
−50
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
20
IH
V = 0.4 V
I
−0.5
−112
73
−0.5
−112
73
mA
mA
IL
‡
V
O
= 2.25 V
−30
−30
O
Outputs high
Outputs low
45
56
59
45
56
59
I
V
CC
= 5.5 V
90
90
mA
CC
Outputs disabled
95
95
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢀ ꢅ ꢆ ꢂꢄ ꢇꢈ ꢀꢁ ꢉꢃꢄ ꢀ ꢅꢆ ꢂꢄ
ꢅ ꢊꢋꢌ ꢍꢈ ꢋꢎꢀ ꢊꢌꢁꢍ ꢏꢐ ꢑꢄꢒꢏ ꢈꢑ ꢓ ꢌ ꢔꢊ ꢑꢓꢕ ꢔ ꢀ
ꢖ ꢌꢍ ꢗꢈ ꢘ ꢊꢀꢍꢄꢍ ꢏꢈ ꢕ ꢎꢍ ꢔꢎ ꢍꢀ
SDAS020B − JUNE 1984 − REVISED AUGUST 1995
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
UNIT
†
= MIN to MAX
SN54AS825A SN74AS825A
MIN
3.5
3.5
3.5
4
MAX
9
MIN
3.5
3.5
3.5
4
MAX
7.5
13
t
t
t
t
t
t
t
PLH
PHL
PHL
PZH
PZL
PHZ
PLZ
CLK
CLR
ns
ns
Any Q
Any Q
13.5
16.5
12
15.5
11
ns
ns
OE
OE
Any Q
Any Q
4
13
4
12
1
10
1.5
1.5
8
1
10
8
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢆꢂ ꢄꢇ ꢈ ꢀ ꢁꢉ ꢃ ꢄꢀ ꢅ ꢆ ꢂ ꢄ
ꢅ ꢊꢋ ꢌ ꢍ ꢈꢋ ꢎ ꢀꢊꢌ ꢁ ꢍꢏ ꢐꢑꢄꢒ ꢏꢈ ꢑ ꢓꢌ ꢔ ꢊꢑꢓ ꢕ ꢔꢀ
ꢖꢌ ꢍ ꢗ ꢈꢘ ꢊꢀ ꢍꢄꢍꢏ ꢈ ꢕ ꢎꢍ ꢔꢎꢍ ꢀ
SDAS020B − JUNE 1984 − REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
t
w
h
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
[3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
[0 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9078003M3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9078003M3A
SNJ54AS
825AFK
5962-9078003MKA
5962-9078003MLA
SNJ54AS825AFK
ACTIVE
ACTIVE
ACTIVE
CFP
CDIP
LCCC
W
JT
FK
24
24
28
1
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
5962-9078003MK
A
SNJ54AS825AW
5962-9078003ML
A
SNJ54AS825AJT
POST-PLATE
5962-
9078003M3A
SNJ54AS
825AFK
SNJ54AS825AJT
SNJ54AS825AW
ACTIVE
ACTIVE
CDIP
CFP
JT
W
24
24
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9078003ML
A
SNJ54AS825AJT
5962-9078003MK
A
SNJ54AS825AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
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Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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