SN74AUC16374_14 [TI]
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS;
| 型号： | SN74AUC16374_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总12页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCES403D–JULY 2002–REVISED JUNE 2005
FEATURES
DGG OR DGV PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1CLK
1D1
1D2
GND
1D3
1D4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
•
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
2
3
4
•
Ioff Supports Partial-Power-Down Mode
Operation
5
6
•
•
•
•
•
Sub-1-V Operable
V
CC
7
V
CC
Max tpd of 2 ns at 1.8 V
8
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
Low Power Consumption, 20-µA Max ICC
±8-mA Output Drive at 1.8 V
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
V
CC
V
CC
DESCRIPTION/ORDERING INFORMATION
2D5
2D6
GND
2D7
2D8
2CLK
2Q5
2Q6
GND
2Q7
2Q8
2OE
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V VCC, but is designed
specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74AUC16374DGGR
TOP-SIDE MARKING
AUC16374
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL(2)
Tape and reel
–40°C to 85°C
Tape and reel
Tape and reel
SN74AUC16374DGVR
SN74AUC16374GQLR
MH374
MH374
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) Package preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCES403D–JULY 2002–REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
GQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1CLK
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2CLK
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
VCC
GND
GND
VCC
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
G
H
J
K
K
(1) NC - No internal connection
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
H
L
L
↑
H or L
X
L
X
X
Q0
Z
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
24
2OE
1OE
25
48
2CLK
1CLK
C1
1D
C1
2
13
2Q1
1Q1
47
36
2D1
1D1
1D
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
To Seven Other Channels
2
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCES403D–JULY 2002–REVISED JUNE 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
3.6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2)
3.6
V
VO
VO
IIK
3.6
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±20
±100
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DGG package
DGV package
GQL package
θJA
Package thermal impedance(3)
58
°C/W
°C
42
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
0.8
MAX UNIT
VCC
Supply voltage
2.7
V
VCC = 0.8 V
VCC
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
0.65 × VCC
1.7
V
0
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.35 × VCC
V
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
Low-level output current
mA
mA
IOL
5
8
9
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
20
85
ns/V
°C
TA
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCES403D–JULY 2002–REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
0.8 V
MIN TYP(1) MAX UNIT
IOH = –100 µA
IOH = –0.7 mA
IOH = –3 mA
VCC – 0.1
0.55
1.1 V
0.8
1
VOH
V
V
IOH = –5 mA
1.4 V
IOH = –8 mA
1.65 V
2.3 V
1.2
1.8
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
0.4
VOL
IOL = 5 mA
1.4 V
IOL = 8 mA
1.65 V
2.3 V
0.45
0.6
IOL = 9 mA
II
All inputs
VI = VCC or GND
VI or VO = 2.7 V
VO = VCC or GND
VI = VCC or GND,
VI = VCC or GND
VO = VCC or GND
0 to 2.7 V
0
±5
µA
µA
µA
µA
pF
pF
Ioff
IOZ
ICC
Ci
±10
±10
20
2.7 V
IO = 0
0.8 V to 2.7 V
2.5 V
3
5
Co
2.5 V
(1) All typical values are at TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 0.8 V
UNIT
TYP
85
MIN
MAX
250
MIN
MAX
250
MIN
MAX
250
MIN
MAX
250
fclock
tw
Clock frequency
MHz
ns
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
5.9
1.4
0.1
1.9
1.2
0.4
1.9
0.7
0.4
1.9
0.6
0.4
1.9
0.6
0.4
tsu
th
ns
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.2 V VCC = 1.5 V
± 0.1 V ± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
85
MIN MAX MIN MAX MIN TYP MAX MIN MAX
fmax
tpd
250
1
250
0.8
0.8
1
250
0.7
0.8
1.4
250
0.7
0.7
0.5
MHz
ns
CLK
OE
Q
Q
Q
7.3
7
4.5
5.3
7.1
2.9
3.6
4.8
1.5
1.5
2.7
2.8
2.9
4.5
2.2
2.2
2.2
ten
1.2
2
ns
tdis
OE
8.2
ns
4
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCES403D–JULY 2002–REVISED JUNE 2005
Operating Characteristics(1)
TA = 25°C
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V
VCC = 2.5 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
TYP
1 fdata = 5 MHz,
1 fclk = 10 MHz,
1 fout = 5 MHz,
OE = GND,
Outputs
enabled,
1 output
switching
Cpd
Power
dissipation
(each
24
24
24.1
26.2
31.2
pF
output)(2) capacitance
CL = 0 pF
Outputs
1 fdata = 5 MHz,
disabled, 1 fclk = 10 MHz,
Power
dissipation
capacitance
1 clock
and 1
data
fout = not
switching,
OE = VCC
Cpd(Z)
7.5
7.5
8
9.4
13.2
pF
pF
,
switching CL = 0 pF
1 fdata = 0 MHz,
1 fclk = 10 MHz,
fout = not
Outputs
disabled,
clock
Cpd
(each
Power
dissipation
13.8
13.8
14
14.7
17.5
switching,
clock)(3) capacitance only
OE = VCC
CL = 0 pF
,
switching
(1) Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}
(2) Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz
in this test, but its ICC component has been subtracted out).
(3) Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
5
SN74AUC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCES403D–JULY 2002–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
S1
TEST
/t
S1
Open
GND
R
L
From Output
Under Test
t
Open
PLH PHL
t
t
/t
2 × V
CC
GND
PLZ PZL
C
L
/t
R
L
PHZ PZH
(see Note A)
C
L
V
∆
R
L
V
CC
0.8 V
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
0.1 V
0.1 V
0.1 V
15 pF
15 pF
15 pF
30 pF
30 pF
LOAD CIRCUIT
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.15 V
0.15 V
V
CC
Timing Input
V /2
CC
0 V
t
w
t
su
t
h
V
CC
V
CC
V /2
CC
V /2
CC
Input
V /2
CC
V /2
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
V /2
CC
V /2
CC
V /2
CC
V /2
CC
Input
0 V
0 V
t
t
t
PLZ
t
t
PHL
PZL
PLH
Output
Waveform 1
V
V
V
CC
OH
V
/2
/2
V
V
/2
/2
V
CC
/2
CC
CC
Output
V
+ V
PHZ
∆
OL
S1 at 2 × V
CC
V
OL
OL
(see Note B)
t
t
PZH
t
PHL
PLH
/2
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
− V
∆
OH
V
CC
V
CC
CC
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
PACKAGING INFORMATION
Orderable Device
74AUC16374DGGRE4
74AUC16374DGVRE4
SN74AUC16374DGGR
SN74AUC16374DGVR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TSSOP
TVSOP
DGV
DGG
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AUC16374GQLR
SN74AUC16374ZQLR
ACTIVE
ACTIVE
VFBGA
VFBGA
GQL
ZQL
56
56
1000
TBD
SNPB
Level-1-240C-UNLIM
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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amplifier.ti.com
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dataconverter.ti.com
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
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www.ti.com/wireless
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