SN74AUC1G125DRYR [TI]
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT; 具有三态输出单总线缓冲器门
| 型号： | SN74AUC1G125DRYR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT |
| 文件： | 总12页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES382K–MARCH 2002–REVISED APRIL 2007
FEATURES
•
Available in the Texas Instruments
NanoFree™ Package
•
•
•
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 1.8 V
•
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
ESD Protection Exceeds JESD 22
•
Ioff Supports Partial-Power-Down Mode
Operation
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
•
•
Sub-1-V Operable
1000-V Charged-Device Model (C101)
Max tpd of 2.5 ns at 1.8 V
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRY PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
3
2
1
4
Y
VCC
GND
A
OE
A
1
2
3
6
5
4
1
2
3
5
OE
A
VCC
NC
Y
1
2
3
5
OE
A
VCC
5
VCC
OE
GND
4
GND
Y
4
Y
GND
NC – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable
(OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SON – DRY
Reel of 3000
SN74AUC1G125YZPR
_ _ _UM_
Reel of 5000
Reel of 3000
Reel of 3000
SN74AUC1G125DRYR
SN74AUC1G125DBVR
SN74AUC1G125DCKR
PREVIEW
U25_
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
UM_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
Copyright © 2002–2007, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES382K–MARCH 2002–REVISED APRIL 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
2
4
A
Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
3.6
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2)
3.6
V
VO
VO
IIK
3.6
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±20
±100
206
252
234
132
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DBV package
DCK package
DRY package
YZP package
θJA
Package thermal impedance(3)
°C/W
°C
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES382K–MARCH 2002–REVISED APRIL 2007
Recommended Operating Conditions(1)
MIN
0.8
MAX UNIT
VCC
Supply voltage
2.7
V
VCC = 0.8 V
VCC
VIH
High-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
0.65 × VCC
1.7
V
0
VIL
Low-level input voltage
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
0.35 × VCC
V
0.7
3.6
VCC
–0.7
–3
–5
–8
–9
0.7
3
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 0.8 V
VCC = 1.1 V
IOH
High-level output current
Low-level output current
VCC = 1.4 V
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 0.8 V
VCC = 1.1 V
IOL
VCC = 1.4 V
5
VCC = 1.65 V
VCC = 2.3 V
8
9
VCC = 0.8 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
20
10
3
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES382K–MARCH 2002–REVISED APRIL 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
0.8 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 µA
IOH = –0.7 mA
IOH = –3 mA
IOH = –5 mA
IOH = –8 mA
IOH = –9 mA
IOL = 100 µA
IOL = 0.7 mA
IOL = 3 mA
0.55
1.1 V
0.8
1
VOH
V
1.4 V
1.65 V
2.3 V
1.2
1.8
0.8 V to 2.7 V
0.8 V
0.2
0.25
1.1 V
0.3
V
VOL
IOL = 5 mA
1.4 V
0.4
IOL = 8 mA
1.65 V
2.3 V
0.45
0.6
IOL = 9 mA
II
A or OE input VI = VCC or GND
VI or VO = 2.7 V
0 to 2.7 V
0
±5
±10
±10
10
µA
µA
µA
µA
pF
pF
Ioff
IOZ
ICC
CI
VO = VCC or GND
2.7 V
VI = VCC or GND,
IO = 0
0.8 V to 2.7 V
2.5 V
VI = VCC or GND
2.5
5.5
Co
VO = VCC or GND
2.5 V
(1) All typical values are at TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.2 V VCC = 1.5 V
± 0.1 V ± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 0.8 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
4.7
5.4
4.8
MIN MAX MIN MAX MIN
TYP MAX MIN MAX
tpd
ten
tdis
A
Y
Y
Y
0.8
0.7
1.4
3.6
4.1
4.3
0.4
0.5
1.4
2.3
2.6
4
0.6
0.6
1.5
1
1.1
2.2
1.5
1.8
2.9
0.5
0.5
0.9
1.3
1.4
2.2
ns
ns
ns
OE
OE
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN TYP MAX MIN MAX
tpd
ten
tdis
A
Y
Y
Y
0.7
1
1.5
1.6
2.2
2.5
2.6
3.1
0.9
1.1
0.8
1.7
1.9
1.7
ns
ns
ns
OE
OE
1.8
Operating Characteristics
TA = 25°C
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
TYP
TYP
Outputs
enabled
14
14
14
15
16
Power
dissipation
capacitance
Cpd
f = 10 MHz
pF
Outputs
disabled
1.5
1.5
1.5
2
2.5
4
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SN74AUC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUT
www.ti.com
SCES382K–MARCH 2002–REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
2 × VCC
Open
GND
S1
RL
From Output
Under Test
CL
V
RL
VCC
CL
(see Note A)
D
RL
0.8 V
2 kW
2 kW
2 kW
2 kW
2 kW
1 kW
500 W
0.1 V
0.1 V
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
0.1 V
LOAD CIRCUIT
0.15 V
0.15 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0 V
tW
tsu
th
VCC
VCC
0 V
Input
VCC/2
VCC/2
Data Input
VCC/2
VCC/2
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
0 V
VCC
0 V
Output
Control
VCC/2
VCC/2
Input
VCC/2
VCC/2
tPZL
tPLZ
tPLH
tPHL
VCC/2
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VOL
VCC
VOL
VCC/2
VCC/2
Output
Output
VOL + V
D
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VCC/2
VCC/2
VCC/2
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W,
slew rate ³ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
5
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PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2007
PACKAGING INFORMATION
Orderable Device
74AUC1G125DBVRE4
74AUC1G125DCKRE4
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
DCK
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74AUC1G125DCKRG4
SN74AUC1G125DBVR
ACTIVE
ACTIVE
SC70
DCK
DBV
5
5
3000
TBD
Call TI
Call TI
SOT-23
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AUC1G125DCKR
SN74AUC1G125YZTR
ACTIVE
ACTIVE
SC70
DCK
YZT
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Apr-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
180
(mm)
SN74AUC1G125DBVR
SN74AUC1G125YZTR
DBV
YZT
5
5
HNT
9
8
3.23
1.1
3.17
1.6
1.37
0.7
4
4
8
8
Q3
Q1
ASEK
180
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74AUC1G125DBVR
SN74AUC1G125YZTR
DBV
YZT
5
5
HNT
200.0
220.0
200.0
220.0
30.0
34.0
ASEK
Pack Materials-Page 2
D: .88 mm + 30 µm
E: 1.38 mm + 30 µm
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