SN74AUC2G241YZPR [TI]

DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS; 双缓冲/驱动器,具有三态输出
SN74AUC2G241YZPR
型号: SN74AUC2G241YZPR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
双缓冲/驱动器,具有三态输出

驱动器 输出元件
文件: 总13页 (文件大小:263K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
FEATURES  
DCT OR DCU PACKAGE  
(TOP VIEW)  
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
1
2
3
4
8
7
6
5
1OE  
1A  
2Y  
V
CC  
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
2OE  
1Y  
2A  
GND  
Ioff Supports Partial-Power-Down Mode  
Operation  
Sub-1-V Operable  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Max tpd of 1.9 ns at 1.8 V  
Low Power Consumption, 10 µA at 1.8 V  
±8-mA Output Drive at 1.8 V  
4
3
2
1
5
6
7
8
GND  
2Y  
2A  
1Y  
1A  
1OE  
2OE  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC  
operation.  
The SN74AUC2G241 is designed specifically to improve the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and transmitters.  
The device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is  
low or 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high or 2OE is low,  
the outputs are in the high-impedance state.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
Tape and reel  
Tape and reel  
SN74AUC2G241YEPR  
_ _ _U2_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AUC2G241YZPR  
–40°C to 85°C  
SSOP – DCT  
Tape and reel  
Tape and reel  
SN74AUC2G241DCTR  
SN74AUC2G241DCUR  
U41_ _ _  
U2_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
DESCRIPTION/ORDERING INFORMATION (CONTINUED)  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is  
determined by the current-sinking/current-sourcing capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of  
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.  
FUNCTION TABLES  
INPUTS  
1OE  
OUTPUT  
1Y  
1A  
H
L
L
H
L
L
H
X
Z
INPUTS  
OUTPUT  
2Y  
2OE  
H
2A  
H
H
L
H
L
L
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
1OE  
6
3
2
1Y  
2Y  
1A  
7
5
2OE  
2A  
2
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
MAX  
3.6  
UNIT  
V
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Output voltage range(2)  
3.6  
V
VO  
VO  
IIK  
3.6  
V
–0.5 VCC + 0.5  
V
Input clamp current  
VI < 0  
–50  
–50  
±20  
±100  
220  
227  
102  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through VCC or GND  
DCT package  
θJA  
Package thermal impedance(3)  
DCU package  
°C/W  
°C  
YEP/YZP package  
Tstg  
Storage temperature range  
–65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) The package thermal impedance is calculated in accordance with JESD 51-7.  
3
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
Recommended Operating Conditions(1)  
MIN  
0.8  
MAX UNIT  
VCC  
Supply voltage  
2.7  
V
VCC = 0.8 V  
VCC  
VIH  
High-level input voltage  
VCC = 1.1 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 0.8 V  
0.65 × VCC  
1.7  
V
0
VIL  
Low-level input voltage  
VCC = 1.1 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
0.35 × VCC  
V
0.7  
3.6  
VCC  
3.6  
–0.7  
–3  
–5  
–8  
–9  
0.7  
3
VI  
Input voltage  
0
0
0
V
V
Active state  
VO  
Output voltage  
3-state  
VCC = 0.8 V  
VCC = 1.1 V  
IOH  
High-level output current  
Low-level output current  
VCC = 1.4 V  
mA  
mA  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 0.8 V  
VCC = 1.1 V  
IOL  
VCC = 1.4 V  
5
VCC = 1.65 V  
VCC = 2.3 V  
8
9
VCC = 0.8 V to 1.65 V(2)  
VCC = 1.65 V to 1.95 V(3)  
VCC = 2.3 V to 2.7 V(3)  
20  
20  
20  
85  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
ns/V  
°C  
TA  
–40  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
(2) The data was taken at CL = 15 pF, RL = 2 k(see Figure 1).  
(3) The data was taken at CL = 30 pF, RL = 500 (see Figure 1).  
4
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
MIN TYP(1) MAX UNIT  
VCC – 0.1  
IOH = –100 µA  
IOH = –0.7 mA  
IOH = –3 mA  
IOH = –5 mA  
IOH = –8 mA  
IOH = –9 mA  
IOL = 100 µA  
IOL = 0.7 mA  
IOL = 3 mA  
0.8 V to 2.7 V  
0.8 V  
0.55  
0.25  
1.1 V  
0.8  
1
VOH  
V
V
1.4 V  
1.65 V  
2.3 V  
1.2  
1.8  
0.8 V to 2.7 V  
0.8 V  
0.2  
1.1 V  
0.3  
0.4  
VOL  
IOL = 5 mA  
1.4 V  
IOL = 8 mA  
1.65 V  
2.3 V  
0.45  
0.6  
IOL = 9 mA  
II  
All inputs  
VI = VCC or GND  
VI or VO = 2.7 V  
0 to 2.7 V  
0
±5  
µA  
µA  
µA  
µA  
pF  
pF  
Ioff  
IOZ  
ICC  
Ci  
±10  
±10  
10  
VO = VCC or GND  
VI = VCC or GND,  
VI = VCC or GND  
VO = VCC or GND  
2.7 V  
IO = 0  
0.8 V to 2.7 V  
2.5 V  
2.5  
5.5  
Co  
2.5 V  
(1) All typical values are at TA = 25°C.  
Switching Characteristics  
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)  
VCC = 1.2 V VCC = 1.5 V  
± 0.1 V ± 0.1 V  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
± 0.2 V  
VCC = 0.8 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
TYP  
5.1  
5.9  
6.2  
MIN MAX MIN MAX MIN TYP MAX MIN MAX  
tpd  
ten  
tdis  
A
Y
Y
Y
1
1.2  
2.2  
3.5  
4.2  
4.8  
0.8  
1
2.3  
2.7  
4.4  
0.7  
0.9  
1
1.2  
1.3  
2.9  
1.9  
2
0.6  
0.8  
1.6  
1.4  
1.6  
3.3  
ns  
ns  
ns  
OE or OE  
OE or OE  
2.5  
4.2  
Switching Characteristics  
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)  
VCC = 1.8 V  
± 0.15 V  
VCC = 2.5 V  
± 0.2 V  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
TYP  
1.6  
1.7  
2.3  
MAX  
2.5  
MIN  
0.8  
1
MAX  
1.8  
2
tpd  
ten  
tdis  
A
Y
Y
Y
0.9  
1.1  
1.9  
ns  
ns  
ns  
OE or OE  
OE or OE  
2.8  
3.6  
0.9  
2.1  
5
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
Operating Characteristics  
TA = 25°C  
VCC = 0.8 V  
TYP  
VCC = 1.2 V  
TYP  
VCC = 1.5 V  
TYP  
VCC = 1.8 V  
TYP  
VCC = 2.5 V  
TEST  
PARAMETER  
UNIT  
CONDITIONS  
TYP  
Power dissipation  
capacitance  
Cpd  
f = 10 MHz  
16  
16  
16  
17  
18  
pF  
6
SN74AUC2G241  
DUAL BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES535ADECEMBER 2003REVISED MARCH 2005  
PARAMETER MEASUREMENT INFORMATION  
2 × V  
CC  
TEST  
/t  
PLH PHL  
S1  
Open  
2 × V  
S1  
Open  
GND  
R
L
t
t
From Output  
Under Test  
t
/t  
PLZ PZL  
CC  
/t  
GND  
PHZ PZH  
C
L
R
L
(see Note A)  
C
L
V
R
L
V
CC  
0.8 V  
2 k  
2 kΩ  
2 kΩ  
2 kΩ  
2 kΩ  
1 kΩ  
500 Ω  
0.1 V  
0.1 V  
0.1 V  
15 pF  
15 pF  
15 pF  
15 pF  
15 pF  
30 pF  
30 pF  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
LOAD CIRCUIT  
0.15 V  
0.15 V  
0.15 V  
0.15 V  
V
CC  
Timing Input  
V /2  
CC  
0 V  
t
w
t
su  
t
h
V
CC  
V
CC  
V /2  
CC  
V /2  
CC  
Input  
V /2  
CC  
V /2  
CC  
Data Input  
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
CC  
CC  
Output  
Control  
V
CC  
/2  
V
CC  
/2  
V /2  
CC  
V /2  
CC  
Input  
0 V  
V
0 V  
t
t
t
PLZ  
t
t
PHL  
PZL  
PLH  
Output  
Waveform 1  
V
OH  
CC  
V
/2  
/2  
V
V
/2  
/2  
V
CC  
/2  
CC  
CC  
Output  
S1 at 2 × V  
V
OL  
+ V  
PHZ  
CC  
V
OL  
V
OL  
(see Note B)  
t
t
PZH  
t
PHL  
PLH  
/2  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
OH  
V
OH  
- V  
V
CC  
V
CC  
CC  
Output  
0 V  
V
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , slew rate 1 V/ns.  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
6-Jun-2005  
PACKAGING INFORMATION  
Orderable Device  
74AUC2G241DCURE4  
SN74AUC2G241DCTR  
SN74AUC2G241DCUR  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
US8  
DCU  
8
8
8
3000  
3000  
3000  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
SM8  
US8  
DCT  
DCU  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
SN74AUC2G241YEPR  
SN74AUC2G241YZPR  
ACTIVE  
ACTIVE  
WCSP  
WCSP  
YEP  
YZP  
8
8
3000  
3000  
TBD  
SNPB  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Pb-Free  
(RoHS)  
SNAGCU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MPDS049B – MAY 1999 – REVISED OCTOBER 2002  
DCT (R-PDSO-G8)  
PLASTIC SMALL-OUTLINE PACKAGE  
0,30  
0,15  
M
0,13  
0,65  
8
5
0,15 NOM  
2,90  
2,70  
4,25  
3,75  
Gage Plane  
PIN 1  
INDEX AREA  
0,25  
1
4
0° – 8°  
0,60  
0,20  
3,15  
2,75  
1,30 MAX  
Seating Plane  
0,10  
0,10  
0,00  
4188781/C 09/02  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion  
D. Falls within JEDEC MO-187 variation DA.  
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DUAL 2-INPUT POSITIVE-OR GATE
TI

SN74AUC2G32DCUR

DUAL 2 INPUT POSITIVE OR GATE
TI

SN74AUC2G32DCURE4

DUAL 2-INPUT POSITIVE-OR GATE
TI

SN74AUC2G32DCURG4

DUAL 2-INPUT POSITIVE-OR GATE
TI

SN74AUC2G32YEPR

DUAL 2 INPUT POSITIVE OR GATE
TI

SN74AUC2G32YZPR

DUAL 2 INPUT POSITIVE OR GATE
TI

SN74AUC2G32YZTR

AUC SERIES, DUAL 2-INPUT OR GATE, PBGA8, ROHS COMPLIANT, DSBGA-8
TI

SN74AUC2G32_09

DUAL 2-INPUT POSITIVE-OR GATE
TI